KR101283752B1 - Method for converting analog to digital in successive approximation register analog to digital converter - Google Patents

Abstract

According to the present invention, a sample / holder for sampling an analog input signal for a predetermined time is compared with a predicted input voltage based on the sampled input voltage for a predetermined time and an input voltage sampled at the sample / holder. A comparator, a digital-to-analog converter (DAC) for converting an input voltage predicted based on the sampled input voltage for a predetermined time into an analog signal and inputting the same to the comparator; An analog-digital control circuit comprising a control logic for predicting an input voltage of an analog input signal, inputting the digital-to-analog converter, checking a comparison result of the comparator, and outputting an N bit digital signal corresponding to the comparison result if the comparison result is matched. It relates to an analog-to-digital conversion method in a converter. According to the present invention, the analog input signal voltage is predicted to reduce the time for converting the actual sampled input voltage into a digital signal, and the power consumption of the analog circuit is reduced by using a power gating method after the analog-digital signal conversion. There is an effect that can be reduced.

Description

Analog-to-digital conversion method in SAR-type analog-to-digital converter {Method for converting analog to digital in successive approximation register analog to digital converter}

The present invention relates to an analog-to-digital conversion device, and more particularly, to an analog-to-digital conversion method of a successive access register (SAR) method.

First, the analog-to-digital conversion principle is briefly described. An analog-to-digital converter (hereinafter, referred to as an ADC) is an analog-type input signal that is converted into a digital value by comparing it with an internally divided reference voltage. In other words, this means converting an analog input signal into a digital output signal.

These ADCs include flash-type ADCs, ADCs using tracking techniques, and ADCs of successive approximation register types (hereinafter referred to as SAR-ADC), among which are SAR-type ADCs. Has been applied most recently.

A typical SAR-ADC is a comparator that receives and compares an analog input signal Vin and an internal subdivided analog reference voltage Vdac, and digital output bit values sequentially from the most significant bit MSB in response to the comparison result of the comparator. And a SAR register for determining a digital signal, a digital to analog converter (DAC) for converting the value of the SAR register into an analog reference voltage (Vdac) and inputting the same to the comparator, and a control unit for controlling the operation of the SAR register.

The SAR register is configured with a size equal to the number of bits of digital data to be converted.

Assuming that the general SAR-ADC of the configuration is an N-bit SAR-ADC, the operation process thereof will be described as follows.

First, in step 1, the variable (c) for counting bits of the SAR register is set to "1", the SAR register is initialized to "0", and in step 2, "1" is set to the I bit of the SAR register. (SAR = 1000… 000), and in step 3, when the DAC digital-analog converts the value of the SAR register, the comparator compares the analog input signal VIN with the digital-analog converted signal Vdac.

At this time, if the analog input signal Vin is smaller than the value of the SAR register, the I bit of the SAR register is cleared to "0" (SAR = 0000 ... 000).

If the analog input signal Vin is greater than or equal to the value of the SAR register in the above process, the variable c for counting the bits of the SAR register as the next step while maintaining the value of the SAR register is maintained. This is compared with a variable (N) that represents the size of the SAR register.

Accordingly, if the variable (c) is smaller than the variable (N) indicating the size of the SAR register, the feedback is returned to the second step, and if the variable (c) is equal to or larger than the variable (N), the comparison operation is terminated. Done. Here, the comparator outputs a value of "1" when the analog input signal is greater than or equal to the value of the SAR register, and a value of "0" when it is small.

The analog input signal Vin is converted into N bits by outputting the converted digital signal Vout whose value finally stored in the SAR register after repeating the above steps up to the Nth bit is equivalent to the analog input signal Vin. Convert to (Vout).

However, the conventional N-bit SAR-ADC not only has to perform N comparison operations in order to sample the voltage of the analog input signal and convert the voltage of the sampled input signal into a digital signal, but also does not perform data conversion. Even though analog circuits operate, there was a problem of causing unnecessary power consumption.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and analog-to-digital conversion method of the SAR (Successive Approximation Register) method was created to reduce the number of comparisons for N-bit digital signal output by predicting the voltage of the input signal The purpose is to provide.

The object of the present invention is not limited to the above-mentioned object, and other objects that are not described will be clearly understood by those skilled in the art from the following description.

In order to achieve the above object, the present invention provides a sample / holder for sampling an analog input signal for a predetermined time, and the input voltage and the sample / holder predicted based on the sampled input voltage for a predetermined time. A comparator comparing the sampled input voltages, a digital-to-analog converter (DAC) converting an input voltage predicted based on the sampled input voltages into an analog signal and inputting the analog signal to the comparator; A control for predicting an input voltage of an analog input signal to be sampled from the sample / holder and inputting it to the digital-to-analog converter, checking a comparison result of the comparator, and outputting an N bit digital signal corresponding to the comparison result if the comparison result is matched In the analog-to-digital conversion method in the analog-to-digital converter containing the logic The control logic turns on a switch connected to the voltage terminals of the sample / holder, the comparator and the digital-to-analog converter while the sleep mode is '0', wherein the control logic is currently sampled analog. Calculating a voltage of an input signal and a voltage of a previously sampled analog input signal to predict a voltage of an analog input signal to be sampled next, and then inputting the predicted input voltage to the digital-analog converter, wherein the comparator Comparing a voltage of a current sampled analog input signal with an output voltage of the digital-to-analog converter and inputting the result into the control logic, wherein the control logic compares the sampled voltage with the magnitude of the predicted voltage. If the voltage sampled in the first step is found to be greater than the expected voltage, the control logic After adding '1' to the predicted voltage input to the digital-to-analog converter, the sampler compares the sampled voltage with the predicted voltage, and if the sampled voltage is larger than the predicted voltage, the control. The logic adds '2' to the predicted voltage, and then compares the sampled voltage with the predicted voltage in the comparator. When the sampled voltage is smaller than the predicted voltage, The control logic subtracts a predetermined value from the predicted voltage, and then determines whether the predetermined value is 1. If it is determined that the voltage sampled in the first step is smaller than the predicted voltage, the control logic is configured to perform the digital operation. Subtract '1' from the predicted voltage input to the analog converter and compare the sampled voltage with the predicted voltage in the comparator again. If it is found to be smaller than the measured voltage, the fourth step of subtracting '2' from the predicted voltage and comparing the sampled voltage with the predicted voltage in the comparator again, and the comparison result of the fourth step, the sampled voltage is estimated voltage If it is found to be greater, the control logic adds a predetermined value to the predicted voltage and then determines whether the predetermined value is '1' in the fifth step and the third or fifth step of determining whether the predetermined value is '1'. If so, the control logic includes a sixth step of checking the comparison result of the comparator to determine whether the sampled voltage is greater than the expected voltage.

In one embodiment of the present invention, the control logic includes a first register, a second register, and a third register, wherein the control logic determines that the predicted voltage is not greater than the predicted voltage in the sixth step. After subtracting '1' from the voltage, the voltage stored in the first register is stored in the second register, the voltage stored in the third register is stored in the first register, and the sleep mode is changed to '1'. Power supply to the sample / holder, the comparator and the digital-to-analog converter.

Alternatively, when the control logic determines that the voltage sampled in the sixth step is larger than the expected voltage, the control logic stores the voltage stored in the first register in the second register and the voltage stored in the third register in the first register. The power supply to the sample holder, the comparator and the digital-analog converter may be cut off by switching the sleep mode to '1'.

If it is determined that the predetermined value is not '1' in the third or fifth step, the control logic checks a comparison result between the sampled voltage and the predicted voltage, and according to the check result, the subtraction operation of the third step. Alternatively, the method may further include returning to the adding operation of the fifth step.

In the third step, the predetermined value may be 1/2 of the value added to the predicted voltage in the second step.

In the fifth step, the predetermined value may be 1/2 of a value subtracted from the predicted voltage of the fourth step.

According to the present invention, the analog input signal voltage is predicted to reduce the time for converting the actual sampled input voltage into a digital signal, and the power consumption of the analog circuit is reduced by using a power gating method after the analog-digital signal conversion. There is an effect that can be reduced.

SAR-ADC of the present invention exhibiting such an effect is expected to be easy to apply in many applications such as wireless sensor network, bio equipment, multimedia equipment, because the configuration is simple, has a high resolution and can be driven with low power.

1 is a block diagram of a SAR-ADC presented as an embodiment of the present invention.
2 is a power consumption graph of the SAR-ADC of FIG.
3 is a waveform diagram illustrating a method of predicting an analog input signal in the SAR-ADC of FIG.
Figure 4 is a waveform diagram comparing the data conversion cycle of the conventional SAR-ADC and SAR-ADC of the present invention.
Figure 5 is a signal flow diagram illustrating the operation of the SAR-ADC in an embodiment of the present invention.
6 is a waveform diagram showing the number of analog input signal prediction and the comparison according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same reference numerals even though they are shown in different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. Also, throughout this specification, when a component is referred to as "comprising ", it means that it can include other components, aside from other components, .

1 is a block diagram of a SAR-ADC showing an embodiment of the present invention.

As shown in FIG. 1, a sample / holder 110 for sampling an analog input signal Vin for a predetermined time, an input voltage predicted based on the sampled input signal for a predetermined time, and Comparator 120 for comparing the input voltage sampled from the sample / holder 110, and digital for converting the input voltage predicted based on the sampled input voltage for a predetermined time into an analog signal and input to the comparator 120 Digital to Analog Converter (DAC) 130 and the sample / holder 110, Comparator 120 and Digital-to-Analog Converter 130 are controlled so that power is supplied only for a predetermined sampling time. Computes two temporally adjacent input signals sampled at the sample / holder 110 to predict an input voltage of an analog input signal to be sampled next and converts the predicted input voltage to the digital-analog converter. And a control logic 140 for inputting to the 130 and checking the comparison result of the comparator 120 and outputting a digital signal of N bits corresponding to the comparison result if the comparison result matches.

The voltage terminals of the sample / holder 110, the comparator 120, and the digital-analog converter 130 are connected to each other by a switch turned on by the control logic 140 in the sleep mode. That is, according to an exemplary embodiment of the present invention, the power supply to the sample / holder 110, the comparator 120, and the digital-analog converter 130 is performed in a sleep mode in which an analog input signal is not converted into a digital signal. It is configured to cut off power consumption in analog circuit by cutting off.

2 is a power consumption graph of a SAR-ADC according to an embodiment of the present invention. As shown in Fig. 2, the time from the sampled i th signal to the i + 1 th signal to be sampled next is the data conversion time.

However, when the frequency of sampling the analog input signal is low, the time for converting the analog signal into the digital signal is very short compared to the sample period. In this case, after the i-th input and sampled analog signal is converted to digital, the analog / sample sample / holder 110, the comparator 120 and the analog circuit for a time until the i + 1 th signal to be sampled next comes in. Although the operation of the digital-to-analog converter 130 is unnecessary, the analog circuits continue to consume power regardless of operation.

Therefore, the control logic 140 cuts the power supply by turning off the switch connected to the voltage terminals of the sample / holder 110, the comparator 120 and the digital-analog converter 130 during the time when the digital conversion is not performed. Reduced consumption

FIG. 3 is a waveform diagram illustrating a method of predicting a voltage of an analog input signal in the SAR-ADC of FIG. 1 presented as an embodiment of the present invention.

Conventional N-bit SAR-ADC converts analog signals to digital signals through N comparisons. If you can predict how analog input signals will change, you can convert analog signals to digital signals with less than N comparison times. There will be.

Therefore, in the SAR-ADC proposed as an embodiment of the present invention, an adder for calculating the voltage difference between the first and second registers in which the voltages of the analog input signals are temporally adjacent to each other, and the voltages of the two temporally adjacent analog input signals, respectively. A third register for storing the difference voltage, the two input voltages and the difference voltages are used to predict the voltage of the analog input signal to be sampled next, and input the predicted input voltage to the digital-analog converter. A control unit for checking a comparison result and outputting a corresponding N-bit digital signal to predict the voltage of the next analog input signal Vin to be sampled (V _{S & H} (K) = V _P (K)) Configure logic 140.

That is, the control logic 140 of FIG. 1 includes three registers for storing voltages of two analog input signals adjacent in time, differential voltages for the two voltages, and differential voltages from voltages of the two analog input signals. And an determiner for predicting a voltage V _{S & H} (K) = V _P (K) of the analog input signal Vin to be sampled.

Each of the data stored in the first to third registers is D0, D1, D2, and the two previously sampled input voltages are V _{S & H} (K-1) and V _{S & H} (K-2), respectively. It is assumed that the predicted input voltage is V _P (K).

First, previously sampled input voltages V _{S & H} (K-1) and V _{S & H} (K-2) are stored in the second and third registers, respectively. Where V _{S & H} (K-1) = D1 and V _{S & H} (K-2) = D2.

At this time, the predicted input voltage V _P (K) is calculated by the formula DELTA D1 = D1-D2 and D0 = D1 + ΔD1 = 2 × D1-D2 and stored in the first register. The predicted input voltage V _P (K) = D 0 is a reference of the output voltage of the digital-to-analog converter 130.

Accordingly, the comparator 120 actually compares the input voltage sampled at the sample / holder 110 with the output voltage of the digital-to-analog converter 130 through several loops. In comparison to N times as shown in 4 (a), the present invention predicts the voltage of the analog input signal to be sampled and performs the comparison operation using the predicted voltage, thereby reducing the number of comparison as shown in FIG. 4 (b). .

Therefore, the SAR-ADC proposed in the present invention reduces power consumption by reducing the number of times of comparing the analog input signal to a digital signal.

That is, the SAR-ADC proposed in the present invention reduces the time for converting an analog signal into a digital signal through prediction of the input signal voltage, and the analog circuit (sample / holder 110) during the time for not converting the analog signal into a digital signal. Power supply to the comparator 120 and the digital-to-analog converter 130 to reduce power consumption in the analog circuit.

5 is an algorithm illustrating the operation of control logic. The operation process thereof will be described below.

First, while the sleep mode is '0', the control logic 140 supplies power by turning on a switch connected to the voltage terminals of the sample / holder 110, the comparator 120, and the digital-to-analog converter 130. The sample / holder 110 samples an analog input signal and inputs the analog input signal to the comparator 120 and the control logic 140. The control logic 140 is connected to a voltage D1 of the currently sampled analog input signal. The voltage D2 of the previously sampled analog input signal is calculated to predict the voltage D0 = 2 × D1-D2 of the next analog input signal to be sampled, and then the predicted input voltage is converted into the digital-to-analog converter 130. ) Is entered.

At this time, the comparator 120 compares the voltage V _{S & H} of the currently sampled analog input signal with the output voltage Vdac of the digital-analog converter 130 and inputs the result to the control logic 140. .

Accordingly, the control logic 140 determines whether the voltage V _{S & H} of the analog input signal sampled as the first step is greater than the predicted input voltage.

At this time, if it is found that the voltage V _{S & H} of the analog input signal sampled in the first step is larger than the predicted input voltage, '1' is added to the predicted voltage D0 input to the digital-analog converter 130. The comparator 120 compares the voltage V _{S & H} of the sampled analog input signal with the predicted input voltage, and when the comparison result determines that the voltage V _{S & H} of the sampled analog input signal is greater than the predicted input voltage. After adding '2' to the predicted voltage D0, a second step of comparing the predicted input voltage with the voltage V _{S & H} of the analog input signal sampled by the comparator 120 is performed.

Subsequently, when it is determined that the comparison result of the second step as the third step is that the voltage V _{S & H} of the sampled analog input signal is smaller than the predicted input voltage, the predetermined value is subtracted from the predicted voltage D0 and then the result value. The predetermined value is 1/2 of the value added to the predicted voltage D0 in the second step.

When the voltage V _{S & H} of the analog input signal sampled in the first step is found to be smaller than the predicted input voltage, '1' is subtracted from the predicted voltage D0 input to the digital-analog converter 130. The comparator 120 compares the voltage V _{S & H} of the sampled analog input signal with the predicted input voltage, and when the comparison result determines that the voltage V _{S & H} of the sampled analog input signal is smaller than the predicted input voltage. After subtracting '2' from the predicted voltage D0, the process proceeds to a fourth step of comparing the voltage V _{S & H} of the analog input signal sampled by the comparator 120 with the predicted input voltage.

Then, the first after a step 5, adding a predetermined value to a predicted voltage (D0) when the comparison is found greater than the predicted input voltage the voltage (V _{S & H)} of the sampled analog input signal in the fourth step of the result The predetermined value is 1/2 of a value subtracted from the predicted voltage D0 of the fourth step.

If it is determined in step 3 or 5 that the predetermined value is not '1', the result of comparing the voltage V _{S & H} of the sampled analog input signal with the predicted input voltage is checked and the third value is determined according to the check result. The subtraction operation returns to the subtraction operation of the step or the addition operation of the fifth step.

Subsequently, when it is determined that the predetermined value is '1' in the third or fifth step, the control logic 140 checks the comparison result of the comparator 120 and estimates the voltage V _{S & H} of the sampled analog input signal. Proceeding to the sixth step to determine if the voltage is greater than.

Accordingly, when it is determined that the voltage V _{S & H} of the analog input signal sampled in the sixth step is not greater than the predicted input voltage, the control logic 140 subtracts '1' from the predicted voltage D0 and then registers the first register. In addition to storing the voltage D1 stored in the second register, the voltage D0 stored in the third register is stored in the first register, and the sleep mode is changed to '1', so that the sample / holder 110 and the comparator 120 And power supply to the digital-to-analog converter 130.

If the voltage V _{S & H} of the analog input signal sampled in step 6 is greater than the predicted input voltage, the voltage D1 stored in the first register is stored in the second register and the voltage stored in the third register ( D0) is stored in the first register and the sleep mode is switched to '1' to cut off the power supply to the sample / holder 110, the comparator 120, and the digital-analog converter 130.

Accordingly, the present invention can predict the voltage of the analog input signal by performing the process of FIG. 5, and find the value to be digitally converted using the predicted voltage exactly at high speed. Referring to the waveform diagram of FIG. The explanation is as follows.

FIG. 6 is a waveform diagram illustrating an analog input signal prediction and a comparison count according to an exemplary embodiment of the present invention. When the voltage V _{S & H} (K + 1) of the predicted input signal is 0.7 V, the predicted input is shown in FIG. The difference between the voltage of the signal and the voltage of the actually sampled input signal is 2 × V _LSB , and when the process of FIG. 5 is performed using the voltage difference, an accurate value matching the comparison result can be found through three comparison operations. .

While the present invention has been described with reference to several preferred embodiments, these embodiments are illustrative and not restrictive. It will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit of the invention and the scope of the appended claims.

110: sample / holder 120: comparator
130: N-bit DAC 140: control logic

Claims (6)

A sample / holder for sampling an analog input signal for a predetermined time, a comparator for comparing an input voltage predicted based on the sampled input voltage for a predetermined time and an input voltage sampled from the sample / holder; A digital-to-analog converter (DAC) for converting an input voltage predicted based on the sampled input voltage for a predetermined time into an analog signal and inputting the same to the comparator; and an analog input signal to be sampled from the sample / holder In the analog-to-digital converter comprising a control logic to predict the input voltage of the input to the digital-to-analog converter and to check the comparison result of the comparator and to output the N-bit digital signal corresponding to the comparison result if In the analog-to-digital conversion method,
The control logic turns on a switch connected to the voltage terminals of the sample / holder, the comparator and the digital-analog converter while the sleep mode is '0';
The control logic calculates the voltage of the current sampled analog input signal and the voltage of the previously sampled analog input signal to predict the voltage of the next analog input signal to be sampled, and then converts the predicted input voltage into the digital-to-analog converter. Inputting to;
The comparator comparing the voltage of the currently sampled analog input signal with the output voltage of the digital-analog converter and inputting the result into the control logic;
The control logic may include a first step of comparing a magnitude of the sampled input voltage and a predicted input voltage;
If it is determined that the input voltage sampled in the first step is larger than the predicted input voltage, the control logic adds '1' to the predicted voltage input to the digital-analog converter, and then again inputs the sampled voltage from the comparator. Compares the predicted input voltage with the predicted input voltage, and if the sampled input voltage is larger than the predicted input voltage, the control logic adds '2' to the predicted voltage and then again compares the input voltage sampled by the comparator. A second step of comparing the predicted input voltage;
If the sampled input voltage is less than the predicted input voltage, the control logic subtracts a predetermined value from the predicted voltage and determines whether the result value is 1;
If it is found that the input voltage sampled in the first step is smaller than the predicted input voltage, the control logic subtracts '1' from the predicted voltage input to the digital-analog converter, and then predicts the input voltage and the sampled voltage from the comparator again. The input voltage is compared, and if the result of the comparison indicates that the sampled input voltage is smaller than the predicted input voltage, subtract '2' from the predicted voltage, and then compare the sampled input voltage with the predicted input voltage again in the comparator. Fourth step to make;
A fifth step in which the control logic adds a predetermined value to the predicted voltage and determines whether the result value is '1' if the sampled input voltage is greater than the predicted input voltage as a result of the comparison in the fourth step; ; And
When it is determined that the result value is '1' in the third or fifth step, the control logic checks the comparison result of the comparator to determine whether the sampled input voltage is greater than the predicted input voltage. Including,
The control logic includes a first register, a second register, a third register,
If it is determined that the input voltage sampled in the sixth step is not greater than the predicted input voltage, the control logic subtracts '1' from the predicted voltage and stores the voltage stored in the first register in the second register. And storing the voltage stored in the third register in the first register and switching the sleep mode to '1' to cut off the power supply to the sample / holder, the comparator and the digital-analog converter.
If it is determined that the input voltage sampled in the sixth step is larger than the predicted input voltage, the control logic stores the voltage stored in the first register in the second register and the voltage stored in the third register in the first register. Store the power supply to the sample holder, the comparator and the digital-to-analog converter by switching the sleep mode to '1'.
delete delete The method of claim 1,
If it is determined that the predetermined value is not '1' in the third or fifth step, the control logic checks a comparison result between the sampled input voltage and the predicted input voltage, and according to the check result, And returning to the subtraction operation or the addition operation of the fifth step.
The method of claim 1,
The method of claim 3, wherein the predetermined value is 1/2 of the value added to the predicted voltage in the second step.
The method of claim 1,
The method of claim 5, wherein the predetermined value is 1/2 of the value subtracted from the predicted voltage of the fourth step.

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