KR101257930B1 - Organic Light Emitting Diode DisplAy And Driving Method Thereof - Google Patents

Abstract

The present invention relates to an organic light emitting diode display and a method of driving the same which can improve display quality by minimizing the amount of change in driving current.

An organic light emitting diode display according to the present invention comprises: a plurality of data lines to which a data voltage is supplied; A plurality of gate lines intersecting the data lines and supplied with scan pulses; A driving voltage source for generating a high potential driving voltage; An organic light emitting diode device emitting light by a current flowing between the driving voltage source and the ground voltage source; A driving device controlling a current flowing through the organic light emitting diode device according to a voltage of a first node; An emission element for switching a current path between the driving element and the base voltage source; A first capacitor connected between the first node and a second node; A second capacitor connected between the second node and the ground voltage source; And charging the first node with a first voltage for a first period, then lowering the voltage of the first node to a second voltage for a second period, and then between the data line and the second node for a third period. After supplying a data voltage to the second node by conducting a current path to increase the voltage of the first node to a third voltage, the current path between the data line and the second node is blocked for a fourth period of time so as to cut the current path. And a switch circuit for maintaining the voltage of the two nodes at the data voltage and the voltage at the first node at the third voltage.

Description

Organic Light Emitting Diode DisplAy And Driving Method Thereof}

1 is a diagram illustrating a light emission principle of a conventional organic light emitting diode display.

2 is a block diagram schematically illustrating a conventional organic light emitting diode display.

3 is a circuit diagram illustrating in detail a pixel illustrated in FIG. 2;

4 is a diagram illustrating an example in which a threshold voltage of a driving TFT is increased due to a positive gAte-BiAs stress.

FIG. 5 is a diagram illustrating a current decrease of an organic light emitting diode device according to an increase in a threshold voltage of a driving TFT.

6 is a block diagram illustrating an organic light emitting diode display device according to an exemplary embodiment of the present invention.

7 is a timing diagram of a driving signal supplied to the pixels of FIG. 6.

8 is a circuit diagram illustrating any one of the pixels of FIG. 6.

FIG. 9 is an equivalent circuit diagram of a pixel for the precharge section A of FIG. 7.

FIG. 10 is an equivalent circuit diagram of a pixel with respect to the threshold voltage compensation section B of FIG. 7.

FIG. 11 is an equivalent circuit diagram of a pixel for the address period C of FIG. 7.

FIG. 12 is an equivalent circuit diagram of a pixel for the light emission period D of FIG. 7.

FIG. 13 shows the voltage Vg applied to the gate electrode of the driving TFT according to the driving signals S [n-1], S [n], and Em [n] in the sections A, B, C, and D of FIG. And a simulation result showing the transient state of the voltage Vs applied to the source electrode of the driving TFT, the voltage Vc stored in the compensation capacitor, and the driving current I _OLED .

FIG. 14 is a simulation result diagram for showing the amount of change in driving current according to actually increasing the threshold voltage of a driving TFT when expressing the same gray scale. FIG.

Description of the Related Art

116: display panel 118: gate driving circuit

120: data driving circuit 122: pixels

124: timing controller 130: organic light emitting diode element driving circuit

S [n-1]: Shear scan pulse S [n]: Current stage scan pulse

Vd: Data voltage DT: Driving TFT

SW1, SW2, SW3: first, second and third switch TFT

ET: Emission TFT Coff: Compensation Capacitor

Cst: Storage Capacitor Em: Emitting Pulse

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode display and a driving method thereof, and more particularly, to an organic light emitting diode display and a driving method thereof capable of minimizing the amount of change in driving current and improving display quality.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include liquid crystal displays (Liquid CrystAl DisplAy: hereinafter referred to as “LCD”), field emission displays (Field Emission DisplAy: FED), and plasma display panels (PlAsmA DisplAy PAnel: hereinafter “PDP”). And an organic light emitting diode display (OrgAniC Light Emitting Diode DisplAy).

Among them, PDP is attracting attention as a display device which is light and small and is most advantageous for large screen because of its simple structure and manufacturing process. However, PDP has low luminous efficiency, low luminance and high power consumption. In addition, an active matrix LCD having a thin film transistor (“TFT”) applied as a switching device has a disadvantage in that it is difficult to make a large screen due to the semiconductor process and consumes a lot of power due to the backlight unit.

In contrast, organic light emitting diode display devices are classified into inorganic light emitting diode display devices and organic light emitting diode display devices according to the material of the light emitting layer. The organic light emitting diode display devices are self-luminous devices that emit light and have high response speed, high luminous efficiency, high luminance, and a wide viewing angle. . In comparison with the organic light emitting diode display, the inorganic light emitting diode display has higher power consumption and cannot obtain high brightness, and cannot emit various colors of R (Red), G (Green), and B (Blue). On the other hand, the organic light emitting diode display is driven at a low DC voltage of several tens of volts, has a fast response speed, obtains high luminance, and emits various colors of R, G, and B, which is suitable for next-generation flat panel display devices. Do.

In the organic light emitting diode display, when a voltage is applied between the anode 100 and the cathode 70 as shown in FIG. 1, electrons generated from the cathode 70 are transferred to the electron injection layer 78A and the electron transport layer ( 78B) is moved toward the organic light emitting layer 78C. Further, holes generated from the anode 100 move toward the organic light emitting layer 78C through the hole injection layer 78e and the hole transport layer 78d. Accordingly, in the organic light emitting layer 78C, light is generated by collision and recombination of electrons and holes supplied from the electron transport layer 78B and the hole transport layer 78d, and the light is emitted to the outside through the anode 100. The image is displayed.

FIG. 2 is a block diagram schematically illustrating a conventional organic light emitting diode display. Referring to FIG. 2, a conventional organic light emitting diode display is arranged in an area defined by the intersection of a gate line GL and a data line DL. The display panel 20 including the pixels 28, the gate driving circuit 22 driving the gate lines GL of the display panel 20, and the data lines DL of the display panel 20. The timing for controlling the data driver circuit 24 for driving the data driver, the gamma voltage generator 26 for supplying a plurality of gamma voltages to the data driver circuit 24, and the data driver circuit 24 and the gate driver circuit 22 The controller 27 is provided.

In the display panel 20, pixels 28 are arranged in a matrix. In addition, the display panel 20 is provided with a supply pad 10 for receiving a high potential voltage from an external high potential voltage source VDD and a base pad 12 for receiving a base voltage from an external base voltage source GND. do. (For example, the supply voltage source VDD and the ground voltage source GND may be supplied from the power supply unit.) The high potential voltage supplied to the supply pad 10 is supplied to each of the pixels 28. The base voltage supplied to the base pad 12 is supplied to the respective pixels 28.

The gate driving circuit 22 sequentially drives the gate lines GL by supplying gate signals to the gate lines GL.

The gamma voltage generator 26 supplies a gamma voltage having various voltage values to the data driving circuit 24.

The data driving circuit 24 converts the digital data signal input from the timing controller 27 into an analog data signal using the gamma voltage from the gamma voltage generator 26. The data driving circuit 24 supplies an analog data signal to the data lines DL whenever the gate signal is supplied.

The timing controller 27 generates a data control signal for controlling the data driving circuit 24 and a gate control signal for controlling the gate driving circuit 22 using a plurality of synchronization signals. The data control signal generated by the timing controller 27 is supplied to the data driving circuit 24 to control the data driving circuit 24. The gate control signal generated by the timing controller 27 is supplied to the gate driving circuit 22 to control the gate driving circuit 22. In addition, the timing controller 27 supplies a digital data signal supplied from the scaler to the data driving circuit 24.

Each of the pixels 28 receives a data signal from the data line DL when the gate signal is supplied to the gate line GL, and generates light corresponding to the data signal.

To this end, each of the pixels 28 includes an organic light emitting diode OLED and a gate line connected to a base voltage source GND (voltage supplied from the base pad 12) as shown in FIG. 3. GL, a data line DL, and a high potential voltage source VDD (voltage supplied from the supply pad 10) and an anode of the organic light emitting diode OLED to connect the organic light emitting diode OLED. A cell driving circuit 30 for driving is provided.

The cell driving circuit 30 includes a switching TFT T1 having a gate connected to the gate line GL, a source electrode connected to the data line DL, and a drain electrode connected to the node N, and a node N. FIG. ), A driving TFT T2 having a gate connected to the transistor; a source electrode connected to the high potential voltage source VDD; and a drain electrode connected to the organic light emitting diode device OLED; And a capacitor C connected therebetween.

When the gate signal is supplied to the gate line GL, the switching TFT T1 is turned on to supply the node N with the data signal supplied to the data line DL. The data signal supplied to the node N is charged to the capacitor C and supplied to the gate of the driving TFT T2. The driving TFT T2 controls the amount of light emitted from the organic light emitting diode OLED by controlling the amount of current I supplied from the high potential voltage source VDD to the organic light emitting diode OLED in response to the data signal supplied to the gate. Done. Then, even when the switching TFT T1 is turned off, the driving TFT T2 maintains the driving current I to emit light of the organic light emitting diode OLED by one frame by the data signal stored in the capacitor C. To be. Here, the actual cell driving circuit 30 may be set in various structures in addition to the above-described structure.

However, in general, when the gate voltage of the same polarity is applied for a long time in the organic light emitting diode display device driven as described above, the threshold voltage Vth of the driving TFT T2 increases, causing a change in operating characteristics. Such a change in the operating characteristics of the driving TFT T2 can also be seen from the experimental results of FIG. 4.

FIG. 4 shows a case where positive gAte-BiAs stress is applied to a hydrogenated amorphous silicon TFT (A-Si: H TFT) for a sample having a channel width / channel length (W / L) of 120 μm / 6 μm. It is an experimental result showing that the characteristic change of the A-Si: H TFT for a sample is brought about. In Fig. 4, the horizontal axis represents the gate voltage [V] of the sample A-Si: H TFT, and the vertical axis represents the current [A] between the source electrode terminal and the drain electrode terminal of the sample A-Si: H TFT. The index in the box represents the gate voltage application time [seC] for each graph color.

4 shows the shift of the threshold voltage and the transfer characteristic curve of the TFT according to the voltage application time when a voltage of +30 V is applied to the gate terminal of the sample A-Si: H TFT. As can be seen in FIG. 4, as the time for applying the positive voltage to the gate terminal of the A-Si: H TFT increases, the transfer characteristic curve of the TFT shifts 31 to the right, and the threshold of the A-Si: H TFT Voltage rises. (Threshold voltage rises from Vth ₁ to Vth ₄ )

When the threshold voltage of the driving TFT T2 rises as described above, the operation of the driving TFT T2 becomes unstable, so that the current I flowing through the organic light emitting diode OLED is reduced even when the same data voltage Vd is applied. Done.

FIG. 5 is a diagram illustrating a decrease in current I of the organic light emitting diode OLED according to an increase in the threshold voltage Vth of the driving TFT T2. As shown in FIG. 5, when the threshold voltage Vth of the driving TFT T2 rises from 1V to 5V, the current flowing through the organic light emitting diode OLED even if the same data voltage (when Vd = 4V) is applied. (I) gradually decreases from 550nA and eventually converges to 0A.

As a result, in the conventional organic light emitting diode display, even if the same data voltage Vd is applied, luminance unevenness occurs due to the deviation of the driving current I depending on the threshold voltage characteristic of the driving TFT T2. There is a problem that the quality is degraded.

Accordingly, it is an object of the present invention to provide an organic light emitting diode display and a driving method thereof capable of minimizing the amount of change in driving current to improve display quality and improve image quality reliability.

In order to achieve the above object, the organic light emitting diode display according to the embodiment of the present invention comprises a plurality of data lines supplied with a data voltage; A plurality of gate lines intersecting the data lines and supplied with scan pulses; A driving voltage source for generating a high potential driving voltage; An organic light emitting diode device emitting light by a current flowing between the driving voltage source and the ground voltage source; A driving device controlling a current flowing through the organic light emitting diode device according to a voltage of a first node; An emission element for switching a current path between the driving element and the base voltage source; A first capacitor connected between the first node and a second node; A second capacitor connected between the second node and the ground voltage source; And charging the first node with a first voltage for a first period, then lowering the voltage of the first node to a second voltage for a second period, and then between the data line and the second node for a third period. After supplying a data voltage to the second node by conducting a current path to increase the voltage of the first node to a third voltage, the current path between the data line and the second node is blocked for a fourth period of time so as to cut the current path. And a switch circuit for maintaining the voltage of the two nodes at the data voltage and the voltage at the first node at the third voltage.

The switch circuit may include: a first switch element forming a current path between the drain electrode of the driving element and the first node in response to a first scan pulse; A second switch element forming a current path between the source electrode of the driving element and the second node in response to the first scan pulse; And a third switch element forming a current path between the data line and the second node in response to a second scan pulse generated subsequent to the first scan pulse.

The emission element is turned on and off in response to an emission pulse; The voltage of the emission pulse is polled between the rising edge and the falling edge of the first scan pulse, and rises between the falling edge of the first scan pulse and the falling edge of the second scan pulse.

The first period is defined as a period between the rising edge of the first scan pulse and the falling edge of the emission pulse, and the second period is between the falling edge of the emission pulse and the falling edge of the first scan pulse. Wherein the third period is defined as a period between the falling edge of the first scan pulse and the falling edge of the second scan pulse, and the fourth period starts from the falling edge of the second scan pulse. It is defined as the low logic period of the second scan pulse.

The first voltage Vpc is as follows.

The second voltage is equal to the threshold voltage of the driving device.

The third voltage is a voltage obtained by adding the data voltage to a threshold voltage of the driving device.

The current I _OLED flowing in the organic light emitting diode device during the fourth period is represented by the following equation.

The driving element, the emission element and the plurality of switch elements are N-type electron metal oxide semiconductor field effect transistors.

The driving device, the emission device, and the plurality of switch devices include a semiconductor layer formed of an amorphous silicon layer.

The driving device may include a gate electrode connected to the first node; A drain electrode commonly connected to the cathode electrode of the organic light emitting diode element and the drain electrode of the first switch element; And a source electrode commonly connected to the drain electrode of the emission element and the drain electrode of the second switch element.

The first switch element may include a gate electrode connected to a first gate line to which the first scan pulse is supplied; A drain electrode commonly connected to the cathode electrode of the organic light emitting diode element and the drain electrode of the driving element; And a source electrode connected to the first node.

The second switch element may include a gate electrode connected to a first gate line to which the first scan pulse is supplied; A drain electrode commonly connected to the source electrode of the driving element and the drain electrode of the emission element; And a source electrode connected to the second node.

The third switch device may include a gate electrode connected to a second gate line to which the second scan pulse is supplied; A drain electrode connected to the data line; And a source electrode connected to the second node.

The emission element may include a gate electrode connected to an emission line to which the emission pulse is supplied; A drain electrode commonly connected to the source electrode of the driving device and the drain electrode of the second switch device; And a source electrode commonly connected to the base voltage source and the second capacitor.

According to an exemplary embodiment of the present invention, a plurality of data lines supplied with a data voltage, a plurality of gate lines intersecting the data lines and supplied with a scan pulse, a driving voltage source generating a high potential driving voltage, between the driving voltage source and the base voltage source An organic light emitting diode device that emits light by a current flowing in the; a driving device that controls a current flowing through the organic light emitting diode device according to a voltage of a first node; And a second capacitor connected between the second node disposed in the same pixel area as the first node and the base voltage source, and a switch circuit operated according to a driving signal. The method of driving the organic light emitting diode display device includes: Connecting a first capacitor between a first node and the second node; Charging a first voltage to the first node for a first period of time; Lowering the voltage of the first node to a second voltage for a second period following the first period; Raising the voltage of the first node to a third voltage by supplying a data voltage to the second node by conducting a current path between the data line and the second node for a third period following the second period; And interrupting a current path between the data line and the second node during the fourth period following the third period to maintain the voltage of the second node at the data voltage and to maintain the voltage of the first node at a third period. Maintaining at a voltage.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 14.

6 is a block diagram illustrating an organic light emitting diode display according to an exemplary embodiment of the present invention, and FIG. 7 is a scan pulse S [n-1], S [supplied to any one of the pixels 122 of FIG. n]) and emission pulses Em [n].

6 and 7, an organic light emitting diode display according to an exemplary embodiment of the present invention includes a display panel 116 on which m × n pixels 122 are formed, and data lines DL [1] to. Data driving circuit 120 for supplying an analog data voltage to DL [m] and gate lines GL [0] to GL [n] intersecting with data lines DL [1] to DL [m]. Is supplied to the scan pulses S [0] to S [n], and the emission lines EL [1] to EL [n intersecting the data lines DL [1] to DL [m]. Gate driving circuit 118 for supplying the emission pulses Em [1] to Em [n], and a timing controller 124 for controlling the data driving circuit 120 and the gate driving circuit 118. Equipped.

The display panel 116 includes pixels formed in pixel areas defined by intersections of n gate lines GL [1] to GL [n] and m data lines DL [1] to DL [m]. (122). Signal lines for supplying a high potential driving voltage (hereinafter, referred to as a driving voltage) to each of the pixels 122 are formed in the display panel 116. Although not shown, signal lines for supplying a ground voltage to each of the pixels 122 are formed in the display panel 116. The gate line GL [0] is for supplying a precharge voltage to the pixels 122 positioned in the first horizontal line.

The data driving circuit 120 converts the digital video data RGB into an analog data voltage in response to the control signal DDC from the timing controller 124, and then converts the analog data voltage (hereinafter, referred to as data voltage) into data. To the lines DL [1] to DL [m]. This data voltage is supplied to the pixels 122 connected to the data lines DL [1] to DL [m].

The gate driving circuit 118 receives the scan pulses S [n-1] and S [n] shown in FIG. 7 in response to the control signal GDC from the timing controller 124. ] To GL [n]) and the emission pulse Em [n] shown in FIG. 7 in response to the control signal GDC from the timing controller 124. 1] to GL [n]). The scan pulses S [n-1], S [n] and emission pulses Em [n] are connected to the pixels 122 connected to the gate lines GL [1] to GL [n]. Supplied.

The timing controller 124 supplies digital video data RGB to the data driving circuit 120 and operates timings of the gate driving circuit 118 and the data driving circuit 120 using vertical / horizontal synchronization signals and clock signals. It generates a control signal (DDC, GDC) to control.

In the timing diagram of FIG. 7, A is a precharge period for supplying a precharge voltage to the gate electrode of the driving TFT provided in the pixel 122. B is a threshold voltage compensation section for discharging the precharge voltage to compensate for the change in the threshold voltage of the driving TFT so that the voltage applied to the gate electrode of the driving TFT converges to the threshold voltage of the driving TFT. C is an address period for allowing a data voltage to be applied to the gate electrode of the driving TFT together with the threshold voltage of the driving TFT. D is a light emission period in which the organic light emitting diode element provided in the pixel 122 emits light by the sum of the threshold voltage and the data voltage of the driving TFT.

Here, the precharge section A is defined as a period between the rising edge of the front end scan pulse S [n-1] and the falling edge of the emission pulse Em [n], and the threshold voltage compensation section B. Is defined as the period between the falling edge of emission pulse Em [n] and the falling edge of shear scan pulse S [n-1]. In addition, the address period C is defined as a period between the polling edge of the front end scan pulse S [n-1] and the polling edge of the present stage scan pulse S [n], and the light emitting period D is present. It is defined as the low logical period of the current stage scan pulse S [n] starting from the falling edge of the stage scan pulse S [n]. The operation of the pixels 122 in A, B, C, and D will be described in detail with reference to FIGS. 9 through 12.

The display panel 116 is connected to a driving voltage source VDD for supplying a driving voltage to the pixels 122 and a ground voltage source GND for supplying a base voltage to the pixels 122.

Each of the pixels 122 includes an organic light emitting diode (OLED), one driving TFT, three switch TFTs, one emission TFT, and two capacitors as shown in FIG. 8.

8 is a circuit diagram illustrating a pixel 122 included in an organic light emitting diode display according to an exemplary embodiment of the present invention.

Referring to FIG. 8, the pixel 122 according to the exemplary embodiment of the present invention may emit light by an electric current flowing between the driving voltage source VDD and the ground voltage source GND, and the data line DL [ OLEDs according to driving signals supplied from 1] to DL [m], gate lines GL [0] to GL [n], and emission lines EL [1] to EL [n]. ) Is provided with an organic light emitting diode element driving circuit (130).

The anode of the organic light emitting diode element OLED is connected to the driving voltage source VDD, and the cathode is connected to the drain electrode D of the driving TFT DT. The organic light emitting diode OLED has a structure as illustrated in FIG. 1, and a driving current I _OLED controlled according to a voltage applied to the gate electrode G of the driving TFT DT through the first node n1. It emits light by Here, the anode of the organic light emitting diode OLED formed of the transparent electrode is formed on the opposite side of the substrate on which the driving TFT DT is formed. Accordingly, the pixels 122 of the organic light emitting diode display according to the present invention emit light according to a top emission method.

The organic light emitting diode element driving circuit 130 is switched according to the driving TFT DT for controlling the driving current I _OLED of the organic light emitting diode element OLED and the front end scan pulse S [n-1]. The first and second switch TFTs SW1 and SW2 are configured to allow the first node n1 to be charged to the precharge voltage, and then to discharge the voltage of the first node n1 to the threshold voltage of the driving TFT DT. ), The third switch TFT SW3 for switching the data according to the current stage scan pulse S [n] to supply the data voltage Vp to the second node n2, and the driving TFT DT following the precharge voltage. The compensation capacitor Coff storing the threshold voltage of the storage capacitor, the storage capacitor Cst storing the data voltage Vp, and the driving TFT DT and the base voltage source GND in response to the emission pulse Em [n]. An emission TFT (ET) for switching the current path therebetween is provided.

Here, the TFTs are N-type electron metal oxide semiconductor field effect transistors (MOSFETs, MetAl-Oxide SemiConduCtor Field EffeCt TrAnsistor). In particular, the semiconductor layers of the TFTs are formed of an amorphous silicon layer so that the amount of change in the threshold voltage between the TFTs due to the same gate bias stress is almost the same.

The gate electrode G of the driving TFT DT is connected to the first node n1, and the drain electrode D of the driving TFT DT is the cathode of the organic light emitting diode OLED and the first switch TFT SW1. Is commonly connected to the drain electrode D of the driving TFT DT, and the source electrode of the driving TFT DT is commonly connected to the drain electrode D of the emission TFT ET and the drain electrode D of the second switch TFT SW2. . The driving TFT DT controls the current flowing through the organic light emitting diode OLED according to the voltage applied to its gate electrode G through the first node n1.

The gate electrode G of the first switch TFT SW1 is connected to the front gate line GL [n-1], and the drain electrode D of the first switch TFT SW1 is the organic light emitting diode OLED. Is connected to the cathode of and the drain electrode D of the driving TFT DT, and the source electrode S of the first switch TFT SW1 is connected to the first node n1. The first switch TFT SW1 is turned on in response to the front end scan pulse S [n-1] from the front end gate line GL [n-1], thereby precharging the voltage to the first node n1. To be supplied. The precharge voltage is stored in the compensation capacitor Coff during the precharge period A of FIG. 7.

The gate electrode G of the second switch TFT SW2 is connected to the front gate line GL [n-1], and the drain electrode D of the second switch TFT SW2 is the source of the driving TFT DT. Commonly connected to the electrode S and the drain electrode D of the emission TFT ET, the source electrode S of the second switch TFT SW2 is connected to the second node n2. The second switch TFT SW2 is turned on in response to the front end scan pulse S [n-1] from the front end gate line GL [n-1], thereby storing the precharge voltage stored in the compensation capacitor Coff. Discharge paths are formed to lower the precharge voltage to the threshold voltage value of the driving TFT DT. The threshold voltage of the driving TFT DT is stored in the compensation capacitor Coff during the threshold voltage compensation period B of FIG. 7.

The gate electrode G of the third switch TFT SW3 is connected to the rear gate line GL [n], and the drain electrode D of the third switch TFT SW3 is connected to the data line DL [k] (1). ? K? M), and the source electrode S of the third switch TFT SW3 is connected to the second node n2. The third switch TFT SW3 is turned on in response to the current scan pulse S [n] from the rear gate line GL [n], so that the data voltage Vd is applied to the second node n2. To be supplied. The data voltage Vd is stored in the storage capacitor Cst during the address period C and the light emission period D of FIG. 7.

One side of the compensation capacitor Coff is connected to the first node n1, and the other side of the compensation capacitor Coff is connected to the second node n2. The compensation capacitor Coff stores the precharge voltage supplied to the first node n1 during the precharge period (A of FIG. 7), and then the threshold voltage compensation period (B of FIG. 7) and the address period (FIG. 7). C) and the light emission period (D in FIG. 7) are maintained at the threshold voltage of the driving TFT DT lower than the precharge voltage.

 One side of the storage capacitor Cst is connected to the second node n2, and the other side of the storage capacitor Cst is commonly connected to the base voltage source GND and the source electrode S of the emission TFT ET. The storage capacitor Cst stores the data voltage Vd supplied to the second node n2 during the address period C of FIG. 7, and then stores the data voltage Vd during the emission period D of FIG. 7. Maintains the voltage at the data voltage Vd.

The gate electrode G of the emission TFT ET is connected to the emission line EL [n], and the drain electrode D of the emission TFT ET is the source electrode S of the driving TFT DT. And a common connection to the drain electrode D of the second switch TFT SW2, and a source electrode S of the emission TFT ET is commonly connected to the other side of the base voltage source GND and the storage capacitor Cst. The emission TFT ET is turned on in response to the emission pulse Em [n] from the emission line EL [n], thereby providing a current between the driving TFT DT and the ground voltage source GND. Switch pass. Here, the voltage of the emission pulse is polled between the rising edge and the falling edge of the shear scan pulse S [n-1], and the falling edge of the shear scan pulse S [n-1] and the current scan pulse ( Rising between the falling edges of S [n]).

The operations of the pixels 122 will be described below with reference to FIGS. 9 through 12.

FIG. 9 is an equivalent circuit diagram of the pixel 122 for the precharge section A of FIG. 7.

Referring to FIG. 9, during the precharge period A, the front end scan pulse S [n-1] is generated at a high logic voltage to turn on the first switch TFT SW1 and the second switch TFT SW2. The current stage scan pulse S [n] is generated with a low logic voltage to turn off the third switch TFT SW3. In addition, the emission pulse Em [n] is generated at a high logic voltage during the precharge period A to turn on the emission TFT ET. Accordingly, the first node n1 is charged with the precharge voltage Vpc as shown in Equation 1 below through the compensation capacitor Coff.

Here, VDD denotes a driving voltage, Vto denotes a threshold voltage of the organic light emitting diode OLED, and Vth denotes a threshold voltage of the driving TFT DT, respectively.

This precharge voltage Vpc is stored and maintained in the compensation capacitor Coff during the precharge period A.

FIG. 10 is an equivalent circuit diagram of the pixel 122 for the threshold voltage compensation section B of FIG. 7.

Referring to FIG. 10, during the threshold voltage compensation interval B, the front end scan pulse S [n-1] maintains a high logic voltage to maintain turn-on states of the first and second switch TFTs SW1 and SW2. The current scan pulse S [n] maintains a low logic voltage to maintain the turn-off state of the third switch TFT SW3. Meanwhile, the emission pulse Em [n] is inverted to a low logic voltage during the threshold voltage compensation period B, thereby turning off the emission TFT ET. Accordingly, the precharge voltage Vpc stored in the compensation capacitor Coff during the precharge period A is along the closed loop through the driving TFT DT operated like a diode (indicated by a dotted line). Discharged. The voltage charged in the first node n1 by this discharge converges to the threshold voltage Vth of the driving TFT DT. The driving TFT DT threshold voltage Vth is stored and maintained in the compensation capacitor Coff during the threshold voltage compensation period B, the address period C, and the light emission period D.

FIG. 11 is an equivalent circuit diagram of the pixel 122 for the address period C of FIG. 7.

Referring to FIG. 11, during the address period C, the front end scan pulse S [n-1] is inverted to a low logic voltage to turn off the first and second switch TFTs SW1 and SW2 and presently. However, the scan pulse S [n] is inverted to a high logic voltage to turn on the third switch TFT SW3. In addition, during the address period C, the emission pulse Em [n] is inverted to a high logic voltage to turn on the emission TFT ET. Accordingly, the data voltage Vd is supplied to the second node n2 and then stored and maintained in the storage capacitor Cst during the address period C and the light emission period D. FIG. The potential of the first node n1 is increased by the data voltage Vd charged in the second node n2. In other words, the potential of the first node n1 is equal to the sum of the driving voltage DTth and the sum of the voltages Vd + Vth of the data voltage Vd.

By this summation voltage Vd + Vth, the threshold voltage Vth of the driving TFT DT is erased as shown in Equation 2 below. As a result, the driving current I _OLED is a function of only the data voltage Vd. do.

Here, I _OLED is a driving current, Kn is a constant value determined by mobility and parasitic capacitance of the driving TFT DT, Vgs is a difference voltage between the gate and the source electrode of the driving TFT DT, and Vth is the driving TFT DT. The threshold voltage of Vd denotes the data voltage, respectively.

As shown in Equation 2, since the driving current I _OLED is determined as a function of the data voltage Vd only, the driving current I even if the threshold voltage Vth _DR of the driving TFT DT is changed due to the gate bias stress. _OLED ) has little effect.

FIG. 12 is an equivalent circuit diagram of the pixel 122 for the emission period D of FIG. 7.

Referring to FIG. 12, during the emission period D, the front end scan pulse S [n-1] maintains a low logic voltage to maintain the turn-off states of the first and second switch TFTs SW1 and SW2. The current stage scan pulse S [n] is inverted to a low logic voltage to turn off the third switch TFT SW3. In addition, the emission pulse Em [n] maintains the high logic voltage during the emission period C to maintain the turn-on state of the emission TFT ET. Accordingly, as shown in Equation 2, the organic light emitting diode OLED emits light by the driving current I _OLED determined as a function of the data voltage Vd only.

FIG. 13 illustrates the gate electrode G of the driving TFT DT according to the driving signals S [n-1], S [n], and Em [n] in the sections A, B, C, and D of FIG. The transient state of the voltage Vg applied to the voltage, the voltage Vs applied to the source electrode S of the driving TFT DT, the voltage Vc stored in the compensation capacitor Coff, and the driving current I _OLED . Is a simulation result. In FIG. 13, the horizontal axis represents time s and the vertical axis represents voltage V or current A. In FIG.

Referring to FIG. 13, the voltage Vg applied to the gate electrode G of the driving TFT DT becomes the threshold voltage compensation period B after the potential is increased to the precharge voltage Vpc during the precharge period A. FIG. Is maintained at this precharge voltage Vpc. The voltage Vg applied to the gate electrode G of the driving TFT DT is the sum of the data voltage Vd and the threshold voltage Vth of the driving TFT DT through the transient period B '. After the potential is lowered to + Vth, the summation voltage Vd + Vth is maintained for the address period C and the light emission period D. FIG. Here, the transient period B 'is determined as the period between the falling edge of the front end scan pulse S [n-1] and the rising edge of the present end scan pulse S [n].

The voltage Vs applied to the source electrode S of the driving TFT DT has a high potential due to the precharge voltage Vpc and the difference voltage Vpc-Vth of the driving TFT DT during the precharge period A. This difference voltage Vpc-Vth is maintained during the post-threshold voltage compensation period B. FIG. Then, the voltage Vs applied to the source electrode S of the driving TFT DT has a potential lowered to 0 V through the transient period B 'and then becomes zero during the address period C and the light emission period D. Is maintained at V.

The voltage Vc stored in the compensation capacitor Coff is discharged through the threshold voltage compensation period B and the transient period B 'after the potential rises to the precharge voltage Vpc during the precharge period A. The potential is lowered by the threshold voltage Vth of the driving TFT DT. The voltage Vc stored in the compensation capacitor Coff is maintained at the threshold voltage Vth of the driving TFT DT during the address period C and the light emission period D. FIG.

The driving current I _OLED is the threshold voltage of the driving TFT DT by the gate voltage Vg of the driving TFT DT maintained at the sum voltage Vd + Vth during the address period C and the emission period D. (Vth) It remains constant without being affected by the rise. This shows that Equation 2 is satisfied.

14 is a simulation result for showing the amount of change in driving current according to the increase in the threshold voltage Vth of the driving TFT DT when the same gray scale is expressed. In Fig. 14, the horizontal axis represents the threshold voltage Vth of the driving TFT DT, and the vertical axis represents the driving current I _OLED .

As shown in Equation 2, since the driving current I _OLED is determined as a function of the data voltage Vd only, the change amount ΔI _OLED of the driving current according to the increase of the threshold voltage Vth of the driving TFT DT is ideally. Must indicate 0%. However, in practice, the change amount of the driving current ΔI _OLED is not only the data voltage Vd but also the coupling of the parasitic capacitances Cgs and Cgd generated by the driving TFT DT with the coupling of these Cgd and Cgs ( It is also affected by the coupling phenomenon. Accordingly, the change amount ΔI _OLED of the driving current according to the increase of the threshold voltage Vth _DR of the driving TFT DT represents a value of 1% to 10% in inverse proportion to the magnitude of the applied data voltage. Here, Cgs denotes a parasitic capacitance between the gate and source electrodes, and Cgd denotes a parasitic capacitance between the gate and drain electrodes (Cgd). As a result, even if the increase in threshold voltage (Vth) is 1V of the driving TFT (DT), in the embodiment of the present invention to 5V, the variation of the driving current flowing in the organic light emitting diode device _(OLED) (△ I OLED) from the same gray level is It can be seen that the change is greatly reduced within the maximum of 10%. This shows a significantly increased effect compared to the amount of change ΔI of the driving current flowing through the organic light emitting diode OLED in the same condition as the conventional 100% (see FIG. 5).

As described above, the organic light emitting diode display and the driving method thereof according to the embodiment of the present invention, the driving flow to the organic light emitting diode element by supplying the data voltage of the driving TFT plus the threshold voltage of the driving TFT The current is changed only by the data voltage regardless of the change in the threshold voltage of the driving TFT. Accordingly, the organic light emitting diode display and the driving method thereof according to the embodiment of the present invention can minimize the amount of change in the driving current caused by the change of the threshold voltage of the driving TFT, thereby improving display quality and improving image quality reliability.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (23)

A plurality of data lines supplied with data voltages; A plurality of gate lines intersecting the data lines and supplied with scan pulses; A driving voltage source for generating a high potential driving voltage; An organic light emitting diode device emitting light by a current flowing between the driving voltage source and the ground voltage source; A driving device controlling a current flowing through the organic light emitting diode device according to a voltage of a first node; An emission element for switching a current path between the driving element and the base voltage source; A first capacitor connected between the first node and a second node; A second capacitor connected between the second node and the ground voltage source; And After charging the first node to a first voltage for a first period, the voltage of the first node is lowered to a second voltage for a second period, and then a current between the data line and the second node for a third period. Conducting a path to supply a data voltage to the second node to increase the voltage of the first node to a third voltage, and then cut off the current path between the data line and the second node for a fourth period of time; And a switch circuit which maintains the voltage of the node at the data voltage and maintains the voltage of the first node at the third voltage. The method of claim 1, The switch circuit, A first switch element forming a current path between the drain electrode of the driving element and the first node in response to a first scan pulse; A second switch element forming a current path between the source electrode of the driving element and the second node in response to the first scan pulse; And And a third switch element forming a current path between the data line and the second node in response to a second scan pulse generated after the first scan pulse. The method of claim 2, The emission element is turned on in response to the high state of the emission pulse and turned off in response to the low state of the emission pulse; And the voltage of the emission pulse is polled between the rising edge and the falling edge of the first scan pulse, and rises between the falling edge of the first scan pulse and the falling edge of the second scan pulse. Diode display. The method of claim 3, wherein The first period is defined as a period between the rising edge of the first scan pulse and the falling edge of the emission pulse, and the second period is between the falling edge of the emission pulse and the falling edge of the first scan pulse. And a third period is defined as a period between the falling edge of the first scan pulse and the falling edge of the second scan pulse, and the fourth period starts from the falling edge of the second scan pulse. And a low logical period of the second scan pulse. 5. The method of claim 4, The first voltage Vpc is as shown in the following formula.

Here, VDD denotes the high potential driving voltage, Vto denotes the threshold voltage of the organic light emitting diode device, and Vth denotes the threshold voltage of the driving device, respectively. 5. The method of claim 4, And the second voltage is a threshold voltage of the driving element. 5. The method of claim 4, And the third voltage is a voltage obtained by adding the data voltage to a threshold voltage of the driving device. 5. The method of claim 4, An organic light emitting diode display device, wherein the current I _OLED flowing through the organic light emitting diode device during the fourth period is as shown in the following equation.

Here, Kn is a constant value determined by mobility and parasitic capacitance of the driving device, Vgs is a difference voltage between the gate electrode and the source electrode of the driving device, Vth is the threshold voltage of the driving device, and Vd is the data voltage, respectively. it means. The method of claim 3, wherein And the driving element, the emission element, and the plurality of switch elements are N-type electron metal oxide semiconductor field effect transistors. The method of claim 9, And the driving element, the emission element and the plurality of switch elements comprise a semiconductor layer formed of an amorphous silicon layer. 11. The method of claim 10, The driving device, A gate electrode connected to the first node; A drain electrode commonly connected to the cathode electrode of the organic light emitting diode element and the drain electrode of the first switch element; And And a source electrode commonly connected to the drain electrode of the emission element and the drain electrode of the second switch element. 11. The method of claim 10, The first switch device, A gate electrode connected to a first gate line to which the first scan pulse is supplied; A drain electrode commonly connected to the cathode electrode of the organic light emitting diode element and the drain electrode of the driving element; And An organic light emitting diode display device comprising: a source electrode connected to the first node. 11. The method of claim 10, The second switch device, A gate electrode connected to a first gate line to which the first scan pulse is supplied; A drain electrode commonly connected to the source electrode of the driving element and the drain electrode of the emission element; And And a source electrode connected to the second node. 11. The method of claim 10, The third switch device, A gate electrode connected to a second gate line to which the second scan pulse is supplied; A drain electrode connected to the data line; And And a source electrode connected to the second node. 11. The method of claim 10, The emission element, A gate electrode connected to the emission line to which the emission pulses are supplied; A drain electrode commonly connected to the source electrode of the driving device and the drain electrode of the second switch device; And And a source electrode commonly connected to the base voltage source and the second capacitor. Claim 16 has been abandoned due to the setting registration fee. Connecting a first capacitor between the first node and the second node; Charging a first voltage to the first node for a first period of time; Lowering the voltage of the first node to a second voltage for a second period following the first period; Raising the voltage of the first node to a third voltage by supplying a data voltage to the second node by conducting a current path between the data line and the second node for a third period following the second period; And The current path between the data line and the second node is interrupted during the fourth period following the third period, thereby maintaining the voltage of the second node at the data voltage and the voltage of the first node at a third voltage. And driving the organic light emitting diode display device. Claim 17 has been abandoned due to the setting registration fee. The drive signal is, And a first scan pulse and a second scan pulse generated after the first scan pulse. Claim 18 has been abandoned due to the setting registration fee. The method of claim 17, The emission element is turned on in response to the high state of the emission pulse and turned off in response to the low state of the emission pulse; And the voltage of the emission pulse is polled between the rising edge and the falling edge of the first scan pulse, and rises between the falling edge of the first scan pulse and the falling edge of the second scan pulse. Method of driving a diode display device. Claim 19 is abandoned in setting registration fee. The method of claim 18, The first period is defined as a period between the rising edge of the first scan pulse and the falling edge of the emission pulse, and the second period is between the falling edge of the emission pulse and the falling edge of the first scan pulse. Wherein the third period is defined as a period between the falling edge of the first scan pulse and the falling edge of the second scan pulse, and the fourth period starts from the falling edge of the second scan pulse. And a low logic period of the second scan pulse. Claim 20 has been abandoned due to the setting registration fee. The first voltage (Vpc) is a driving method of the organic light emitting diode display device, characterized in that as shown below.

Here, VDD denotes the high potential driving voltage, Vto denotes the threshold voltage of the organic light emitting diode device, and Vth denotes the threshold voltage of the driving device, respectively. Claim 21 has been abandoned due to the setting registration fee. 20. The method of claim 19, And wherein the second voltage is a threshold voltage of the driving element. Claim 22 is abandoned in setting registration fee. 20. The method of claim 19, And wherein the third voltage is a voltage obtained by adding the data voltage to a threshold voltage of the driving device. Claim 23 has been abandoned due to the setting registration fee. 20. The method of claim 19, The current I _OLED flowing through the organic light emitting diode device during the fourth period is as shown in the following equation. Here, Kn is a constant value determined by mobility and parasitic capacitance of the driving device, Vgs is a difference voltage between the gate electrode and the source electrode of the driving device, Vth is the threshold voltage of the driving device, and Vd is the data voltage, respectively. it means.

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