KR101239850B1

KR101239850B1 - Vertical light emitting diode and method of fabricating the same

Info

Publication number: KR101239850B1
Application number: KR1020060093393A
Authority: KR
Inventors: 김윤구; 서원철
Original assignee: 서울옵토디바이스주식회사
Priority date: 2006-09-26
Filing date: 2006-09-26
Publication date: 2013-03-06
Also published as: KR20080028070A

Abstract

A vertical light emitting diode and a method of manufacturing the same are disclosed. The method includes forming a compound semiconductor layer including a first conductive compound semiconductor layer, an active layer, and a second conductive compound semiconductor layer on the sacrificial substrate. A conductive substrate is formed on the compound semiconductor layers, and metal patterns defining scribing lines are formed on the conductive substrate. Subsequently, the sacrificial substrate is separated from the compound semiconductor layers to expose a first conductive compound semiconductor layer, and an electrode pad is formed on the first conductive compound semiconductor layer. Thereafter, the conductive substrate is cut along the scribing lines and separated into individual light emitting diode chips. The metal patterns are separated along the scribing line, thereby preventing the compound semiconductor layers and the conductive substrate from warping when separating the compound semiconductor layers from the sacrificial substrate, and facilitating a process of cutting the conductive substrate.

Vertical Light Emitting Diodes, Metal Patterns, Sub-patterns

Description

Vertical light emitting diode and its manufacturing method {VERTICAL LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME}

1 is a cross-sectional view illustrating a method of manufacturing a vertical light emitting diode according to the prior art.

2 is a cross-sectional view illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.

3 is a plan view illustrating metal patterns applicable to embodiments of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical light emitting diode and a method of manufacturing the same, and more particularly, to a vertical light emitting diode employing a metal pattern for preventing bowing and a method of manufacturing the same.

In general, nitrides of Group III elements, such as gallium nitride (GaN) and aluminum nitride (AlN), have excellent thermal stability and have a direct transition energy band structure. As a lot of attention. In particular, blue and green light emitting devices using gallium nitride (GaN) have been utilized in various applications such as large-scale color flat panel display devices, traffic lights, indoor lighting, high density light sources, high resolution output systems, and optical communications.

The nitride semiconductor layer of such a group III element, in particular, GaN, is difficult to fabricate a homogeneous substrate capable of growing it, and thus, it is difficult to fabricate a homogeneous substrate capable of growing it, such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy; MBE) and other processes. A sapphire substrate having a hexagonal system structure is mainly used as a heterogeneous substrate. However, since sapphire is an electrically insulator, it restricts the light emitting diode structure and is very stable mechanically and chemically, making it difficult to process such as cutting and shaping. In recent years, a technology for growing a nitride semiconductor layer on a heterogeneous substrate such as sapphire and then separating the heterogeneous substrate to fabricate a vertical-type LED has been researched.

Referring to FIG. 1A, gallium nitride-based compound semiconductor layers are sequentially grown on a sacrificial substrate 11 such as a sapphire substrate. The compound semiconductor layers include a first conductivity type semiconductor layer 15, an active layer 17, and a second conductivity type semiconductor layer 19. In addition, a buffer layer 13 is generally interposed between the first conductive semiconductor layer 15 and the sacrificial substrate 11.

Referring to FIG. 1B, a conductive substrate 21 is attached to the compound semiconductor layers. The conductive substrate 21 is generally attached on the conductive substrate 21 by the bonding layer 23. On the other hand, a reflective layer (not shown) may also be interposed between the conductive substrate 21 and the compound semiconductor layers.

Referring to FIG. 1C, the sacrificial substrate 11 is separated from the compound semiconductor layers. At this time, the buffer layer 13 is also removed, and the first conductivity type compound semiconductor layer 15 is exposed. The sacrificial substrate 11 may be separated from the compound semiconductor layers mainly using a laser lift-off process, and may be separated through other chemical and chemical methods. Thereafter, an electrode pad 17 is formed on the exposed first conductive compound semiconductor layer 15, and individual light emitting diode chips are completed by cutting the conductive substrate 21.

According to the prior art, by adopting the conductive substrate 21 having excellent heat dissipation performance, the light emitting efficiency of the light emitting diode can be improved, and a light emitting diode having a vertical structure can be provided. However, after the sacrificial substrate 11 is separated, the residual stress due to lattice mismatch between the compound semiconductor layers and the sacrificial substrate 11 and the coefficient of thermal expansion between the conductive substrate 21 and the compound semiconductor layers. Due to the difference or the like, warpage of the compound semiconductor layers occurs.

The warpage phenomenon can be solved to some extent by adjusting the thermal expansion coefficient or the thickness of the conductive substrate. However, it is difficult to control the coefficient of thermal expansion of the conductive substrate, and especially when adopting a metal conductive substrate having excellent electrical conductivity, it is required to adjust the composition ratio of the metal elements using alloying technology to control the coefficient of thermal expansion. In addition, when the conductive substrate is thick, the cutting process of the conductive substrate becomes difficult, and when the conductive substrate is cut using a laser, the laser power is increased, and a lot of metal by-products are generated to contaminate the chip.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a vertical light emitting diode manufacturing method which can prevent warpage of a compound semiconductor layer when the sacrificial substrate is separated, and which can easily cut a conductive substrate.

Another object of the present invention is to provide a light emitting diode manufacturing method capable of preventing warpage of the light emitting diode even after being separated into individual light emitting diode chips.

Another object of the present invention is to provide a vertical light emitting diode capable of preventing warpage of the compound semiconductor layers.

In order to achieve the above technical problem, an aspect of the present invention provides a vertical light emitting diode manufacturing method. The method includes forming a compound semiconductor layer including a first conductive compound semiconductor layer, an active layer, and a second conductive compound semiconductor layer on the sacrificial substrate. A conductive substrate is formed on the compound semiconductor layers, and metal patterns defining scribing lines are formed on the conductive substrate. Subsequently, the sacrificial substrate is separated from the compound semiconductor layers to expose a first conductive compound semiconductor layer, and an electrode pad is formed on the first conductive compound semiconductor layer. The conductive substrate is then cut along the scribing lines and separated into individual light emitting diode chips. The metal patterns are separated along the scribing line to prevent the compound semiconductor layers and the conductive substrate from warping when the compound semiconductor layers are separated from the sacrificial substrate, and the conductive substrate can be thinned to facilitate the cutting process. Let's do it.

Each of the metal patterns may have lower patterns spaced apart from each other on a cross section. Therefore, even after being separated into individual light emitting diode chips, it is possible to further prevent the bending of each chip.

Meanwhile, the metal patterns may be formed using a plating technique. Accordingly, the metal patterns may be easily formed by selectively plating a metal material.

Another aspect of the invention provides a vertical light emitting diode. This light emitting diode includes a conductive substrate. Compound semiconductor layers are positioned on the conductive substrate. The compound semiconductor layers include a first conductive compound semiconductor layer, an active layer, and a second conductive compound semiconductor layer. Meanwhile, a metal pattern is disposed on the conductive substrate to face the compound semiconductor layers. The metal pattern is located within a region of the conductive substrate. In addition, electrode pads are disposed on the compound semiconductor layers to face the conductive substrate. According to this aspect, a metal pattern is located on a conductive substrate to prevent bending of the light emitting diode. In addition, since the metal pattern is limited in the area of the conductive substrate, a plurality of light emitting diodes can be easily provided using a single conductive substrate.

On the other hand, the metal pattern may have lower patterns spaced apart from each other on the cross section. Therefore, the stress caused by the metal pattern can be reduced, thereby further preventing warping of the compound semiconductor layers.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to ensure that the spirit of the present invention can be fully conveyed to those skilled in the art. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, and the like of the components may be exaggerated for convenience. Like numbers refer to like elements throughout.

2 is a cross-sectional view illustrating a method of manufacturing a vertical light emitting diode according to an exemplary embodiment of the present invention, and FIG. 3 is a plan view illustrating a metal pattern applicable to embodiments of the present invention.

Referring to FIG. 2A, compound semiconductor layers are formed on the sacrificial substrate 51. The sacrificial substrate 51 is generally a sapphire substrate, but may be another hetero substrate. The compound semiconductor layers include a first conductive compound semiconductor layer 55, an active layer 57, and a second conductive compound semiconductor layer 59. The compound semiconductor layers are III-N-based compound semiconductor layers, and may be grown by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The first conductivity type and the second conductivity type represent N-type and P-type, or P-type and N-type.

Meanwhile, before forming the compound semiconductor layers, the buffer layer 53 may be formed. The buffer layer 53 is adopted to mitigate lattice mismatch between the sacrificial substrate 51 and the compound semiconductor layers, and may generally be a gallium nitride-based material layer.

Referring to FIG. 2B, conductive substrates 61 are formed on the compound semiconductor layers. The conductive substrate 61 is a substrate such as Si, GaAs, GaP, AlGaINP, Ge, SiSe, GaN, AlInGaN or InGaN, but Al, Zn, Ag, W, Ti, Ni, Au, Mo, Pt, Pd, Cu It may be formed by attaching a single metal of Cr or Fe or an alloy substrate thereof on the compound semiconductor layers. In this case, the conductive substrate 61 may be attached to the compound semiconductor layers through the bonding layer 63, and a reflective layer (not shown) may be interposed between the conductive substrate 61 and the compound semiconductor layers. have. On the other hand, the conductive substrate 61 may be formed using a plating technique. That is, the conductive substrate 61 may be formed by plating a metal such as Cu or Ni on the compound semiconductor layers by using a plating technique.

The coefficient of thermal expansion of the conductive substrate 61 may be controlled using alloying technology, but is not essential. In addition, the conductive substrate 61 does not need to be thick, unlike the prior art for preventing warpage.

On the other hand, when the sacrificial substrate 51 is separated by using a laser lift off (LLO) technology, the surface of the compound semiconductor layers may be damaged. This may be because the interface between the sacrificial substrate 51 and the first conductivity type compound semiconductor layer 55 is heated to a high temperature by the energy of the laser, and thus gas is generated as the buffer layer 53 is decomposed. Therefore, in order to discharge the gas generated in the laser lift-off process, the compound semiconductor layers may be patterned in advance before the conductive substrate 61 is formed. In this case, the compound semiconductor layers may be patterned along a scribing line, and thus individual LED chip regions may be defined. Thereafter, the conductive substrate 61 is formed.

Subsequently, metal patterns 65 are formed on the conductive substrate 61. The metal patterns 65 may be selectively formed of, for example, Cu or Ni using a plating technique. The metal patterns are spaced apart from each other along the scribing line 67. That is, the metal patterns 65 are located in individual LED chip regions, whereby a scribing line 67 is defined, and the conductive substrate 61 is exposed at the scribing line 67. .

On the other hand, each of the metal patterns 65 may be a single pattern of a polygonal cylindrical shape, such as a cylindrical or square cylinder. In contrast, each of the metal patterns 65 may have subpatterns 65a, 65b, and 65c spaced apart from each other on a cross section. The conductive substrate 61 is exposed in the chip region by the subpatterns spaced apart from each other. As the lower patterns 65a, 65b and 65c are formed, the stress of the conductive substrate 61 in the chip region is reduced.

Various shapes of the metal pattern 65 having lower patterns are illustrated in FIGS. 3A to 3C. Referring to these, the subpatterns may be defined by concentric grooves (a), a matrix of small squares (b), or (c) with rectangles arranged about the squares. In addition, it may be formed in various patterns.

Referring to FIG. 2C, the sacrificial substrate 51 is separated from the compound semiconductor layers. The sacrificial substrate 51 may be separated by laser lift off (LLO) technology or other mechanical or chemical methods. In this case, the buffer layer 53 is also removed to expose the first conductive compound semiconductor layer 55.

Subsequently, electrode pads 69 are formed on the LED chip regions. The electrode pads 69 are ohmic contacted to the first conductivity type compound semiconductor layer 55.

Referring to FIG. 2 (d), a vertical light emitting diode is completed by cutting the conductive substrate 61 along the scribing lines 67 and separating them into individual LED chips. Here, since the metal patterns 65 are spaced along the scribing lines 67, there is no need to cut the metal patterns 65, and by cutting the conductive substrate 61 together with the compound semiconductor layers. Separated into individual light emitting diode chips. Therefore, since the relatively thin conductive substrate 61 can be cut by using a laser or the like and separated into individual chips, cutting is easy. In particular, when the compound semiconductor layers are patterned in advance before the conductive substrate 61 is formed, it may be separated into individual LED chips by cutting only the conductive substrate 61.

According to the present embodiment, a vertical light emitting diode in which compound semiconductor layers are positioned on a conductive substrate 61 is provided. The compound semiconductor layers include a first conductivity type compound semiconductor layer 55, an active layer 57, and a second conductivity type compound semiconductor layer 59. Meanwhile, the metal pattern 65 is disposed on the conductive substrate 61 to face the compound semiconductor layers. The metal pattern 65 is defined in the region of the conductive substrate 61. In addition, an electrode pad 69 is positioned on the compound semiconductor layers to face the conductive substrate 61.

The vertical light emitting diode may prevent the compound semiconductor layers from bending by adopting the metal pattern 65 on the conductive substrate 61. In addition, since the metal pattern 65 has sub-patterns 65a, 65b, and 65c spaced apart from each other on a cross section, the stress of the conductive substrate 61 is further reduced. Accordingly, the compound semiconductor layers can be further prevented from bending.

According to embodiments of the present invention, by adopting metal patterns defining scribing lines, it is possible to prevent warpage of the compound semiconductor layers and to increase the thickness of the conductive substrate that needs to be cut. Separation process is easy. In addition, by forming the metal patterns to have sub-patterns, the stress of the conductive substrate can be reduced even after being separated into individual LED chips, thereby further preventing warpage of the LED.

Claims

Forming compound semiconductor layers including the first conductive compound semiconductor layer, the active layer, and the second conductive compound semiconductor layer on the sacrificial substrate,

Forming a conductive substrate on the compound semiconductor layers,

Forming metal patterns defining scribing lines on the conductive substrate,

Separating the sacrificial substrate from the compound semiconductor layers to expose a first conductive compound semiconductor layer,

Forming an electrode pad on the first conductivity type compound semiconductor layer,

And cutting the conductive substrate along the scribing lines and separating the conductive substrate into individual LED chips.

The method according to claim 1,

Each of the metal patterns has a sub-pattern spaced apart from each other on the cross-section of the vertical light emitting diode manufacturing method.

The method according to claim 1,

The metal pattern is a vertical light emitting diode manufacturing method formed using a plating technique.

Conductive substrates;

Compound semiconductor layers on the conductive substrate and including a first conductivity type compound semiconductor layer, an active layer, and a second conductivity type compound semiconductor layer;

A metal pattern positioned on the conductive substrate to face the compound semiconductor layers, the metal pattern being defined in an area of the conductive substrate;

And a electrode pad disposed on the compound semiconductor layers opposite the conductive substrate.

The method of claim 4,

The metal pattern is a vertical light emitting diode having a lower pattern spaced apart from each other on the cross section.