KR101226899B1 - Digital-to-Analog Converter using 2D INL bounded switching scheme - Google Patents

Abstract

The technical field of the present invention relates to a digital-to-analog converter (DAC), and more particularly, to a DAC applying an INL bounded switching technique, and more particularly, to an existing INL bounded switching technique in applying an INL bounded switching technique. It is about the DAC to change the use.
The DAC disclosed herein uses a two-dimensional INL bounded switching technique based on a current cell matrix structure, and switching (selection) each current cell constituting the matrix for converting a digital signal input to the DAC into an analog output signal. Is implemented through a row and column decoding method, wherein the switching is performed by dividing the cell matrix into two quadrants up and down and two bilaterally to the left and right to be located in the first and third quadrants of the cell matrix. Cells are preferentially switched, and cells located in the second and fourth quadrants are subsequently switched to solve the problem of the present invention.

Description

Digital-to-Analog Converter using 2D INL bounded switching scheme}

The technical field of the present invention relates to a digital-to-analog converter (DAC), and more particularly, to a DAC applying an INL bounded switching technique, and more particularly, to an existing INL bounded switching technique in applying an INL bounded switching technique. It is about the DAC to change the use.

As digital video devices are recently integrated with networking technology, high-speed wireless communication technology capable of transmitting high-definition video data by wirelessly connecting multimedia devices requiring high-speed data transmission or wireless USB technology for wirelessly connecting computers and peripheral devices. Is required, and high-speed wireless personal communications such as IEEE 802.15.3 can transmit data at lower power than conventional Wireless Local Area Networks (WLANs) for application to battery-powered portable devices. Rate Wireless Personal Area Network (HR-WPAN) technology is being actively developed. In particular, IEEE 802.15.3 HR-WPAN with a data rate of 55 [Mbps] is being replaced by HR-WPAN technology such as Ultra-Wide Band (UWB) with a data rate of 480 [Mbps]. Increasing production costs by integrating more blocks into the System-on-a-Chip (SoC) for wireless communications through the CMOS process.

This low power high speed wireless data communication system has a high-speed digital-to-analog converter (DAC) that has a resolution of 6 bits or more, an operating speed of 1 [GS / s] or more, and a low power supply voltage and small area. ) Is required.

The present invention proposes a high-speed DAC having a resolution of 6 bits or more and an operating speed of 1 [GS / s] or more, which can be implemented with a low power supply voltage and a small area. To provide a DAC with an INL bounded switching technique that minimizes the glitch energy that has the greatest impact on the system and ensures linearity in integral non-linearity (INL) characteristics.

DAC disclosed in the present specification for solving the above problems is

A two-dimensional INL bounded switching technique based on a current cell matrix structure is used, and switching (selection) of each current cell constituting the matrix for converting a digital signal input to the DAC into an analog output signal is performed. The first and third quadrants of the cell matrix may be implemented by using a row-column decoding scheme, wherein the switching through the decoding scheme divides the cell matrix into two quadrants up and down and two bilaterally to the left and right. The cells located in the quadrant are preferentially switched, and the cells located in the second and fourth quadrants are subsequently switched to solve the problem of the present invention.

The DAC according to the present invention can realize low power supply voltage and small area, minimize glitch energy, and guarantee linearity in INL characteristics, and thus require a resolution of 6 bits or more and an operation speed of 1 [GS / s] or more. Can be easily applied to

1 is a view showing the overall configuration of the DAC according to the present invention.
2 is a view showing an example of the configuration of a digital interface (digital interface) that can be implemented in the DAC according to the present invention.
3 is a diagram illustrating a basic current cell structure applied to a DAC according to the present invention, in which a dummy switch is added.
4 is a small area master-slave deglitching circuit applied to the DAC according to the present invention.
5 is a diagram illustrating a current cell matrix of a DAC to which a current cell switching technique according to the present invention is applied.
6A and 6B show the results of experiments on the two-dimensional gradient error and the two-dimensional symmetric error of the conventional two-dimensional hierarchical structure and the two-dimensional INL bounded switching method according to the present invention with a leveled error range of -1 to 1. Figure is presented.
7 is a diagram showing an example of a chip layout of a DAC according to the present invention.
8 is a diagram showing an example of measurement results of differential non-linearity (DNL) and INL of the DAC according to the present invention.
9 is a view showing an example of the spectrum of the analog output signal of the DAC according to the present invention.
10 is a diagram showing an example of Spurious-Free Dynamic Range (SFDR) which is a dynamic performance of the DAC according to the present invention.

Prior to the description of the concrete contents for carrying out the present invention, for the sake of understanding, an outline of a solution to the problem to be solved by the present invention is firstly presented.

The implementation of a high speed DAC generally employs a binary-weighted current cell array structure or a current driving scheme using a current cell matrix structure. The binary current column structure eliminates the need for additional circuitry, such as a decoder that converts binary-weighted codes into thermometer codes, enabling high-speed operation with small footprint, but with process variables. Mismatch of the current source due to the change of current and large glitch energy due to the code change limit the overall performance of the DAC.

On the other hand, when using the current cell matrix structure, low glitch energy and monotonicity can be guaranteed, but the area occupied by the connection line between the decoder and the current cell increases the overall area of the DAC and delays the propagation of logic gates generated by the complex decoder. Due to time, the maximum operating speed is limited. In order to solve this disadvantage, a simple circuit is implemented by using a decoder method for driving rows and columns in a current cell matrix structure, thereby reducing the area of connection lines while applying to high-speed operation.

On the other hand, the mismatch of the current source due to any error that degrades static performance such as DNL or INL is [V _GS -V _TH ] for all transistors to operate in the saturation region within the analog output range. The channel width (W) and the channel length (L) of the eddy current source transistor can be reduced. Accumulation of errors due to gradient and symmetrical errors in rows and columns caused by process-related errors in the current source array, thermal distribution within the chip, and voltage drops on the power lines can lead to various current cell switching (selections). The technique can be minimized.

On the other hand, at high operating frequencies, the low output impedance of the current cell, incomplete synchronization of the switch drive signal, the voltage variation of the drain node of the current source transistor, the feed-through of the digital signal, and the time difference of turning on and off each current cell In addition, it is a factor that limits the dynamic performance of the DAC. To solve this, a circuit such as flip-flop or latch is added in front of the deglitching circuit or a master-slave deglitching circuit is applied. Due to the additional circuitry and complexity of the circuit, there is a problem of increasing the total area and power consumption of the DAC.

The DAC according to the present invention applies a 6-bit current cell matrix structure to ensure linearity and have low glitch energy while satisfying a 6-bit resolution and an operating speed of 1.4 [GS / s], and implements a digital interface at the digital input stage. Depending on the application, the data can be processed serially or in parallel. In addition, by applying the basic current cell structure, it can stably generate the analog output value of up to 0.6 [V _{p -p} ] at the low supply voltage of 1.0 [V] and output the current cell satisfying the required resolution with small area. Have an impedance.

The master-slave deglitching circuit according to the present invention improves the performance degradation due to the glitch energy and the delay time between the current cells in a small area, and the two-dimensional INL bounded switching technique based on the row-column decoder method Compensation for the inclination of the row and column and the symmetry error occurring in the original array improves the INL characteristics and minimizes the propagation delay time by the decoder to be suitable for high speed operation.

DETAILED DESCRIPTION OF EMBODIMENTS Hereinafter, specific details for carrying out the present invention will be described in detail with reference to the accompanying drawings, based on the preferred embodiments of the present invention. Although the same reference numerals have been given in the drawings, it will be noted that in the description of the drawings may refer to components of other drawings if necessary. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 is a view showing the overall configuration of the DAC according to the present invention.

The DAC according to the present invention has a 6-bit resolution and 1.4 [GS / s] operating speed and can be implemented in a 65 [nm] CMOS process. 1, based on a current cell matrix structure consisting of 63 current cells, a digital interface, a clock generator, a row decoder, a column decoder, a column array of currents (current source array), on-chip reference current generator, etc.

The DAC according to the present invention selects data of one or four input channels (CH1 to CH4) according to the application and generates an output current of 6 [mA] for driving a load resistor R _L of 50 [Ω]. And output an analog value up to 0.6 [V _{p -p} ]. On the other hand, the clock signals Q and QB for the organic operation of each block are generated inside the chip using a single clock from the outside. Techniques for reducing process errors, such as separating current sources and current cell switches, and adding dummy current sources at the same time as layout techniques to reduce interference between analog and digital blocks. In addition, by integrating a current reference circuit consisting only of CMOS transistors independent of temperature changes and changes in supply voltage on-chip, and controlling the reference current with an external digital code, the range of output voltage and output current according to the characteristics of the application. Allow to change

Hereinafter, each detail of the DAC according to the present invention will be described in detail.

<Digital Interface for Multiple Channels>

According to the present invention, the DAC includes a digital interface having four input channels in front of a row-column decoder (ROW-COLUMN DECODER) as shown in FIG. 2 and an up converter of a quadrature modulator composed of I / Q channels. It can be applied to an up converter or for immediate application to digital circuits that output data at regular intervals, such as barrel shifters. That is, as shown in FIG. 2, the digital control signal DCON is provided to receive input data on one channel CH1 or to receive input data that is 1/4 of the operating frequency on four channels CH1 to CH4. After converting the channel data (D [0: 5]), the data can be sequentially transmitted to the decoder of the row and column. A buffer and latch are added at the front of the digital interface to eliminate delays between input data.

<Base current cell>

The DAC according to the present invention processes a digital input signal up to 700 [MHz] at a high operating frequency of 1.4 [GS / s] with a low supply voltage of 1.0 [V] to output an analog output signal up to 0.6 [V _{p -p} ]. Enable the creation of. The magnitude of the channel width (W) and the channel depth (L) of the current source MOS transistor can be determined by applying the following equation (1) to minimize mismatch of the current source and the following equation (2) considering the current flowing in the current cell. Through these two equations, the size of W and L and the value of [V _GS -V _TH ] of the MOS transistor can be adjusted to design the MOS transistor to have a minimum area while operating in the saturation region. In equations (1) and (2), V _GS , V _TH , I _LSB , and σ (I) / I are the gate-source voltage of the current source, the threshold voltage of the transistor, and the Least Significant Bit (LSB), respectively. The standard deviation of the output current of the LSB considering the output current and the INL yield, and A _β and A _VTH represent mismatch parameters for device mobility and mismatch parameters for threshold voltages provided by the process, respectively.

--- 식(1).

--- Equation (1).

--- 식(2).

--- Equation (2).

In addition, the output impedance of the current cell has an INL characteristic of 0.5 [LSB] or less for the improvement of linearity through Equation (3) and Equation (4) below, and SFDR is 6 bit at the Nyquist input frequency. Make sure that the analog output signal meets the required resolution by setting the resolution to 36 [dB] or more. In Eqs. (3) and (4), N, Z _o , R _L , and I _LSB represent the resolution, the output impedance of the current cell, the load resistance, and the output current of the LSB, respectively.

--- 식(3).

--- Equation (3).

--- 식(4).

--- Equation (4).

On the other hand, the cascode current cell structure can realize a large output impedance, but [V _GS for stably generating an analog output of up to 0.6 [V _{p -p} ] at a low supply voltage of 1.0 [V]. -V _TH ] value decreases and the size of the transistors W and L increases to reduce mismatch of the current source based on Equation (1). On the other hand, the DAC according to the present invention applies a basic current cell structure as shown in FIG. 3 to obtain an output impedance satisfying low INL and high SFDR required for a small area. The basic current cell structure, on the other hand, adds a dummy switch to the output node and applies a switch driving signal S and a signal SB opposite in phase to affect the analog output signal. Minimize the impact.

<Deglitching Circuit Applied to DAC According to the Present Invention>

In general, a high-speed DAC uses a de-glitching circuit that adjusts a crossover point of switch drive signals S and SB to reduce the glitch energy caused by the variation of the drain node voltage V _DS of the current source transistor. The operating speed of such deglitching circuits tends to limit the settling time. The deglitching circuit using the inverter is limited in operation speed due to the difference of the two signals due to the delay of the propagation time of the logic gate, while the latching method eliminates the difference between the two signals by simultaneously generating the two signals in the rising and falling operation. It is widely applied to high speed operation.

On the other hand, fluctuations in the settling behavior of the output signal due to the time difference between on and off of each current cell degrade the SFDR, so adding circuits such as D-flip-flops, latches before the de-glitching circuit, or master-slave. By applying a deglitching circuit, it is possible to maintain a constant fixing operation regardless of an input code even in a high speed operation, but there is a disadvantage in that the area is increased due to additional elements.

The deglitching circuit according to the present invention is a master-slave deglitching circuit, and as shown in FIG. 4, using a small number of elements, the decoder output D _IN is received and synchronized with the clock signals Q and QB to generate a switch driving signal. And minimize the time difference between the current cells.

First, the master latch consists of two crossed minimum size inverters and stores the decoder output signal value when the clock signal QB is “HIGH”. When the clock signal Q becomes "HIGH", the decoder output signal stored in the master latch is applied to the slave latch to generate the switch drive signal, and maintain the signal value generated when the clock signal Q is "LOW". do. On the other hand, the slave latch properly adjusts the size of NMOS and PMOS to determine the intersection point (0.85 [V]) when the voltage change of the drain node of the current source transistor is the smallest, and stably at a high operating speed of 1 [GHz] or more. To work.

The number of transistors used in the master-slave deglitching circuit according to the present invention is 60% higher in area efficiency than that of the conventional master-slave deglitching circuit.

Two-dimensional INL bounded switching for improved linearity

Various current cell switching techniques have been developed to compensate for the accumulation of slope error and symmetry error between current sources in a current cell matrix structure for high speed DAC. Q ² random walk, which has the best INL characteristics, has a disadvantage in that the implementation area is very large due to the complicated decoder and routing, and the operation speed is limited due to the parasitic capacitance generated. Therefore, a row-column decoder-based current cell switching technique that can divide binary input data into rows and columns to form a simple decoder has been applied to high-speed DACs in recent years.

Meanwhile, the table below compares the INL bounded algorithm with superior INL characteristics and the hierarchical symmetrical sequence technique among the existing row and column decoder based switching schemes in one dimension. The numbers listed in the upper table of the following table indicate the current cell switching order, which is an optimal switching order obtained by a great number of experiments in order to reduce the symmetry error and the slope error and have excellent INL characteristics.

Referring to the lower table of the following table, it can be seen that the one-dimensional INL bounded algorithm is superior to the hierarchical symmetric sequence method considering both the symmetry error and the slope error. However, when a simple two-dimensional switching technique using the one-dimensional INL bounded algorithm is applied to the row and column decoding method, the error of the row or the column accumulates. Simple application here means that the switching order of the rows and the switching order of the columns (current cell selection order) are the same in the order of the INL bounded algorithm shown in the following table.

Therefore, the current cell switching method according to the present invention applies the INL bounded switching method by extending the two-dimensional method so that the error component is the smallest in one dimension, and the switching order of the rows and columns and the switching order of the rows are different from each other. Try to minimize the error.

The current cell matrix of the DAC to which the current cell switching technique according to the present invention is applied is shown in FIG. 5, which is an optimal switching sequence obtained by very many experiments in order to minimize the above-mentioned first error and have excellent INL characteristics. . Referring to FIG. 5, the current cell matrix is composed of 64 current cells, and one shaded cell is a dummy cell, which is mentioned above to reduce errors in a DAC manufacturing process.

In Fig. 5, numerals 1 to 63 represent the switching order of the current cells, which is the same as the INL bounded algorithm shown in the following table for the column, and the switching order for the left and right for the row. Are different. If we look more closely, we first divide the 64 cell matrices into two quarters of two, up and down, and two to the left and right, so that the cells in the first and third quadrants are preferentially switched, and the second and fourth quadrants The switching order of the left row and right row is ordered to switch cells later.

The biggest principle of the switching order largely follows the switching order (2,6,4,8,5,1,7,3) for eight columns. That is, the cell in the sixth column is ranked first, the cell in the first column is ranked second, the cell in the eighth column is ranked third, the cell in the third column is ranked fourth, and the cell in the fifth column is 5th. By rank, the cells in the second column are switched to sixth, the cells in the seventh column to seventh, and the cells in the fourth column to eighth.

In addition, referring to FIG. 5, such switching is alternately switched between four cells of the first quadrant and four cells of the third quadrant with respect to eight cells having the same row switching order. That is, cells located in the row having the first row switching order (third row in the first quadrant and the eighth row in the third quadrant) are alternately switched cell by cell, and the cells in the row having the row switching order no. After switching for the eight cells, the cells in the row with the second row switching order (first row for the first quadrant and sixth row for the third quadrant) are similarly crossed according to the switching order for the eight columns. Is switched to.

After switching of cells located in the first and third quadrants is completed, switching of the cells located in the second and fourth quadrants is performed in the same manner as the cells of the first and third quadrants.

The row decoder and column decoder divide the 6-bit digital input into 3 bits each and arrange the outputs of the decoder according to the position of the current cell to facilitate high speed operation. The decoder circuits used are OR-NAND and 3 inputs. Concisely constructed using NAND gates.

6A and 6B show the results of experiments on the two-dimensional gradient error and the two-dimensional symmetric error of the conventional two-dimensional hierarchical structure and the two-dimensional INL bounded switching method according to the present invention with a leveled error range of -1 to 1. Figure is presented. 6A is an experimental result for the two-dimensional tilt error, and FIG. 6B shows an experimental result for the two-dimensional symmetry error. As a result, when comparing the maximum INL for the two-dimensional gradient error and the two-dimensional symmetry error, it can be seen that the two-dimensional INL bounded switching method according to the present invention is superior to the conventional two-dimensional symmetric switching method. Here, (i) is a case of two-dimensional INL bounded switching scheme according to the present invention, and (ii) is a case of symmetric switching technique of two-dimensional hierarchical structure.

<Chip Layout of DAC According to the Present Invention>

The 6-bit 1.4 [GS / s] DAC according to the present invention can be fabricated in a chip of 65 [nm] CMOS process, and the maximum output current is 0.6 [V _{p -p} ] up to 50 [Ω] considering the load resistance. It was designed as 6 [mA] to be analog output value. In addition, the current cell switch is arranged symmetrically around the current source and at the same time separates the analog block and the digital block to reduce interference between the digital signal and the analog signal, and a dummy current source is added around the current cell array to add current. Minimize circle mismatch.

The chip layout of the DAC according to the present invention is shown in FIG. 7 and the area of the DAC excluding the input and output pads is 0.11 [mm ² ].

In addition, the performance of the DAC according to the present invention was measured under the condition of driving 51 [Ω] load resistance among thin film chip resistors having excellent resistance value tolerance and resistance temperature coefficient characteristics, and excellent current noise characteristics and high frequency characteristics. INL is at levels of up to 0.18 [LSB] and 0.11 [LSB], respectively, as shown in FIG. 8. The DAC according to the present invention consumes 11.9 [mW] at a supply voltage of 1.0 [V] and an operating speed of 1.4 [GS / s].

9 is a diagram showing the spectrum of the analog output signal of the DAC according to the present invention measured at 5 [MHz] output frequency and 1.4 [GS / s] operating speed. SFDR is 40.8 [dB] at maximum.

10 is a diagram showing the dynamic performance of the DAC according to the present invention, Figure 10 is 5 [MHz] when increasing the operating frequency (sampling frequency) of the DAC from 200 [MS / s] to 1.4 [GS / s] ] Is the SFDR at the output frequency.

Referring to FIG. 10, it can be observed that SFDR remains almost constant regardless of the operation speed, which means stable operation of the DAC according to the present invention.

So far I looked at the center of the preferred embodiment for the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

Claims (4)

For Digital-to-Analog Converter (DAC) using two-dimensional INL bounded switching scheme based on current cell matrix structure:
The switching (selection) of each current cell constituting the matrix for converting the digital signal input to the DAC into an analog output signal is implemented through row-column decoding,
The switching through the decoding scheme divides the cell matrix up and down and to the left and right into four quarters, so that cells located in the first and third quadrants of the cell matrix are preferentially switched. DAC using a two-dimensional INL bounded switching technique, characterized in that cells located in the fourth quadrant are to be switched later. The method of claim 1, wherein the switching of each current cell is
Based on the switching order given for the columns of the matrix, and after the cells of the first quadrant and the cells of the third quadrant having the same row switching order are switched alternately on a cell basis, the second quadrant and the first quadrant Cells of the quadrant 4 are switched in the same manner as the cells of the first quadrant and the cells of the third quadrant are switched. The method of claim 2,
And the column and row decoding are performed by dividing the number of bits of the input digital signal by half. The method of claim 3, wherein
The deglitching circuit applied to the DAC is a master-slave deglitching circuit,
The master-slave deglitching circuit is a DAC using a two-dimensional INL bounded switching technique, characterized in that it consists of a master latch implemented by two intersected inverters and a slave latch implemented by NMOS and PMOS.

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