KR101204613B1 - Semiconductor component and method for manufacturing of the same - Google Patents

Abstract

The present invention provides a semiconductor device and a method of manufacturing the same. A semiconductor device according to an embodiment of the present invention is a base substrate, a depletion-mode High Electron Mobility Transistor (HEMT) structure disposed on the base substrate, disposed on the base substrate, and in series with the depletion-mode HEMT structure And a connected enhancement-mode HEMT structure and a first diode structure disposed on the base substrate and connected in parallel to the increase-mode HEMT structure.

Semiconductor devices, diodes, high electron mobility transistors, depletion mode, increasing mode, two-dimensional electron gas,

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR COMPONENT AND METHOD FOR MANUFACTURING OF THE SAME}

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a nitride-based semiconductor field effect transistor structure and a method of manufacturing the same.

Generally, III-nitride based semiconductors containing group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen (N) have a wide energy band gap, high electron mobility and saturated electron velocity, and It has characteristics such as high thermochemical stability. Such III-nitride-based semiconductor-based field effect transistors (N-FETs) are semiconductor materials having a wide energy band gap, such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), and indium. It is manufactured based on materials such as gallium nitride (InGaN) and aluminum indium gallium nitride (AlINGaN).

A general nitride field effect transistor has a so-called High Electron Mobility Transistor (hereinafter referred to as 'HEMT') structure. For example, the HEMT structured semiconductor device may include a base substrate, a nitride based semiconductor layer formed on the base substrate, a source electrode and a drain electrode disposed on the semiconductor layer, and the semiconductor layer between the source electrode and the drain electrode. A gate electrode disposed on the substrate. Such a semiconductor device may generate a 2-Dimensional Electron Gas (2DEG) that is used as a movement path of a current in the semiconductor layer. However, the nitride-based field effect transistor having the above structure has a low resistance between the drain electrode and the source electrode when the gate voltage is 0 or negative (-), so that the current flows in the on-state. Current and power dissipation in the device degrade the device's high voltage and high current operating characteristics.

In addition, the semiconductor device having a general HEMT structure may include at least one of a depletion-mode HEMT structure and an enhancement-mode HEMT structure. When the gate voltage is 0 volts, the depletion mode HEMT structure is in an 'on' state where current flows due to low resistance between the drain electrode and the source electrode. In this case, consumption of current and power is generated, thereby degrading high voltage and high current operating characteristics of the semiconductor device. Accordingly, the semiconductor device having the depletion mode HEMT structure has a disadvantage of applying a separate negative voltage to the gate electrode in order to maintain an 'off' state. In contrast, the semiconductor device having the incremental mode HEMT structure can be normally off even without applying a separate voltage to the gate electrode. However, the semiconductor device having the incremental mode HEMT structure has a lower electrical characteristic such as a lower current density and a higher breakdown voltage than a depletion mode HEMT structure having a normally on structure.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of high voltage and high current operation and a method of manufacturing the same.

Disclosure of Invention Problems to be Solved by the Invention The present invention is to provide a semiconductor device and a method of manufacturing the same, which maintain the normally off state and improve electrical characteristics without applying a separate voltage.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a reduced amount of leakage current and a method of manufacturing the same.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method of manufacturing the same that increase the amount of current during device operation.

A semiconductor device according to the present invention is a base substrate, a depletion-mode High Electron Mobility Transistor (HEMT) structure disposed on the base substrate, disposed on the base substrate, and in series with the depletion-mode HEMT structure. And a connected enhancement-mode HEMT structure, and a first diode structure disposed on the base substrate and connected in parallel to the increase-mode HEMT structure.

According to an embodiment of the present invention, the first diode structure may provide a forward current flow path together with the increase-mode HEMT structure in the forward operation of the semiconductor device.

According to an embodiment of the present invention, the first diode structure may have a lower breakdown voltage than the increase-mode HEMT structure.

According to an embodiment of the present invention, a second diode structure may be connected to a source electrode of the increase-mode HEMT structure and a drain electrode of the depletion-mode HEMT structure.

According to an embodiment of the present invention, the second diode structure may provide a reverse current flow path along with the first diode structure in a reverse operation of the semiconductor device.

According to an embodiment of the present invention, the second diode structure may have a lower breakdown voltage than the increase-mode HEMT structure.

The semiconductor device according to the present invention includes a base substrate including a first region, a second region, and a third region, and a two-dimensional electron gas disposed on the base substrate and providing a current movement path therein. 2DEG), an insulating pattern disposed on the semiconductor layer, source / drain and cathode electrode patterns formed on the semiconductor layer and the insulating pattern, and a gate formed on the semiconductor layer and the insulating pattern yarn, and An anode electrode pattern, wherein the semiconductor layer, the insulating pattern, the source / drain and cathode electrode patterns, and the gate and anode electrode patterns formed on the first region form a depletion-mode HEMT structure, and the second The semiconductor layer formed on the region, the insulating pattern, the source / drain and cathode electrode patterns, and the gate and anode electrode patterns Is an incremental-mode HEMT structure connected in series with the depletion-mode HEMT structure, wherein the semiconductor layer, the insulation pattern, the source / drain and cathode electrode patterns, and the gate and anode electrode patterns formed on the third region are A first diode structure is formed that is connected in parallel to the incremental-mode HEMT structure.

According to an embodiment of the present invention, the first diode structure may have a lower breakdown voltage than the increase-mode HEMT structure.

According to an embodiment of the present invention, the gate and anode electrode patterns provide a gate electrode of the depletion-mode HEMT structure and an anode electrode connected to the gate electrode, and the source / drain and cathode electrode patterns are the depletion-mode HEMT. A drain electrode of the structure, a gate electrode of the incremental-mode HEMT structure, and a cathode electrode provided to the first diode structure may be provided.

According to an embodiment of the present invention, the source electrode of the depletion-mode HEMT structure and the drain electrode of the incremental-mode HEMT structure may be formed by sharing the same portions of the source / drain and cathode electrode patterns.

In example embodiments, the semiconductor layer may include a first semiconductor layer disposed on the base substrate and a second semiconductor layer disposed on the first semiconductor layer and having a wider energy band gap than that of the first semiconductor layer. May comprise a membrane.

In example embodiments, the base substrate further includes a fourth region, wherein the semiconductor layer, the insulating pattern, the source / drain and cathode electrode patterns, and the gate and anode electrode patterns are formed in the fourth region. A second diode structure may be connected in parallel with the depletion-mode HEMT structure and the incremental-mode HEMT structure.

According to an embodiment of the present invention, the second diode structure is reversed from the source electrode of the incremental-mode HEMT structure to the drain electrode of the depletion-mode HEMT structure together with the first diode structure in the reverse operation of the semiconductor device. Can provide current flow.

According to an embodiment of the present invention, the source / drain and cathode electrode patterns formed in the first region may include first and second metal patterns spaced apart from each other via the gate and anode electrode patterns. .

In an embodiment, the gate and anode electrode patterns may include a third metal pattern spaced apart from the first and second metal patterns between the first and second metal patterns in the first region. Including the first to third metal patterns may be curved in a plurality of times in the first region.

In example embodiments, the source / drain and cathode electrode patterns and the gate and anode electrode patterns may be formed of the same metal material.

A method of manufacturing a semiconductor device according to the present invention may include preparing a base substrate, forming a depletion-mode High Electron Mobility Transistor (HEMT) structure on the base substrate, and performing the depletion on the base substrate. Forming an enhancement-mode HEMT structure in series with a mode HEMT structure, and forming a first diode structure in parallel with the increase-mode HEMT structure on the base substrate.

According to an embodiment of the present invention, the method may further include forming a second diode structure on the base substrate, the second diode structure being connected to the source electrode of the incremental-mode HEMT structure and the drain electrode of the depletion-mode HEMT structure.

According to an embodiment of the present invention, the second diode may be formed to have a breakdown voltage lower than the threshold voltages of the source and drain electrodes of the increase-mode HEMT structure.

According to an embodiment of the present invention, the first diode may be formed to have a breakdown voltage lower than the threshold voltages of the source and drain electrodes of the increase-mode HEMT structure.

In the method of manufacturing a semiconductor device according to the present invention, the method includes preparing a base substrate having a first region, a second region, and a third region, and forming a two-dimensional electron gas (2DEG) therein on the base substrate. A second step of forming an insulating pattern on the semiconductor layer, a second step of forming a source / drain and a cathode electrode pattern on the semiconductor layer and the insulating pattern, and on the semiconductor layer and the insulating pattern And a third step of forming a gate and anode electrode pattern, wherein the first step, the second step, and the third step comprise a depletion-mode High Electron Mobility Transistor (HEMT) on the first area. ) Forming a structure, forming an enhancement-mode HEMT structure in series with the depletion-mode HEMT structure on the second region, and forming an image on the third region. Increase-mode HEMT structure may include forming a first diode structure in parallel connection.

According to an embodiment of the present invention, the second step includes forming a first metal film on the semiconductor layer and patterning the first metal film, wherein the third step comprises the first step on the semiconductor layer. The method may include forming a second metal film having a different metal from the first metal film, and patterning the second metal film.

In an embodiment, the second and third steps may include forming a metal film on the semiconductor layer and patterning the metal film to form the source / drain and cathode electrode patterns and the gate and anode electrode patterns. And forming at the same time.

According to an embodiment of the present invention, the base substrate further includes a fourth region, wherein the first, second and third steps are source electrodes of the incremental-mode HEMT structure on the fourth region. And forming a second diode structure connected to the drain electrode of the depletion-mode HEMT structure.

The semiconductor device according to the present invention includes a depletion mode HEMT structure having a normallyal structure formed on a single base substrate, an increase mode HEMT structure having a normally off structure, and a diode structure for increasing the amount of forward current. Accordingly, the semiconductor device according to the present invention has both high current density and breakdown voltage characteristics of the depletion mode HEMT structure and normally off characteristics of the incremental mode HEMT structure, and increases the amount of current in the forward operation, thereby improving high current and high voltage characteristics. do.

The semiconductor device according to the present invention includes a depletion mode HEMT structure formed on a single base substrate, an increase mode HEMT structure, a first diode structure for increasing a forward current amount, and a second diode structure for improving reverse breakdown voltage. Accordingly, the semiconductor device according to the present invention improves the amount of current in the forward operation, the breakdown voltage is increased in the reverse operation to improve the high current and high voltage characteristics.

In the semiconductor device according to the present invention, an insulating film is formed between the low resistance layer and the gate structure, and thus, when no voltage is applied to the gate structure, a normal current is turned off even when a voltage is applied to the source electrode and the drain structure. (normally off). Accordingly, the present invention can provide a semiconductor device having a high electron mobility transistor (HEMT) structure capable of an enhancement mode operation.

The semiconductor device manufacturing method according to the present invention may implement a depletion mode HEMT structure having a normallyal structure, an increase mode HEMT structure having a normally off structure, and a diode structure that increases a forward current amount on a single base substrate. Accordingly, the present invention provides a semiconductor device having both high current density and breakdown voltage characteristics of a depletion mode HEMT structure and normally off characteristics of an increase mode HEMT structure, and increasing current amount in a forward operation, thereby improving high current and high voltage characteristics. can do.

The semiconductor device manufacturing method according to the present invention may implement a depletion mode HEMT structure, an increase mode HEMT structure, a first diode structure for increasing a forward current amount, and a second diode structure for increasing a reverse breakdown voltage on a single base substrate. Accordingly, the present invention can increase the amount of current in the forward and reverse operation, it is possible to manufacture a semiconductor device with improved high current and high voltage characteristics.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments may be provided to make the disclosure of the present invention complete, and to fully inform the scope of the invention to those skilled in the art. Like reference numerals may refer to like elements throughout the specification.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is to be understood that the terms 'comprise', and / or 'comprising' as used herein may be used to refer to the presence or absence of one or more other components, steps, operations, and / Or additions.

In addition, the embodiments described herein will be described with reference to cross-sectional views and / or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of films and regions are exaggerated for effective explanation of technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include variations in forms generated by the manufacturing process. For example, the etched area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Hereinafter, a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram illustrating a semiconductor device in accordance with an embodiment of the present invention. Referring to FIG. 1, a semiconductor device according to an embodiment of the present invention may include a transistor and a diode that perform both depletion-mode and enhancement-mode operations. For example, the semiconductor device may include a high electron mobility transistor (hereinafter, referred to as a "depletion-mode HEMT") that performs the depletion-mode operation and the increase-mode operation. HEMT (hereinafter, referred to as 'increase-mode HEMT': 20) and a diode 30 electrically connected to the increase-mode HEMT 20.

The depletion-mode HEMT 10 may have a structure in which resistance between the drain electrode and the source electrode is lower than that of the increase-mode HEMT 20. For example, the depletion-mode HEMT 10 may have a negative threshold voltage, and the increase-mode HEMT 20 may have a positive threshold voltage. The incremental-mode HEMT 20 may be connected in series with the depletion-mode HEMT 10. The diode 30 may be connected in parallel to the incremental-mode HEMT 20. The diode 30 may have a schottky diode structure. The diode 30 may provide a current movement path through which the forward current of the semiconductor device flows together with the increase-mode HEMT 20 in the forward operation of the semiconductor device. To this end, the diode 30 may be designed to have a lower breakdown voltage than the increase-mode HEMT 20.

Such a designed semiconductor device includes a depletion-mode HEMT 10 having a normally on structure, an increase-mode HEMT 20 having a normally off structure, and a diode for increasing the amount of forward current. 30 may be provided. Accordingly, the semiconductor device has both high current density and breakdown voltage characteristics of the depletion-mode HEMT 10 and normally off characteristics of the increase-mode HEMT 20. This increases the amount of current, whereby the high current and high voltage characteristics can be improved.

The semiconductor device as described above may operate as follows.

2A and 2B are diagrams for describing an operation process of a semiconductor device according to example embodiments. More specifically, FIG. 2A illustrates a current flow in a forward operation of a semiconductor device according to an embodiment of the present invention, and FIG. 2B illustrates a current flow in a reverse operation of a semiconductor device according to an embodiment of the present invention. to be.

Referring to FIG. 2A, when a voltage larger than the threshold voltage between the gate electrode G and the source electrode S of the increase-mode HEMT 20 is applied to the gate electrode G, the increase-mode HEMT 20 ) Can be 'on'. In this case, the gate / source voltage of the depletion-mode HEMT 10 may be adjusted to approach zero. Accordingly, both the depletion-mode HEMT 10 and the increase-mode HEMT 20 may be turned on. Here, as described above, since the diode 30 is designed to have a lower breakdown voltage than the increase-mode HEMT 20, most current may flow through the diode 30. Accordingly, since the semiconductor device may use the high current characteristics of the depletion-mode HEMT 10 having the normally-on structure in the forward operation, the high current and high voltage characteristics of the device may be improved.

Referring to FIG. 2B, a voltage lower than the threshold voltage between the gate electrode G and the source electrode S of the increase-mode HEMT 20 may be applied to the gate electrode G. Referring to FIG. The voltage of the drain electrode D of the depletion-mode HEMT 10 may be relatively low, and the voltage of the source electrode S of the increase-mode HEMT 20 may be relatively high. Accordingly, the increase-mode HEMT may be in an 'off' state and may be driven in the forward direction of the diode 30 '. Accordingly, in the semiconductor device, a current may flow through the diode 30 and the depletion-mode HEMT 10 in a reverse operation.

Hereinafter, a semiconductor device implementing the circuit diagram described with reference to FIGS. 1, 2A, and 2B will be described in detail. In this case, overlapping contents of the above-described semiconductor device may be omitted or simplified.

3 is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line II ′ of FIG. 3. 3 and 4 illustrate an example of a semiconductor device implementing the circuit diagram described with reference to FIGS. 1, 2A, and 2B.

3 and 4, a semiconductor device 100 according to an embodiment of the present invention may include a base substrate 110, a semiconductor layer 120, an insulation pattern 130, a source / drain and a cathode electrode pattern 140. And the gate and anode electrode patterns 150.

The base substrate 110 may be a single plate for forming a semiconductor device having a high electron mobility transistor (HEMT) structure. For example, the base substrate 110 may be at least one of a silicon substrate, a silicon carbide substrate, and a sapphire substrate. The base substrate 110 may include a first region A, a second region B, and a third region C. FIG. The first area A is an area where the depletion-mode HEMT 10 shown in FIG. 1 is implemented, and the second area B is an area where the incremental-mode HEMT 20 shown in FIG. 1 is implemented. Can be. The third region C may be a region in which the diode 30 shown in FIG. 1 is implemented. The semiconductor device 100 may include a depletion-mode HEMT structure disposed on the first region A, an increase-mode HEMT structure connected in series with the depletion-mode HEMT on the second region B, and the third region. A diode structure in parallel with the incremental-mode HEMT may be provided on region C.

The semiconductor layer 120 may be disposed on the base substrate 110. The semiconductor layer 120 may include a lower layer 122 and an upper layer 124 sequentially stacked on the base substrate 110. The upper layer 124 may be formed of a material having a wider energy band gap than the lower layer 122. In addition, the upper layer 124 may be formed of a material having a different lattice constant than the lower layer 122. For example, the lower layer 122 and the upper layer 124 may be a film including a III-nitride-based material. More specifically, the lower layer 122 and the upper layer 124 may be formed of any one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and indium aluminum gallium nitride (InAlGaN). . For example, the lower layer 122 may be a gallium nitride layer (GaN), and the upper layer 124 may be an aluminum gallium nitride layer (AlGaN). Here, at least the lower layer 122 of the semiconductor layer 120 may be formed of high resistivity or P-type gallium nitride (GaN), thereby reducing leakage current of the semiconductor device 100. have.

The upper layer 124 may include a first semiconductor pattern 125, a second semiconductor pattern 126, and a third semiconductor pattern 127. The first semiconductor pattern 125 may be provided in a plate shape on the first region A. FIG. The second semiconductor pattern 126 may be formed in two plate shapes spaced apart from each other on the second region (B). In addition, the third semiconductor pattern 127 may be provided in a plate shape on the third region (C). In the semiconductor layer 120, a two-dimensional electron gas (2DEG) may be generated at an interface between the lower layer 122 and the upper layer 124. The flow of current during the operation of the semiconductor device 100 may be made through the two-dimensional electron gas (2DEG).

The insulating pattern 130 may be formed on the semiconductor layer 120. The insulation pattern 130 may include the first insulation pattern 132, the second insulation pattern 134, and the third insulation pattern 136. The first insulating pattern 132 may have first and second lines 132a and 132b formed to be elongated at a predetermined interval from each other. In this case, as shown in FIG. 3, the first and second lines 132a and 132b may have a curved shape two or more times on the upper layer 124 of the semiconductor layer 120. The second insulating pattern 134 may cover the second semiconductor pattern 126 on the second region (B). In addition, the second insulating pattern 134 may cover the lower layer 122 exposed in the space between two plates of the second semiconductor pattern 126. Accordingly, the second insulating pattern 134 may have a portion in contact with the upper surface of the second semiconductor pattern 126 and a portion in contact with the lower layer 122. The third insulating pattern 136 may be formed on the third region (C). The third insulating pattern 136 may be formed to cover the third semiconductor pattern 127. In addition, an opening 136a exposing the third semiconductor pattern 127 may be provided in the third insulating pattern 136. Here, the insulating pattern 130 may further include a fourth insulating pattern 138 disposed on the lower layer 122 exposed between the first region A and the second region B. FIG. have. The fourth insulating pattern 138 may be interposed between the first semiconductor pattern 125 and the second semiconductor pattern 126. The insulating pattern 130 may be formed of a silicon oxide layer SiO ₂ . Alternatively, the insulating pattern 130 may be made of silicon nitride (SiN) or silicon oxynitride (SiON).

The source / drain and cathode electrode patterns 140 may include a first metal pattern 142 formed over the first to third regions A, B, and C, and the first region in the first region A. A second metal pattern 144 spaced apart from the metal pattern 142 and a third metal pattern 146 spaced apart from the first metal pattern 142 in the second region B may be included. The first metal pattern 142 may be formed of first to third portions 142a, 142b, and 142c. The first portion 142a may be provided to cover a portion of one side of the semiconductor layer 120 and the first insulating pattern 132 in the first region A. FIG. The second portion 142b may be provided to cover the lower layer 122 exposed between the first semiconductor pattern 125 and the second semiconductor pattern 126 in the second region B. Referring to FIG. Accordingly, the second portion 142b may cover the fourth insulating pattern 138. The third portion 142c may be formed to cover the third semiconductor pattern 127 and the third insulating pattern 136 in the third region C. FIG.

The second metal pattern 144 may be spaced apart from the first portion 142a by a predetermined interval and may cover a portion of the other side of the semiconductor layer 120 and the first insulating pattern 132. Here, the space between the first and second lines 132a and 132b may be exposed between the second metal pattern 144 and the first portion 142a. Accordingly, the first portion 142a of the first metal pattern 142 and the second metal pattern 144 may be provided to form a shape in which each other is spaced apart from each other by a predetermined interval. In addition, the third metal pattern 146 may be disposed between the second portion 142b and the third portion 142c on the second region B.

Meanwhile, the first portion 142a may be used as a source electrode of the depletion-mode HEMT structure, and the second metal pattern 144 may be used as a drain electrode of the depletion-mode HEMT structure. In addition, the second portion 142b may be used as a source electrode of the depletion-mode HEMT structure and may also be used as a drain electrode of the increase-mode HEMT structure. The source electrode of the depletion-mode HEMT structure and the drain electrode of the incremental-mode HEMT structure are shared by the second portion 142b such that the depletion-mode HEMT structure and the incremental-mode HEMT structure are electrically series. Can be connected. In addition, the third portion 142c may be used as a cathode of the semiconductor device 100. On the other hand, as described above, since the first metal pattern 142 and the second metal pattern 144 of the first metal pattern 142 and the second metal pattern 144 is formed in the shape intersect with each other to increase the area between them, the first An amount of current between the first metal pattern 142 and the second metal pattern 144 may be increased. In this case, an amount of current between the source electrode and the drain electrode of the depletion-mode HEMT structure may increase during operation of the semiconductor device 100.

The gate and anode electrode patterns 150 may include a third metal pattern 152 and a fourth metal pattern 154. The third metal pattern 152 may include a first portion 152a used as a gate electrode of the depletion-mode HEMT structure, a second portion 152b used as an anode electrode of the semiconductor device 100, and It may be composed of a portion connecting the first portion 152a and the second portion 152b.

The fourth metal pattern 154 may be formed to cover the second insulating pattern 134 in the second region (B). Accordingly, the fourth metal pattern 154 may form a schottky contact with the second insulating pattern 134. In addition, the fourth metal pattern 154 may extend to be adjacent to the second portion 142b used as the source electrode of the depletion-mode HEMT structure and the drain electrode of the increase-mode HEMT structure. Accordingly, the fourth metal pattern 154 is used as a gate electrode of the incremental-mode HEMT structure, and at the same time, a field plate dispersing an electric field concentrated in the gate electrode and the second portion 142b. plate).

The semiconductor layer 120, the insulating pattern 130, the source / drain and cathode electrode patterns 140, and the gate and anode electrode patterns 150 having the above structure are formed on the base substrate 110. The depletion-mode HEMT structure, the incremental-mode HEMT structure, and the diode structure may be implemented. The depletion-mode HEMT structure may be implemented in the first region A, and the incremental-mode HEMT structure may be implemented to be connected in series with the depletion-mode HEMT structure in the second region B. In addition, the diode structure may be implemented to be connected in parallel to the increase-mode HEMT structure in the third region (C).

As described above, the semiconductor device 100 according to the present invention includes a depletion mode HEMT structure having a normallyal structure formed on a single base substrate 110, an increase mode HEMT structure having a normally off structure, and a forward current amount. It has a diode structure to increase the. Accordingly, the semiconductor device 100 according to the present invention has both the high current density and breakdown voltage characteristics of the depletion mode HEMT structure and the normally off characteristic of the increase mode HEMT structure, and the amount of current increases in the forward operation, thereby increasing the high current and the high voltage. Characteristics are improved.

In addition, in the semiconductor device 100 according to the present invention, an insulating pattern 130 is interposed between the upper layer 124, which is a relatively low resistance layer of the semiconductor layer 120, and the gate electrode (that is, the fourth metal pattern 154). As a result, when no voltage is applied to the gate electrode, even when voltage is applied to the source electrode and the drain structure, the gate electrode may be normally off without current flow. Accordingly, the present invention can provide a semiconductor device having a high electron mobility transistor (HEMT) structure capable of an enhancement mode operation.

Subsequently, a manufacturing process of the semiconductor device 100 according to the embodiment of the present invention will be described in detail. In this case, overlapping contents of the semiconductor device 100 described above may be omitted or simplified.

5A, 6A, 7A, and 8A are plan views illustrating a manufacturing process of a semiconductor device according to an exemplary embodiment of the present invention, and FIGS. 5B, 6B, 7B, and 8B are sequentially shown in FIGS. 5A, 6, and 8B. 7A and 8A are cross-sectional views taken along the line II 'of FIG.

5A and 5B, the base substrate 110 may be prepared. For example, preparing the semiconductor substrate 110 may include preparing at least one of a silicon substrate, a silicon carbide substrate, and a sapphire substrate.

The semiconductor layer 120 may be formed on the base substrate 110. For example, a lower layer 122 may be formed on the base substrate 110. The forming of the lower layer 122 may be performed by performing an epitaxial growth process using the base substrate 110 as a seed layer. The lower layer 122 may be formed of a gallium nitride layer (HaN). An upper layer 124 may be formed on the lower layer 122. As an example, the upper layer 124 may be formed by performing an epitaxial growth process using the lower layer 122 as a seed layer. As another example, the forming of the upper layer 124 may be performed by forming a predetermined semiconductor layer conformally covering the lower layer 122 and then patterning the insulating layer. The upper layer 124 may be formed of an aluminum gallium nitride layer (AlGaN). Through the above-described process, the first semiconductor pattern 125 is formed on the first region A of the base substrate 110, and the second semiconductor pattern () is formed on the second region B of the base substrate 110. 126 may be formed, and a third semiconductor pattern 127 may be formed on the third region C of the base substrate 110. The first to third semiconductor patterns 125, 126, and 127 may be simultaneously formed in-situ.

6A and 6B, an insulating pattern 130 may be formed on the semiconductor layer 120. The forming of the insulating pattern 130 may include forming an insulating film that conformally covers the resultant on which the semiconductor layer 120 is formed, and selectively etching the insulating film. Accordingly, the first to fourth insulating patterns 132, 134, 136, and 138 described above with reference to FIGS. 3 and 4 on the first to third regions A, B, and C of the base substrate 110. ) May be formed at the same time.

7A and 7B, source / drain and cathode electrode patterns 140 may be formed. For example, the forming of the source / drain and cathode electrode patterns 140 may include forming a first metal film conformally covering a resultant product on which the insulating pattern 130 is formed, and selectively removing the first metal film. It may include the step of performing an etching process. In the performing of the first etching process, a photoresist etching process may be used. Accordingly, the first to third metal patterns 142, 144, and 146 described above with reference to FIGS. 3 and 4 may be simultaneously formed on the base substrate 110. Here, the first portion 142a of the first metal pattern 142 formed in the first region A may be used as a source electrode of the depletion-mode HEMT. The second portion 142b of the first metal pattern 142 formed in the second region B may be used as a drain electrode of the increase-mode HEMT structure. The third portion 142c of the first metal pattern 142 formed in the third region C may be used as a cathode of the semiconductor device. Since the source electrode of the depletion-mode HEMT and the drain electrode of the increase-mode HEMT are shared with each other, the depletion-mode HEMT and the increase-mode HEMT may be connected in series with each other. In addition, the cathode of the semiconductor device may be bonded to the upper layer 124 of the third region C to form a Schottky diode structure. The source / drain and cathode electrode patterns 140 may include gold (Au), nickel (Ni), platinum (Pt), titanium (Ti), aluminum (Al), palladium (Pd), iridium (Ir), It may be formed of at least one metal of metal elements made from rhodium (Rh), cobalt (Co), tungsten (W), molybdenum (Mo), tantalum (Ta), copper (Cu), and zinc (Zn). have.

8A and 8B, gate and anode electrode patterns 150 may be formed. For example, the forming of the gate and anode electrode patterns 150 may include forming a second metal film different from the first metal film and conformally covering the resultant product on which the insulating pattern 130 is formed, and forming the second metal film. And optionally etching. Accordingly, the third metal pattern 152 and the fourth metal pattern 154 may be simultaneously formed on the base substrate 110. The third metal pattern 152 may include a first portion 152a used as a gate electrode of a depletion-mode HEMT, a second portion 152b used as an anode electrode of a semiconductor device, and a portion connecting them. . The fourth metal pattern 154 may be used as a gate electrode of the increase-mode HEMT. Since the second metal pattern 152 and the fourth metal pattern 154 are simultaneously formed by patterning one second metal layer, the gate electrode of the depletion-mode HEMT, the gate electrode of the increase-mode HEMT, and the semiconductor device are formed. The anode electrode of can be formed in-situ (in-situ) at the same time. The gate and anode electrode patterns 150 may be formed of a metal material different from the source / drain and cathode electrode patterns 140. For example, the gate and anode electrode patterns 150 may include gold (Au), nickel (Ni), platinum (Pt), titanium (Ti), aluminum (Al), palladium (Pd), iridium (Ir), and rhodium (Rh). ), Cobalt (Co), tungsten (W), molybdenum (Mo), tantalum (Ta), copper (Cu), and zinc (Zn) is formed of at least one metal of at least one metal element, the source The drain and cathode electrode patterns 140 may be formed of a different metal material.

The semiconductor device manufacturing method according to the embodiment of the present invention described above is a single semiconductor device having the depletion-mode HEMT 10, the increase-mode HEMT 20, and the diode 30 of the circuit diagram shown in FIG. 1. It may be manufactured on the base substrate 110. Accordingly, the method of manufacturing a semiconductor device according to an embodiment of the present invention includes the semiconductor device 100 that exhibits high voltage and high current characteristics of a device having a normally-on structure and high breakdown voltage characteristics of a device having a normally-off structure. Can be prepared.

In addition, in the method of manufacturing the semiconductor device 100 according to an embodiment of the present invention, the step of forming the diode structure may be completed in the process of manufacturing the depletion-mode HEMT structure and the increase-mode HEMT structure. Accordingly, in the method of manufacturing the semiconductor device 100 according to the embodiment of the present invention, the depletion-mode HEMT 10, the increase-mode HEMT 20, and the diode 30 may be a single base substrate 110. It is possible to simplify the manufacturing process of the semiconductor device 100 implemented on the).

Subsequently, one modification of the semiconductor device according to the exemplary embodiment of the present invention will be described in detail. In this case, overlapping descriptions of the above-described semiconductor device may be omitted or simplified.

FIG. 9 is a diagram illustrating a modified example of the semiconductor device according to example embodiments, and FIG. 10 is a cross-sectional view taken along line II-II ′ of FIG. 9.

9 and 10, the semiconductor device 102 may include a base substrate 110, a semiconductor layer 120, an insulation pattern 130, a source / drain and cathode electrode pattern 141, and a gate and anode electrode pattern ( 151). The base substrate 110, the semiconductor layer 120, and the insulating pattern 130 may be substantially the same as or similar to those of the semiconductor device 100 described with reference to FIGS. 3 and 4. Omit.

The source / drain and cathode electrode patterns 141 and the gate and anode electrode patterns 151 may be simultaneously formed by patterning the same metal layer. Accordingly, the source / drain and cathode electrode patterns 141 and the gate and anode electrode patterns 151 may be made of the same metal material. The source / drain and cathode electrode patterns 141 and the gate and anode electrode patterns 151 may include gold (Au), nickel (Ni), platinum (Pt), titanium (Ti), aluminum (Al), and palladium (Pd). ), At least any of metal elements consisting of iridium (Ir), rhodium (Rh), cobalt (Co), tungsten (W), molybdenum (Mo), tantalum (Ta), copper (Cu), and zinc (Zn) It may be formed of one metal.

The semiconductor device 102 having the structure as described above has the source / drain and cathode electrode patterns 141 and the gate and anode electrode patterns 151 compared to the semiconductor device 100 according to the exemplary embodiment described above. It may have a structure made of the same metal material. In this case, the source / drain and cathode electrode patterns 141 and the gate and anode electrode patterns 151 may be simultaneously formed in-situ during the manufacturing process of the semiconductor device 102. The manufacturing process of the semiconductor device can be simplified.

Hereinafter, a semiconductor device according to another exemplary embodiment of the present invention will be described in detail. In this case, overlapping contents of the semiconductor device according to the exemplary embodiment described above may be omitted or simplified.

FIG. 11 is a circuit diagram illustrating a semiconductor device according to another embodiment of the present invention. FIG. 12A is a diagram illustrating a current flow in a forward operation of a semiconductor device according to another embodiment of the present invention, and FIG. 12B illustrates another embodiment of the present invention. FIG. Is a view showing a current flow in a reverse operation of a semiconductor device according to an example.

11 is a circuit diagram illustrating a semiconductor device according to another embodiment of the present invention. Referring to FIG. 11, a semiconductor device according to another embodiment of the present invention may include a transistor structure for performing both depletion-mode and enhancement-mode operations, and a plurality of diodes. have. As an example, the semiconductor device may include a depletion-mode HEMT 10, an increase-mode HEMT 20, and first and second diodes 30 and 40. The depletion-mode HEMT 10, the increase-mode HEMT 20, and the first diode 30 may include the depletion-mode HEMT 10, the increase-mode HEMT 20, described above with reference to FIG. 1. And may be substantially the same as or similar to the diode 30, a detailed description thereof will be omitted.

The second diode 40 may be electrically connected to the depletion-mode HEMT 10 and the incremental-mode HEMT 20. For example, one end of the second diode 40 is connected to the drain electrode end of the depletion-mode HEMT 10, and the other end of the second diode 40 is the source electrode end of the increase-mode HEMT 10. Can be connected to. The second diode 40 may be electrically connected to the depletion-mode HEMT 10 and the increase-mode HEMT 20 in parallel. The second diode 40 together with the first diode 30 may provide a current movement path in a reverse direction of the semiconductor device. The second diode 40 may be designed to have a lower breakdown voltage than the increase-mode HEMT 20.

The above-described designed semiconductor device includes a depletion-mode HEMT 10 having a normally on structure and an increase-mode HEMT 20 having a normally off structure, and a first current increasing an amount of forward current. The diode 30 and the second diode 40 for increasing the reverse current amount may be provided. Accordingly, the semiconductor device has both high current density and breakdown voltage characteristics of the depletion-mode HEMT 10 and normally off characteristics of the increase-mode HEMT 20, and the first diode 30 in a forward operation. ), And the amount of current increases by the second diode 40 in the reverse operation, thereby improving high current and high voltage characteristics.

Referring to FIG. 12A, a semiconductor device according to another embodiment of the present invention has a larger voltage than the threshold voltage between the gate electrode G and the source electrode S of the increase-mode HEMT 20. When applied to, the incremental-mode HEMT 20 may be 'on'. In this case, the gate / source voltage of the depletion-mode HEMT 10 may be adjusted to approach zero. Accordingly, both the depletion-mode HEMT 10 and the increase-mode HEMT 20 may be turned on. Here, as described above, since the first diode 30 is designed to have a lower breakdown voltage than the increase-mode HEMt 20, most current may flow through the first diode 30. Accordingly, since the semiconductor device may use the high current characteristics of the depletion-mode HEMT 10 having the normally-on structure in the forward operation, the high current and high voltage characteristics of the device may be improved.

12B, a semiconductor device according to another embodiment of the present invention has a voltage lower than that of the threshold voltage between the gate electrode G and the source electrode S of the increase-mode HEMT 20. When applied to, the voltage of the drain electrode D of the depletion-mode HEMT 10 may be lowered, and the voltage of the source electrode S of the increase-mode HEMT 20 may be higher. Accordingly, the increase-mode HEMT 20 is in an 'off' state, and the first and second diodes 30 and 40 are driven in the forward direction, so that the source electrode S of the depletion-mode HEMT 10 is driven. ) May flow into the drain electrode D. In this case, since the second diode 40 is provided to have a low breakdown voltage, the semiconductor device may increase the reverse current amount of the semiconductor device by the second diode 40. Accordingly, the semiconductor device may have high current and high voltage operating characteristics.

13 is a plan view illustrating a semiconductor device according to another embodiment of the present invention. 14 is a cross-sectional view taken along line III-III 'of FIG. 13, and FIG. 15 is a cross-sectional view taken along line IV-IV ′ of FIG. 13.

13 to 15, the semiconductor device 200 according to another embodiment of the present invention may include a base substrate 210, a semiconductor layer 220, an insulation pattern 230, a source / drain and a cathode electrode pattern ( 240, the gate and the anode electrode pattern 250 may be included.

The base substrate 210 may be a plate for forming a semiconductor device having a high electron mobility transistor (HEMT) structure. For example, the base substrate 210 may be at least one of a silicon substrate, a silicon carbide substrate, and a sapphire substrate. The base substrate 210 may include a first region A, a second region B, a third region C, and a fourth region D. FIG. The first area A is an area in which the depletion-mode HEMT 10 shown in FIG. 11 is implemented, and the second area B is an area in which the increment-mode HEMT 20 shown in FIG. 11 is implemented. Can be. The third region C may be a region where the first diode 30 shown in FIG. 11 is implemented, and the fourth region D may be an region where the second diode 40 shown in FIG. 11 is implemented. . Accordingly, a depletion-mode HEMT structure is provided on the first region A, an increase-mode HEMT structure connected in series with the depletion-mode HEMT is provided on the second region B, and the third region ( C) may be provided with a first diode structure connected in parallel to the increase-mode HEMT. In addition, a fourth diode structure may be provided on the fourth region D to be connected to the drain electrode end of the depletion-mode HEMT structure and the source electrode end of the increase-mode HEMT structure.

The semiconductor layer 220 may be disposed on the base substrate 210. The semiconductor layer 220 may include a lower layer 222 and an upper layer 224 sequentially stacked on the base substrate 210. The upper layer 224 may be made of a material having a wider energy band gap than the lower layer 222. In addition, the upper layer 224 may be made of a material having a different lattice constant than the lower layer 222. For example, the lower layer 222 may be a gallium nitride layer (GaN), and the upper layer 224 may be an aluminum gallium nitride layer (AlGaN). Here, at least the lower layer 222 of the semiconductor layer 220 may be formed of high resistivity or P-type gallium nitride (GaN) to reduce the leakage current of the semiconductor device 200. have.

The upper layer 224 may include first to fourth semiconductor patterns 225, 226, 227, and 228. The first to third semiconductor patterns 225, 226, and 227 may be substantially the same as or similar to the first to third semiconductor patterns 125, 126, and 127 described above with reference to FIG. 2. Detailed description will be omitted. The fourth semiconductor pattern 228 may be provided in a plate shape on the fourth region D. FIG. Meanwhile, a two-dimensional electron gas (2DEG) may be generated at the interface between the lower layer 222 and the upper layer 224 in the semiconductor layer 220 having the above structure. The flow of current during the operation of the semiconductor device 200 may be made through the two-dimensional electron gas (2DEG).

The insulating pattern 230 may be formed on the semiconductor layer 220. The insulating pattern 230 may include the first to fifth insulating patterns 232, 234, 236, 238, and 239. The first to fourth insulating patterns 232, 234, 236, and 238 may be substantially the same as or similar to the first to fourth insulating patterns 132, 134, 136, and 138 described with reference to FIG. 2. The detailed description thereof will be omitted. The fifth insulating pattern 239 may be formed on the fourth region D to cover the fourth semiconductor pattern 228. The fifth insulating pattern 239 may have an opening 239a exposing a portion of the fourth semiconductor pattern 228. The insulating pattern 230 may be formed of a silicon oxide layer SiO ₂ . Alternatively, the insulating pattern 230 may be made of silicon nitride (SiN) or silicon oxynitride (SiON).

The source / drain and cathode electrode patterns 240a may include a first metal pattern 242 formed over the first to third regions A, B, and C, and the fourth region in the first region A. The second metal pattern 244 may extend to the region D, and the third metal pattern 246 may be spaced apart from the first metal pattern 242 in the second region B. The third metal pattern 246 may be substantially the same as or similar to the third metal pattern 146 described above with reference to FIG. 2.

The first metal pattern 242 may be formed of first to fourth portions 242a, 242b, 242c, and 242d. The first to third portions 242a, 242b, and 242c may be substantially the same as or similar to the first to third portions 142a, 142b, and 142c described with reference to FIG. 2, and a detailed description thereof. Is omitted. The fourth part 242d may extend from the third part 242c toward the fourth area D. The fourth part 242d may be formed to cover one side of the fourth semiconductor pattern 228 and the fifth insulating pattern 239 in the fourth region D. FIG.

One end 244a of the second metal pattern 244 is spaced apart from the first portion 242a, and the first insulating pattern 232 is disposed between the second metal pattern 244 and the first portion 242a. Spaced space between the first and second lines 232a and 232b. Accordingly, the first portion 242a of the first metal pattern 242 and one end 244a of the second metal pattern 244 are spaced apart from each other by a predetermined interval on the first semiconductor pattern 125. Shape can be achieved. In addition, the other end 244b of the second metal pattern 244 may be formed to extend from the first region A to the fourth region D. FIG. The other end 244b of the second metal pattern 244 may be formed to cover the other side of the fourth semiconductor pattern 228 and the fifth insulating pattern 239 in the fourth region (D). In addition, the other end 244b of the second metal pattern 244 may be formed to fill the opening 239a of the fifth insulating pattern 239.

Meanwhile, the first portion 242a may be used as the source electrode of the depletion-mode HEMT structure, and one end 244a of the second metal pattern 244 may be used as the drain electrode of the depletion-mode HEMT structure. In addition, the second portion 242b may be used as a source electrode of the depletion-mode HEMT structure and may be used as a drain electrode of the increase-mode HEMT structure. The source electrode of the depletion-mode HEMT structure and the drain electrode of the incremental-mode HEMT structure are shared by the second portion 242b so that the depletion-mode HEMT structure and the incremental-mode HEMT structure are electrically in series. Can be connected. In addition, the third portion 242c may be used as a cathode of the semiconductor device 200. In addition, one end of the second diode structure is connected to the drain electrode end of the depletion-mode HEMT structure by the other end 244b of the second metal pattern 244, and by the fourth part 242d. The other end of the second diode structure is connected to the first diode structure and the incremental-mode HEMT structure. Accordingly, the second diode structure may be connected in parallel to the depletion-mode HEMT and the incremental-mode HEMT structures.

The gate and anode electrode patterns 250 may include a third metal pattern 252, a fourth metal pattern 254, and a fifth metal pattern 256. The third and fourth metal patterns 252 and 254 may be substantially the same as or similar to the third and fourth metal patterns 152 and 154 described above with reference to FIG. 2, and a detailed description thereof will be omitted. do. The fifth metal pattern 256 may be provided to be bonded to the second metal pattern 244 in the fourth region D. The fourth metal pattern 254 may be used as a gate electrode of the incremental-mode HEMT structure and at the same time as a field plate for dispersing an electric field concentrated in the gate electrode and the second portion 242b. have. In addition, the fifth metal pattern 256 may be used as an electrode (eg, an anode electrode) that draws a voltage for operating the second diode structure.

As described above, the semiconductor device 200 according to another embodiment of the present invention includes a depletion mode HEMT structure having a normallyal structure formed on a single base substrate 210, an incremental mode HEMT structure having a normally off structure, And a first diode structure that increases the amount of forward current and a second diode structure that increases the amount of reverse current. Accordingly, the semiconductor device 200 according to another embodiment of the present invention has both the high current density and breakdown voltage characteristics of the depletion mode HEMT structure and the normally off characteristic of the increase mode HEMT structure, and the amount of current in the forward and reverse operations is increased. Increasingly, high current and high voltage characteristics are improved.

In addition, the semiconductor device 200 according to another exemplary embodiment may include an insulating pattern between the upper layer 224, which is a relatively low resistance layer of the semiconductor layer 220, and the gate electrode (that is, the fourth metal pattern 254). When the voltage is not applied to the gate electrode through 230, the device may be normally off when there is no flow of current even when a voltage is applied to the source electrode and the drain structure. Accordingly, the present invention can provide a semiconductor device having a high electron mobility transistor (HEMT) structure capable of an enhancement mode operation.

Subsequently, a modification of the semiconductor device according to another embodiment of the present invention will be described in detail. In this case, overlapping descriptions of the above-described semiconductor device may be omitted or simplified.

16 is a plan view illustrating a modified example of a semiconductor device according to example embodiments of the inventive concepts. FIG. 17 is a cross-sectional view taken along the line VV ′ of FIG. 16, and FIG. 18 is a cross-sectional view taken along the line VI-VI ′ of FIG. 16.

16 to 18, the semiconductor device 202 may include a base substrate 210, a semiconductor layer 220, an insulation pattern 230, a source / drain and cathode electrode pattern 241, and a gate and anode electrode pattern ( 251). The base substrate 210, the semiconductor layer 220, and the insulating pattern 230 may be generally the same as or similar to the semiconductor device 200 according to another exemplary embodiment of the present invention described with reference to FIGS. 13 to 15. The detailed description thereof may be omitted.

The source / drain and cathode electrode patterns 241 and the gate and anode electrode patterns 251 may be simultaneously formed by patterning the same metal layer. Accordingly, the source / drain and cathode electrode patterns 241 and the gate and anode electrode patterns 251 may be made of the same metal material. The source / drain and cathode electrode patterns 241 and the gate and anode electrode patterns 251 include gold (Au), nickel (Ni), platinum (Pt), titanium (Ti), aluminum (Al), and palladium (Pd). ), At least any of metal elements consisting of iridium (Ir), rhodium (Rh), cobalt (Co), tungsten (W), molybdenum (Mo), tantalum (Ta), copper (Cu), and zinc (Zn) It may be formed of one metal.

The semiconductor device 202 having the above structure has the source / drain and cathode electrode patterns 241 and the gate and anode electrode patterns 251 compared to the semiconductor device 200 according to another embodiment of the present invention described above. It may have a structure made of the same metal material. In this case, the source / drain and cathode electrode patterns 241 and the gate and anode electrode patterns 251 may be simultaneously formed in-situ during the manufacturing process of the semiconductor device 202. The manufacturing process of the semiconductor device can be simplified.

19 illustrates a package module including a semiconductor device to which the technology of the present invention is applied. Referring to FIG. 19, the above-described semiconductor device technology may be applied to the package module 300. For example, the package module 300 may be provided in the same form as the semiconductor device 320 and the quad flat package (QFP) packaged semiconductor device 330. The semiconductor devices 100, 102, 200, and 202 manufactured according to the present invention may be applied to the semiconductor devices 220 and 230 of various other types. The package module 300 may be formed by installing the semiconductor devices 320 and 330 on a separate semiconductor substrate 210. In this case, the semiconductor substrate 310 may include a printed circuit board. As described above, the semiconductor devices 100, 102, 200, and 202 according to the embodiments of the present invention may be packaged to have a structure coupled to the package module 300. Accordingly, the present invention can provide a package module 300 having high current and high voltage characteristics by including semiconductor devices 100, 102, 200, and 202 capable of high current and high voltage operation.

The foregoing detailed description is illustrative of the present invention. It is also to be understood that the foregoing is illustrative and explanatory of preferred embodiments of the invention only, and that the invention may be used in various other combinations, modifications and environments. That is, changes or modifications may be made within the scope of the concept of the invention disclosed in this specification, the scope equivalent to the disclosed contents, and / or the skill or knowledge in the art. The foregoing embodiments are intended to illustrate the best mode contemplated for carrying out the invention and are not intended to limit the scope of the present invention to other modes of operation known in the art for utilizing other inventions such as the present invention, Various changes are possible. Accordingly, the foregoing description of the invention is not intended to limit the invention to the precise embodiments disclosed. In addition, the appended claims should be construed as including steps in other embodiments.

1 is a circuit diagram illustrating a semiconductor device in accordance with an embodiment of the present invention.

2A is a diagram illustrating a current flow in a forward operation of a semiconductor device according to an exemplary embodiment of the present invention.

2B is a view illustrating a current flow in a reverse operation of a semiconductor device according to an exemplary embodiment of the present invention.

3 is a plan view showing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view taken along the line II ′ of FIG. 2.

5A, 6A, 7A, and 8A are plan views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

5B, 6B, 7B, and 8B are cross-sectional views taken along the line II ′ of FIG. 5A, 6, 7A, and 8A, in turn.

9 is a plan view illustrating a modification of the semiconductor device according to the embodiment of the present invention.

FIG. 10 is a cross-sectional view taken along the line II-II 'of FIG. 9.

11 is a circuit diagram illustrating a semiconductor device according to another embodiment of the present invention.

12A is a view illustrating a current flow in a forward operation of a semiconductor device according to another exemplary embodiment of the present invention.

12B is a view illustrating a current flow in a reverse operation of a semiconductor device according to another exemplary embodiment of the present invention.

13 is a plan view illustrating a semiconductor device according to another embodiment of the present invention.

FIG. 14 is a cross-sectional view taken along the line III-III ′ of FIG. 13.

FIG. 15 is a cross-sectional view taken along the line IV-IV 'of FIG. 13.

16 is a plan view illustrating a modified example of a semiconductor device according to example embodiments of the inventive concepts.

FIG. 17 is a cross-sectional view taken along the line VV ′ of FIG. 16.

FIG. 18 is a cross-sectional view taken along the line VI-VI ′ of FIG. 16.

19 illustrates a package module including a semiconductor package to which the technology of the present invention is applied.

Description of the Related Art [0002]

10: depletion-mode HEMT

20: increase-mode HEMT

30: diode

100: semiconductor device

110: base substrate

120: semiconductor layer

130: insulation pattern

140: source / drain and cathode electrode patterns

150: gate and anode electrode pattern

Claims (24)

delete delete delete A base substrate; A depletion-mode High Electron Mobility Transistor (HEMT) structure disposed on the base substrate; An enhancement-mode HEMT structure disposed on the base substrate and connected in series with the depletion-mode HEMT structure; And A first diode structure disposed on the base substrate, the first diode structure being connected in parallel to the incremental-mode HEMT structure, And a second diode structure coupled to the source electrode of the incremental-mode HEMT structure and the drain electrode of the depletion-mode HEMT structure. 5. The method of claim 4, And the second diode structure provides a reverse current flow path with the first diode structure in reverse operation of the semiconductor device. The method according to claim 4 or 5, And the second diode structure has a lower breakdown voltage than the incremental-mode HEMT structure. A base substrate including a first region, a second region, and a third region; A semiconductor layer disposed on the base substrate to generate a 2-Dimensional Electron Gas (2DEG) that provides a current movement path therein; An insulation pattern disposed on the semiconductor layer; Source / drain and cathode electrode patterns formed on the semiconductor layer and the insulating pattern; And A gate and an anode electrode pattern formed on the semiconductor layer and the insulating pattern; The semiconductor layer, the insulating pattern, the source / drain and cathode electrode patterns, and the gate and anode electrode patterns formed on the first region form a depletion-mode HEMT structure, The semiconductor layer, the insulation pattern, the source / drain and cathode electrode patterns, and the gate and anode electrode patterns formed on the second region form an increase-mode HEMT structure connected in series with the depletion-mode HEMT structure, The semiconductor layer, the insulating pattern, the source / drain and cathode electrode patterns, and the gate and anode electrode patterns formed on the third region form a first diode structure connected in parallel to the increase-mode HEMT structure. . The method of claim 7, wherein And the first diode structure has a lower breakdown voltage than the incremental-mode HEMT structure. The method of claim 7, wherein The gate and anode electrode patterns provide a gate electrode of the depletion-mode HEMT structure and an anode electrode connected to the gate electrode, Wherein the source / drain and cathode electrode patterns provide a drain electrode of the depletion-mode HEMT structure, a gate electrode of the incremental-mode HEMT structure, and a cathode electrode provided in the first diode structure. The method of claim 7, wherein And the source electrode of the depletion-mode HEMT structure and the drain electrode of the incremental-mode HEMT structure share the same portions of the source / drain and cathode electrode patterns. The method of claim 7, wherein The semiconductor layer is: A first semiconductor film disposed on the base substrate; And A second semiconductor film disposed on the first semiconductor film, the second semiconductor film having a broader energy band gap than the first semiconductor film and forming a pattern to expose a portion of the first semiconductor film; The insulating pattern formed on the second region is in contact with a portion and a side surface of the second semiconductor film formed on the second region and the upper surface of the first semiconductor film, and the gate electrode pattern formed on the second region. Is formed on a surface of the insulating pattern such that a part of the gate electrode pattern reaches a position lower than an upper surface of the second semiconductor film. A base substrate including a first region, a second region, a third region, and a fourth region; A semiconductor layer disposed on the base substrate to generate a 2-Dimensional Electron Gas (2DEG) that provides a current movement path therein; An insulation pattern disposed on the semiconductor layer; Source / drain and cathode electrode patterns formed on the semiconductor layer and the insulating pattern; And A gate and an anode electrode pattern formed on the semiconductor layer and the insulating pattern; The semiconductor layer, the insulating pattern, the source / drain and cathode electrode patterns, and the gate and anode electrode patterns formed on the first region form a depletion-mode HEMT structure, The semiconductor layer, the insulation pattern, the source / drain and cathode electrode patterns, and the gate and anode electrode patterns formed on the second region form an increase-mode HEMT structure connected in series with the depletion-mode HEMT structure, The semiconductor layer, the insulation pattern, the source / drain and cathode electrode patterns, and the gate and anode electrode patterns formed on the third region form a first diode structure connected in parallel to the incremental-mode HEMT structure, The semiconductor layer, the insulating pattern, the source / drain and cathode electrode patterns, and the gate and anode electrode patterns formed on the fourth region are connected in parallel to the depletion-mode HEMT structure and the incremental-mode HEMT structure. 2 A semiconductor device constituting a diode structure. 13. The method of claim 12, The second diode structure is a semiconductor device that provides reverse current flow from the source electrode of the incremental-mode HEMT structure to the drain electrode of the depletion-mode HEMT structure together with the first diode structure in reverse operation of the semiconductor device. . The method according to any one of claims 7 to 11, The source / drain and cathode electrode patterns formed in the first region may include a first metal pattern and a second metal pattern spaced apart from each other via the gate and anode electrode patterns. 15. The method of claim 14, The gate and anode electrode patterns may include a third metal pattern spaced apart from the first and second metal patterns between the first and second metal patterns in the first region. The first to third metal patterns may be curved in a plurality of times in the first region. The method according to any one of claims 7 to 11, And the source / drain and cathode electrode patterns and the gate and anode electrode patterns are made of the same metal material. Preparing a base substrate having a first region, a second region, and a third region; Forming a semiconductor layer on the base substrate to generate a two-dimensional electron gas (2DEG) therein; Forming an insulating pattern on the semiconductor layer; Forming a source / drain and a cathode electrode pattern on the semiconductor layer and the insulating pattern; And And forming a gate and an anode electrode pattern on the semiconductor layer and the insulating pattern. The first, second and third steps comprise forming a depletion-mode HEMT structure on the first region, an incremental-mode HEMT connected in series with the depletion-mode HEMT structure on the second region. Forming a structure, and forming a first diode structure on the third region, the first diode structure being connected in parallel to the incremental-mode HEMT structure, The semiconductor layer is formed on the first semiconductor film and the first semiconductor film on the base substrate, and has a wider energy band gap than the first semiconductor film to expose a portion of the first semiconductor film. And a second semiconductor film forming a pattern, wherein the insulating pattern formed on the second region is in contact with a portion and a side surface of the second semiconductor film formed on the second region, and an upper surface of the first semiconductor film. And the gate electrode pattern formed on the second region is formed on a surface of the insulating pattern such that a part of the gate electrode pattern reaches a lower position than an upper surface of the second semiconductor film. Preparing a base substrate; Forming a depletion-mode HEMT structure on the base substrate; Forming an incremental-mode HEMT structure in series with the depletion-mode HEMT structure on the base substrate; Forming a first diode structure connected in parallel to said incremental-mode HEMT structure on said base substrate; And Forming a second diode structure on the base substrate, the second diode structure being connected to the source electrode of the incremental-mode HEMT structure and the drain electrode of the depletion-mode HEMT structure. The method of claim 18, And the second diode structure is formed to have a breakdown voltage lower than threshold voltages of the source and drain electrodes of the incremental-mode HEMT structure. The method according to any one of claims 17 to 19, And the first diode structure is formed to have a breakdown voltage lower than the threshold voltages of the source and drain electrodes of the incremental-mode HEMT structure. Preparing a base substrate having a first region, a second region, and a third region; Forming a semiconductor layer on the base substrate to generate a two-dimensional electron gas (2DEG) therein; Forming an insulating pattern on the semiconductor layer; Forming a source / drain and a cathode electrode pattern on the semiconductor layer and the insulating pattern; And And forming a gate and an anode electrode pattern on the semiconductor layer and the insulating pattern. The first, second and third steps comprise forming a depletion-mode HEMT structure on the first region, an incremental-mode HEMT connected in series with the depletion-mode HEMT structure on the second region. Forming a structure, and forming a first diode structure on the third region, the first diode structure being connected in parallel to the incremental-mode HEMT structure. 22. The method of claim 21, The second step is: Forming a first metal film on the semiconductor layer; And Patterning the first metal film; The third step is: Forming a second metal film on the semiconductor layer, the second metal film having a metal different from that of the first metal film; And And patterning the second metal film. 22. The method of claim 21, The second and third steps are: Forming a metal film on the semiconductor layer; And Patterning the metal layer to simultaneously form the source / drain and cathode electrode patterns and the gate and anode electrode patterns. Preparing a base substrate having a first region, a second region, a third region, and a fourth region; Forming a semiconductor layer on the base substrate to generate a two-dimensional electron gas (2DEG) therein; Forming an insulating pattern on the semiconductor layer; Forming a source / drain and a cathode electrode pattern on the semiconductor layer and the insulating pattern; And And forming a gate and an anode electrode pattern on the semiconductor layer and the insulating pattern. The first, second and third steps comprise forming a depletion-mode HEMT structure on the first region, an incremental-mode HEMT connected in series with the depletion-mode HEMT structure on the second region. Forming a structure, forming a first diode structure connected in parallel to said incremental-mode HEMT structure on said third region, and source electrode and depletion of said incremental-mode HEMT structure on said fourth region -Forming a second diode structure connected to the drain electrode of the mode HEMT structure.

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