KR101199625B1 - Apparatus and method of electronic control processing of digital signal in nuclear power plant - Google Patents

Abstract

PURPOSE: An apparatus and method for digital signal electronic control processing of a nuclear power plant are provided to minimize the change of hardware by equally setting an input-output of duplex two FPGAs and an input-output of a card performing a predetermined function. CONSTITUTION: A first FPGA(120) and a second FPGA(150) output a system management signal. Input buffers(110,140) transmit a system state signal generated by the operation of a nuclear plant to one of the first FPGA and the second FPGA. Output buffers(130,160) transmit the system management signal to a device which controls the nuclear plant. The first FPGA transmits a first error detection signal to the second FPGA. The second FPGA transmits a second error detection signal to the first FPGA. The first FPGA determines whether the first error detection signal is identical to the second error detection signal.

Description

Apparatus and method for digital signal electronic control of nuclear power plant {APPARATUS AND METHOD OF ELECTRONIC CONTROL PROCESSING OF DIGITAL SIGNAL IN NUCLEAR POWER PLANT}

The present invention relates to an apparatus and method for digital signal electronic control processing of a nuclear power plant. Instead of a plurality of logic integrated circuits (ICs) used in existing control apparatuses and systems to use a single function, a redundant FPGA ( Field Programmable Gate Array) is a technology that improves the safety of power plant operation by reducing the failure rate that can occur at interfaces such as ports (or pins) of multiple logic ICs or FPGAs.

Nuclear power plants usually consist of more than 100 individual functions.

These are largely divided into nuclear steam supply systems (NSSS) centered on nuclear reactors, turbines / power generating cylinders that supply steam to run generators, and other ancillary equipment.

Looking at pressurized light-type power plants, which currently dominate Korea's nuclear power plants, the primary system centered on nuclear reactors, the secondary system including steam generators, turbines, generators and condensers, engineering safety equipment systems for accidents, transmission and distribution systems, It consists of measurement control system and other auxiliary systems.

Korean standard nuclear power plants, including Yeonggwang 3 and 4, are divided into various systems such as protection systems, monitoring systems, and control systems.

The various systems that make up a nuclear power plant perform selected operations with cards implemented with multiple logic ICs that perform their respective functions.

However, in the event of a problem with each logic IC, the card may not perform the selected operation, but may also affect other cards, control devices or systems due to card malfunction.

In addition, not only malfunction of the card itself, but also malfunction of an input buffer or malfunction occurring at an interface such as a port or a pin of the card is not easy to detect.

In addition, since there is no function to detect the malfunction and cut off the output, there is a possibility that an incorrectly calculated value may be output, which may interfere with the operation of the nuclear power plant.

Such problems may cause serious problems that may paralyze some or all functions of protection, monitoring, and control of nuclear power plants.

The digital signal electronic control apparatus of a nuclear power plant according to an embodiment of the present invention is the first FPGA and the second FPGA for outputting a system management signal, the system status signal generated by the operation of the nuclear power plant, the first FPGA and the first It may include an input buffer for transmitting to at least one of the two FPGA, and an output buffer for receiving the output system management signal and delivers to the device for controlling the nuclear power plant.

The digital signal electronic control method of a nuclear power plant according to an embodiment of the present invention, in the input buffer, transmitting a system status signal generated by the operation of the nuclear power plant to at least one of the first FPGA and the second FPGA, Outputting a system management signal in response to the transmitted system status signal in at least one of a first FPGA and a second FPGA, and receiving an output system management signal from an output buffer and controlling the nuclear power plant; And transmitting a first error detection signal from the first FPGA to the second FPGA, and wherein the second FPGA further sends a second error detection signal to the first FPGA. And at least one of the first error detection signal and the second error detection signal is the input system status signal, checksum, CRC, and parity. It may include at least one of the signals.

According to an embodiment of the present invention, not only a malfunction of the card itself, but also a malfunction of an input buffer or a malfunction of one or more ports or pins of the card can be detected.

In addition, according to one embodiment of the present invention, it can provide a function to detect the malfunction when the output is cut off.

According to one embodiment of the present invention, each logic IC is implemented in two redundant FPGAs, and if a problem occurs in one FPGA, the logic IC may be prepared by processing a predetermined operation in another FPGA. have.

According to one embodiment of the present invention, by setting the input and output of the two redundant FPGA to the same as the input and output of the card that performs the previously selected function, it is possible to minimize the change of hardware to improve the safety of the system.

1 is a view illustrating a digital signal electronic control apparatus of a nuclear power plant according to an embodiment of the present invention.
2 is a view for explaining a digital signal electronic control apparatus of a nuclear power plant according to another embodiment of the present invention.
3 is a view for explaining a digital signal electronic control apparatus of a nuclear power plant according to another embodiment of the present invention.
4 is a view for explaining a digital signal electronic control method of a nuclear power plant according to an embodiment of the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The terminologies used herein are terms used to properly represent preferred embodiments of the present invention, which may vary depending on the user, the intent of the operator, or the practice of the field to which the present invention belongs. Therefore, the definitions of the terms should be made based on the contents throughout the specification. Like reference symbols in the drawings denote like elements.

1 is a diagram illustrating a digital signal electronic control apparatus 100 of a nuclear power plant according to an embodiment of the present invention.

The digital signal electronic control apparatus 100 according to an embodiment of the present invention may improve the stability of the nuclear power plant operation by providing a predetermined function provided by an existing card through two independent FPGAs.

Specifically, the digital signal electronic control apparatus 100 of a nuclear power plant according to an embodiment of the present invention may include a first input buffer 110, a first FPGA 120, a first output buffer 130, and a second input buffer. 140, a second FPGA 150, and a second output buffer 160.

The first input buffer 110 and the second input buffer 120 according to an embodiment of the present invention to transfer the system status signal generated by the operation of the nuclear power plant to at least one of the first FPGA and the second FPGA. Can be.

The first FPGA 120 and the second FPGA 150 according to an embodiment of the present invention may output a system management signal.

The first output buffer 130 and the second output buffer 160 according to an embodiment of the present invention may receive the output system management signal and transmit it to a device for controlling the nuclear power plant.

For example, when the first FPGA 120 operates normally, the first FPGA 120 collects the system status signal and outputs a system management signal according to a program set in advance based on the collected system status signal. can do.

If the first FPGA 120 malfunctions and the second FPGA 140 operates normally, the first FPGA 120 generates a failover signal, and the second FPGA 140 generates the failover signal according to the failover signal. In place of the first FPGA 120, a system management signal may be output according to a preset program based on the collected system status signal.

In this case, since the first FPGA 120 may verify the overall abnormal operation or the clock signal, the first FPGA 120 may detect a malfunction of the input buffer or a malfunction of one or more ports or pins of the corresponding FPGA. .

In detail, the first FPGA 120 may transmit a first error detection signal to the second FPGA 140, and the second FPGA 140 may transmit a second error detection signal to the first FPGA 120.

At least one of the first error detection signal and the second error detection signal according to an embodiment of the present invention may include at least one of the input system status signal, checksum, CRC, and parity signal.

The first FPGA 120 according to an embodiment of the present invention determines whether the second error detection signal received from the second FPGA 140 is the same as the first error detection signal, and if the determination result is the same, An output signal may be generated and transmitted to the output buffer according to the operation condition.

The second FPGA 140 according to an embodiment of the present invention determines whether the first error detection signal received from the first FPGA 120 is the same as the second error detection signal, and if the determination result is the same, An output signal may be generated and transmitted to the output buffer according to the operation condition.

The predetermined operation condition of the FPGA may vary depending on which system the digital signal electronic control apparatus 100 is applied to.

For example, when a redundant FPGA is applied to a core protection operator system, the FPGAs 120 and 140 may receive core state information as the system state signal.

In addition, the FPGAs 120 and 140 may receive the received state information of the core, calculate a stability and operation margin of the core, and output a system management signal for appropriately managing the core.

A more detailed description of the selected function of the FPGA will be described later with reference to FIGS. 4 and 5.

The second FPGA 140 may operate independently of the operation of the first FPGA 120 and may monitor whether the first FPGA 120 itself, the ports, the pins, and the like operate normally.

That is, the second FPGA 140 may monitor the state of the first FPGA 120 and determine a case in which the first FPGA 120 operates abnormally.

Similarly, the first FPGA 120 may also monitor whether the second FPGA 140 itself, the ports, the pins, and the like operate normally.

The first FPGA 120 and the second FPGA 140 according to an embodiment of the present invention may perform output signal switching by using a failover signal.

An input buffer according to an embodiment of the present invention may be allocated to at least one of the first FPGA 120 and the second FPGA 140 by distributing a plurality of system state signals.

An embodiment of distributing a plurality of system status signals in an input buffer will be described in detail with reference to FIGS. 2 and 3.

2 is a view for explaining a digital signal electronic control apparatus 200 of a nuclear power plant according to another embodiment of the present invention.

The digital signal electronic control apparatus 200 of a nuclear power plant according to another embodiment of the present invention may control input / output of the FPGAs 220 and 230 through the first input buffer 210 and the first output buffer 230. Can be.

In addition, the digital signal electronic control apparatus 200 of the nuclear power plant according to another embodiment of the present invention input and output the FPGAs 220, 230 through the second input buffer 240 and the second output buffer 260. Can be controlled.

The first input buffer 210 and the second input buffer 240 according to another embodiment of the present invention may distribute two input signals, respectively, and transmit them to the FPGAs 220 and 230.

Accordingly, at least one of the first FPGA 220 and the second FPGA 250 compares the plurality of distributed system state signals input to a plurality of different ports, and the distributed plurality of system state signals are all the same. Can be determined.

For example, in the first FPGA 220, the first system status signal transmitted from the first input buffer 210 and the second system status signal distributed and transmitted from the second input buffer 220 are provided with the first system status signal. It can be delivered through a different port or pin.

Accordingly, the first FPGA 220 may determine whether the first system state signal and the second system state signal are the same.

If the first system state signal and the second system state signal are not the same, the first FPGA 220 determines that there is a problem with a port or pin, generates a failover signal, and generates a failover signal through the second FPGA 240. It can be controlled to perform the operation instead.

That is, at least one of the first FPGA 220 and the second FPGA 220 may generate and output a failover signal when the plurality of distributed system state signals are not the same.

That is, each FPGA compares two or more identical signals input through different ports (or pins) to see if they have different values, and when two input signals check different values, it sends a failover signal to another FPGA or output buffer. It does not send its output signal.

If three or more input signals use signals having a plurality of identical values. That is, if two or more identical signals of each FPGA have the same value, the entire input signal or checksum, CRC, and parity signals can be sent to another FPGA and compared.

If the input signal values, or checksum, CRC, and parity signals are the same, the output signal of the master FPGA (the first FPGA or the second FPGA) may be exported.

3 is a view for explaining a digital signal electronic control apparatus 300 of a nuclear power plant according to another embodiment of the present invention.

Each digital signal electronic control apparatus 300 described in FIG. 3 may include one input buffer 310, one FPGA 320, and one output buffer 330.

The input buffer 310 may branch and output the input signal into a plurality of system status signals.

Accordingly, the output plurality of system state signals may be input through a plurality of ports or pins of the FPGA 320.

Thus, the FPGA 320 according to an embodiment of the present invention can determine whether all of the plurality of system status signals inputted to the different ports or pins are the same.

If the input buffer 310 branches and outputs the input signal into four system status signals, and inputs it through four ports or pins of the FPGA 320, the FPGA 320 inputs the four input signals. It can be determined whether the system status signals are all the same.

If only a system status signal input to a specific port (or pin) is different from the remaining three system status signals, the FPGA 320 according to an embodiment of the present invention determines that the port (or pin) is broken. can do.

For example, when there are a plurality of system status signals indicating different values, it may be determined that the same plurality of system status signals are normal.

For example, if the input signals are divided into six, four of the system status signals are identical to the FPGA 320, and two are different, the four system status signals may be determined to be normal.

The digital signal electronic control apparatus according to an embodiment of the present invention can be applied to a system classified into various systems.

For example, the digital signal electronic control apparatus according to an embodiment of the present invention may be applied to a protection system or a monitoring system. Specific examples will be described with reference to FIGS. 4 and 5.

The digital signal electronic control apparatus according to an embodiment of the present invention may include a sensing unit, FPGAs for processing respective functions, and a system control unit.

The sensing unit may sense a system status signal generated according to the operation of the nuclear power plant, and the system controller may control the operation of the nuclear power plant in response to the output system management signal.

A system management signal may be output between the sensing unit and the system control unit by receiving a system state signal through FPGAs having two FPGAs in pairs.

The sensing unit according to an embodiment of the present invention may include a main processor and an input / output bus converter.

The main processor controls all the processors according to the input signal, and the input / output bus converter may distribute the input signals to a plurality of the plurality of FPGAs and transmit the duplicated signals to each of the FPGAs or at least two or more FPGAs.

Thus, the FPGA, which receives a plurality of input signals through different ports or pins, may determine whether all input signals are the same.

If they are not the same, they can recognize a problem with the port or pin and output a failover signal to delegate the operation to another FPGA.

For example, the digital signal electronic control apparatus according to an embodiment of the present invention may be applied to a core protection calculator system (CPCS).

The core protection operator system sends a + 5V to + 10V control rod position signal to the core protection calculator and the control rod assembly calculator to calculate the core stability and operating margin according to the control rod position. It is responsible for sending each signal.

The control rod position signal may be transmitted to a card of the core protection operator system, and the same control rod position signal may be transmitted to an impedance matching card of the control rod assembly position light shield assembly without a separate isolation device to process the selected control operation. .

The digital signal electronic control apparatus according to an embodiment of the present invention may be applied to replace the card functions of the core protection operator system.

Each card providing the input / output function of the core protection operator system can control the input / output signal through a set of a plurality of logic gates. Therefore, when a problem occurs in one logic gate inside the card during operation of the nuclear power plant, a serious problem may be caused that the operation of the nuclear power plant as well as the card is stopped.

To address this, each card can be replaced with FPGAs each containing two redundant FGPAs.

For example, FPGAs may include a pair of FPGAs to perform the function of such core protection operators.

 In other words, paired FPGAs can take the role of a card to perform the functions of the core protection operator.

For example, FPGAs may include analog to digital converter (ADC) cards, digital input (DI) cards, digital output (DO) cards, RO cards, FI cards, watch dog timer (WDT) cards, and digital analog loop-back (DALCAL). Each card can provide each function.

For example, FPGAs, each including a first FPGA and a second FPGA, receive the sensed system status signals to manage at least one of nuclear boiling deviation margin, local power density margin, and neutron flux output. Can output a signal.

In addition, the FPGAs including the first FPGA and the second FPGA, respectively, receive the sensed system status signal to receive any one of a core protection calculator (CPC) and a control element assembly calculator (CEAC). Output the system management signal for selecting a signal; output the system management signal for indicating a current state of the core on an external display device by receiving the sensed system state signal; Receiving the status signal and outputting the system management signal for managing at least one of a low nuclear bounce rate stop / prepare signal, a high local output stop / prepare signal, a sensor fault signal, and a control rod withdraw prohibition signal, The system tube for receiving a sensed system status signal to measure the speed of the reactor coolant pump May output a signal.

In addition, FPGAs each including a first FPGA and a second FPGA may output the system management signal that receives the sensed system status signal and periodically generates a watchdog timer signal. The system management signal may be outputted by receiving the sensed system status signal and generating a digital / analog loop back signal.

The sensed system state signal may be divided into a plurality and may be delivered to the first FPGA and the second FPGA, respectively. Accordingly, each of the first FPGA and the second FPGA may determine whether the plurality of input system state signals are the same and determine that the first FPGA and the second FPGA operate normally only when they are the same.

If they are not the same, they can recognize a problem with the port or pin and output a failover signal to delegate the operation to another FPGA.

For example, when the first FPGA is the master FPGA and the plurality of input signals are not the same, a failover signal may be generated to control the second FPGA to take over the operation.

Specifically, FPGAs including the first FPGA and the second FPGA may replace the functions of the ADC card.

That is, as one of FIGS. 1 to 3, an analog input may be received, digitally converted through one of the first FPGA and the second FPGA, and then output in a digital form.

At this time, the information for changing the analog input into a digital output may be classified into the temperature of the primary low temperature tube of the steam generator, the coolant temperature of the high temperature tube, the subscriber pressure, the neutron flux detector signal, and the location of the target control rod.

Similarly, any one of two FPGAs including two FPGAs may input and output signals such as CPC / CEAC selection instead of a digital input (DI) card.

In addition, any one of two FPGAs including two FPGAs may output an external display signal as the system management signal in place of a digital output (DO) card, and a low nuclear boiling rate (preliminary) in place of an RO card. Can output a stop signal, generate periodic signals when the system is running on behalf of the WDT (Watch Dog Timer) card, and check the internal operation of FPGAs on behalf of the Digital Analog Loop-Back (DALCAL) card It can output a signal for.

In addition, any one of the FPGAs each including two FPGAs may output a system management signal for measuring the pump speed of the reactor coolant in place of the FI card.

Existing cards have a possibility that the whole function of the card can be stopped when the logic IC constituting the inside malfunctions. Even if it malfunctions, the function can be performed through another FPGA.

As another example, the digital signal electronic control apparatus according to an embodiment of the present invention may be applied to a plant monitoring system (PMS).

That is, the system status signal is a signal input to the power plant monitoring system of the nuclear power plant, the system management signal is a plant information collection, power plant information indication, power plant information recording, alarm generation, providing various information, nuclear reactor core and primary and secondary It may be interpreted as a signal for managing at least one of the side performance evaluation means.

The plant monitoring system can collect, direct, and record the information of the nuclear power plant, generate alarms, and provide various information for the nuclear plant to operate within the limits of the technical guidelines. In addition, the plant monitoring system may provide means for reactor core and half-side performance evaluation.

To this end, the power plant monitoring system may include a safety system of the PDAS (Plant Data Acquisition) A-D, a PDAS N1-N3 as a non-safety system, and a plant monitoring computer system (PMCS) for each cabinet.

The components of the plant monitoring system can provide the functions as described above through each card, such as the core protection operator system, where each FPGA comprising two FPGAs replaces each card and replaces the nuclear power plant. It can improve the safety of the operation.

The digital signal electronic control device according to an embodiment is an input / output for controlling the input and output of the main processor and the sensed system status signal sensing unit for sensing the system status signal, to be applied to the core protection operator system and the power plant monitoring system It may include a bus converter.

FIG. Is a diagram illustrating a system to which a digital signal electronic control apparatus according to another embodiment is applied.

The system to which the digital signal electronic control apparatus according to another embodiment of the present invention is applied may be applied to a plant protection system (PPS).

That is, the signal is input to the power plant protection system of the nuclear power plant, the system management signal is a nuclear reactor stop signal, safety injection signal, nuclear reactor building isolation signal, nuclear reactor building water spray signal, recirculation operation signal, main steam isolation signal, auxiliary water supply operation Signal, fuel building emergency exhaust operation signal, reactor building exhaust isolation operation signal, and main control room emergency ventilation operation signal.

The power plant protection system of the nuclear power plant, the reactor protection system (RPS) associated with the shutdown of the reactor, the DPS (Diverse Protection System) to strengthen the protection of the nuclear power plant in parallel with the PPS, and to maintain the design criteria accident results within the allowable value It may include an Engineered Safety Features Actuation System (ESFAS).

RPS and ESFAS can include several blocks, which can be implemented as cards. Each card can provide functions to shut down the reactor, protect the power plant, and maintain accident results.

In place of each of these cards, a redundant first FPGA and a second FPGA may be applied.

That is, the first FPGA and the second FPGA are programmed to perform a function of a specific card, and when any one of the first FPGA and the second FPGA abnormally operates, the other may perform the function. .

Therefore, RPS and ESFAS using the first FPGA and the second FPGA in place of the card can improve the stability of operation.

Specifically, the first FPGA and the second FPGA determine whether 'BISTABLES COMPARATORS' comparing the input analog signal with a preset fixed / variable set value, and whether the analog signal input from the 'BISTABLES COMPARATORS' reaches the preset value. 'BISTABLE RELAYS', which outputs when reached, includes four multi-channels, and reactor trip switches It can operate in place of 'AUXILIARY RELAY CABINET' which initializes the trip signal or initializes the operation of 'AUXILIARY RELAY CABINET'.

In addition, the first FPGA and the second FPGA monitor 'TEST & CALIBRATION', which performs diagnosis and measurement of BISTABLE COMPARATOR, BISTABLE RELAYS, BISTABLE COINCIDENCE LOGIC MATRICES, INITIATION LOGIC CIRCUIT, and monitors insulation breakdown of the supplied power supply and chassis ground. It can replace the function of 'GROUND DETECTION'.

4 is a view for explaining a digital signal electronic control method of a nuclear power plant according to an embodiment of the present invention.

The digital signal electronic control method of a nuclear power plant according to an embodiment of the present invention transmits a system status signal generated according to the operation of the nuclear power plant to at least one of the first FPGA and the second FPGA in an input buffer (step 401).

Next, the digital signal electronic control method of the nuclear power plant according to an embodiment of the present invention may output a system management signal in response to the transmitted system status signal in at least one of the first FPGA and the second FPGA ( Step 402).

Next, the digital signal electronic control method of the nuclear power plant according to an embodiment of the present invention may receive the output system management signal from the output buffer and transmit the received system management signal to the apparatus for controlling the nuclear power plant (step 403).

The digital signal electronic control method of a nuclear power plant according to an embodiment of the present invention transmits a first error detection signal from the first FPGA to the second FPGA, and the second FPGA transmits a second signal to the first FPGA. An error detection signal is transmitted, and at least one of the first error detection signal and the second error detection signal may include at least one of the input system status signal, checksum, CRC, and parity signal.

In addition, the digital signal electronic control method of the nuclear power plant according to an embodiment of the present invention, in the first FPGA, it is determined whether the second error detection signal received from the second FPGA is the same as the first error detection signal. The second FPGA may determine whether the first error detection signal received from the first FPGA is the same as the second error detection signal, and if the determination result is the same, generate an output signal according to a predetermined operation condition. To the output buffer.

For example, when the first FPGA is a master FPGA, the digital signal electronic control method of a nuclear power plant according to an embodiment of the present invention may distribute a plurality of sensed system state signals to the first FPGA.

If the ports (or pins) of the first FPGA are in normal operation, all of the plurality of input system state signals will be the same, and if not, at least one of the plurality of input system state signals will not be identical. .

If at least one of the system state signals is not the same, the first FPGA may not be determined to operate normally, and thus the system management signal may be controlled to output a system management signal using the second FPGA through a failover signal.

That is, the digital signal electronic control method of a nuclear power plant according to an embodiment of the present invention distributes a plurality of input signals, transfers them to an FPGA, and then inputs them through different ports (or pins), and all of the input signals are the same. It may be determined whether or not the FPGA malfunctions.

That is, the digital signal electronic control method of the nuclear power plant according to an embodiment of the present invention may determine not only a malfunction of the FPGA itself but also a malfunction of an interface such as a pin or a port.

The digital signal electronic control method of a nuclear power plant according to an embodiment of the present invention may improve stability through a first FPGA replacing a specific card and a second FPGA replacing another specific card.

Specifically, the digital signal electronic control method of a nuclear power plant according to an embodiment of the present invention outputs a first system management signal corresponding to the received first system status signal by using a first FPGA, and the second FPGA By using, it may be considered a case of outputting a second system management signal corresponding to the received second system status signal.

At this time, the digital signal electronic control method of the nuclear power plant according to an embodiment of the present invention can monitor the state of each FPGA by monitoring the state of each other using the first FPGA and the second FPGA.

For example, when the first FPGA operates abnormally, the second FPGA operates in place of the first FPGA, and when the second FPGA operates abnormally, the first FPGA operates in the second FPGA. In operation, the controller may output at least one of the first system management signal and the second system management signal.

The digital signal electronic control method of a nuclear power plant according to an embodiment of the present invention controls the operation of the nuclear power plant in response to the output system management signal.

As a result, according to an embodiment of the present invention, when each logic IC is implemented as two redundant FPGAs, and when a problem occurs in one FPGA, a problem occurs in the logic IC by processing selected operations in another FPGA. You can prepare.

According to an embodiment of the present invention, not only a malfunction of the card itself, but also a malfunction of an input buffer or a malfunction of one or more ports or pins of the card can be detected.

In addition, according to one embodiment of the present invention, it can provide a function to detect the malfunction when the output is cut off.

In addition, according to an embodiment of the present invention, by setting the input and output of the two redundant FPGA to the same as the input and output of the card that performs the previously selected function, it is possible to minimize the change of hardware to improve the safety of the system.

The digital signal electronic control method of the nuclear power plant described above may be embodied in the form of program instructions that can be executed by various computer means and recorded in a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be those specially designed and constructed for the present invention or may be available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Magneto-optical media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

As described above, the present invention has been described by way of limited embodiments and drawings, but the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains various modifications and variations from such descriptions. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the equivalents of the claims, as well as the claims.

100: digital signal electronic control device of nuclear power plant
110: first input buffer 120: first FPGA
130: first output buffer 140: second input buffer
150: second FPGA 160: second output buffer

Claims (11)

A first FPGA and a second FPGA for outputting a system management signal;
An input buffer configured to transmit a system status signal generated according to operation of a nuclear power plant to at least one of the first FPGA and the second FPGA; And
An output buffer which receives the output system management signal and delivers it to a device for controlling the nuclear power plant
Including,
The first FPGA sends a first error detection signal to the second FPGA, the second FPGA sends a second error detection signal to the first FPGA,
The first FPGA determines whether the second error detection signal received from the second FPGA is the same as the first error detection signal, and if the determination result is the same, generates an output signal according to a predetermined operation condition to generate the output buffer. To,
The second FPGA determines whether the first error detection signal received from the first FPGA is the same as the second error detection signal, and if the determination result is the same, generates an output signal according to a predetermined operation condition to generate the output buffer. Digital signal electronic control device of nuclear power plant to transmit to. delete The method of claim 1,
And at least one of the first error detection signal and the second error detection signal includes at least one of the input system status signal, checksum, CRC, and parity signal. delete delete The method of claim 1,
And the first FPGA and the second FPGA perform an output signal conversion using a failover signal. The method of claim 1,
The input buffer is
And digitally distribute the system status signals to the first FPGA and the second FPGA. The method of claim 7, wherein
At least one of the first FPGA and the second FPGA compares the plurality of distributed system state signals input to a plurality of different ports, and determines whether the plurality of distributed system state signals are the same. Digital signal electronic control device of power plant. 9. The method of claim 8,
At least one of the first FPGA and the second FPGA generates and outputs a failover signal when the plurality of distributed system state signals are not the same. Transmitting, at an input buffer, a system status signal generated according to operation of the nuclear power plant to at least one of the first FPGA and the second FPGA;
Outputting a system management signal in response to the transmitted system status signal in at least one of the first FPGA and the second FPGA; And
Receiving an output system management signal from an output buffer and transferring the received system management signal to a device for controlling the nuclear power plant
Including,
Transmitting a first error detection signal from the first FPGA to the second FPGA;
Transmitting a second error detection signal from the second FPGA to the first FPGA;
Determining whether the second error detection signal received from the second FPGA in the first FPGA is the same as the first error detection signal;
Determining whether the first error detection signal received from the first FPGA in the second FPGA is the same as the second error detection signal; And
If the determination result is the same, generating an output signal according to a predetermined operation condition and transmitting the same to the output buffer;
Further comprising:
And at least one of the first error detection signal and the second error detection signal comprises at least one of the input system status signal, checksum, CRC, and parity signal.
delete

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