KR101165547B1 - Decision feedback equalizer block for receiver of voltage-mode driver and receiver using the decision feedback equalizer block - Google Patents

Abstract

The decision feedback equalizer block according to the present invention includes an adder for removing an offset from an input signal, a sampler connected to the adder to output a sample signal for the input signal, and a sampler connected to the sampler according to a determination result signal. And a first unit block and a second unit block, the equalizer unit block including a mux for selecting the final sample signal and a DFF connected to the mux. The adder of the present invention is characterized by including two switched capacitors.

Description

DECISION FEEDBACK EQUALIZER BLOCK FOR RECEIVER OF VOLTAGE-MODE DRIVER AND RECEIVER USING THE DECISION FEEDBACK EQUALIZER BLOCK}

The present invention relates to a decision feedback equalizer for use in a receiver. In particular, the present invention relates to a decision feedback equalizer block for a voltage mode driver, and to a decision feedback equalizer block capable of offset cancellation and data and edge equalization, and a receiver using the same.

The demand for high-speed memory is growing, and the current data rate of DRAM is over 4Gbps. However, the bandwidth of the limited channel distorts the original data by inter symbol interference (ISI), and the voltage margin and time margin are reduced, which causes the problem of limiting the performance of the receiver.

In order to eliminate Data ISI, a method of improving a voltage margin by using a feed-forward equalizer and a decision feedback equalizer has been introduced. In addition, in applications where the phase of clock and data is ideally adjusted using clock data recovery, the edge ISI is eliminated because distortion caused by edge ISI causes errors in the clock-data recovery operation. Edge-only equalizer techniques are used to improve timing margins.

 Meanwhile, as the commercialization of portable products is accelerated, efforts are being made to reduce the power consumption of I / O to construct circuits at low power. I / O signaling is used from the existing VDD base to the GND base to reduce the power of the I / O.

Signaling to the GND base requires circuit design based on the PMOS, which has a larger capacitance than the NMOS and is not suitable for high speed operation. Therefore, for high speed operation, the NND-based receiver is designed and used using the GND base signal using a level shifter.

The feedforward equalizer, a technique used to improve voltage margin, is capable of high speed operation but is vulnerable to high frequency noise, while the decision feedback equalizer is insensitive to noise and simple to implement, but it is difficult to operate at high speed due to the limitation of the operation speed due to feedback delay. have.

To solve this problem of decision feedback equalizer, loop-unrolling decision feedback equalizer can be used to reduce the delay caused by feedback, but it is suitable for low power design due to large circuit area and high current consumption. You will not.

In addition, a feed forward equalizer, a loop unrolling decision feedback equalizer, and an edge-only equalizer have a problem in that voltage margin and time margin cannot be improved at the same time.

In conventional current mode equalizers, increasing the resistance (R) of the load increases the voltage gain but reduces the bandwidth, which is correlated. In the current mode equalizer using charging and discharging RC at the load stage, the voltage gain can be increased by increasing the current without increasing the resistor R to increase the operation speed. The effect of equalization was maximized. This use of current mode equalizers makes them unsuitable for low power applications.

To reduce the power consumption of high-speed circuits, an additional level shifter is required, using GND-based signaling techniques in I / O. The level shifter used to change only the signaling level also affects current consumption. There was a problem with madness.

The decision feedback equalizer block used in the receiver of the voltage mode driver according to the present invention and the receiver using the decision feedback equalizer block aim at the following problems.

First, we want to improve the performance of the receiver by removing the voltage offset without any additional device in the equalizer of the receiver.

Second, the equalizer of the data ISI and the edge ISI are performed in the equalizer of the receiver to increase the voltage margin and the time margin.

Third, the ground (GND) base and NMOS is designed to enable high-speed operation.

Fourth, the crystal feedback equalizer can be driven at low power by using a switched capacitor.

The solution to the problem of the present invention is not limited to those mentioned above, and other solutions not mentioned can be clearly understood by those skilled in the art from the following description.

The decision feedback equalizer block used in the receiver of the voltage mode driver according to the present invention is an adder for removing an offset from an input signal, a sampler connected to the adder and outputting a sample signal for the input signal, and a sampler connected to the decision result signal. Therefore, it includes an equalizer unit block including a mux for selecting the final sample signal among the sample signal output by the sampler and the DFF connected to the mux.

The decision feedback equalizer block used in the receiver of the voltage mode driver according to the present invention includes a first unit block and a second unit block.

The adder of the decision feedback equalizer block used in the receiver of the voltage mode driver according to the invention is characterized in that it comprises two switched capacitors.

The adder of the first unit block of the decision feedback equalizer block used in the receiver of the voltage mode driver according to the present invention outputs a result value (poutn1) of ((vcm1) + (VCM2 + CV)-(INN)). A 1-1 switched capacitor and a 1-2 switched capacitor which outputs (poutp1) the result of ((vcm1) + (VCM2-CV)-(INP)), and the adder of the second unit block is ((vcm1) Outputs the result of (-1 vv1) + (VCM2 + CV)-(INP)) and a 2-1 switched capacitor that outputs the result of (noutn1) + (VCM2-CV)-(INN)) (noutp1) ) Is characterized in that it comprises a 2-2 switched capacitor.

Here, VCM1 is a first input voltage value, VCM2 is a second input voltage value, CV is a control voltage value, INN is a negative input signal value, and INP is a positive input signal value.

The adder of the first unit block and the adder of the second unit block of the decision feedback equalizer block used in the receiver of the voltage mode driver according to the present invention have a value equal to 0 and the capacitor negative output value or the capacitor positive output value under the condition that INN and INP are equal. The offset is performed by changing the control voltage value CV such that the probability of 1 is 0.5.

A receiver using the decision feedback equalizer according to the present invention includes an adder for removing an offset from an input signal, a sampler for outputting a sample signal for the input signal, and a final sample signal among sample signals output by the sampler according to the first data determination result signal. And a first data equalizer block including a first unit block and a second unit block, the equalizer unit block including mux and DFF.

A receiver using the decision feedback equalizer according to the present invention includes an adder for removing an offset from an input signal, a sampler for outputting a sample signal for the input signal, and a final sample signal among sample signals output by the sampler according to the first edge determination result signal. And a first edge equalizer block including a first unit block and a second unit block, the equalizer unit block including mux and DFF.

A receiver using the decision feedback equalizer according to the present invention includes an adder for removing an offset from an input signal, a sampler for outputting a sample signal for the input signal, and a final sample signal among sample signals output by the sampler according to the second data determination result signal. And a second data equalizer block including a first unit block and a second unit block, the equalizer unit block including a mux and a connected DFF.

A receiver using the decision feedback equalizer according to the present invention includes an adder for removing an offset from an input signal, a sampler for outputting a sample signal for the input signal, and a final sample signal among sample signals output by the sampler according to the second edge determination result signal. And a second edge equalizer block including a first unit block and a second unit block, the equalizer unit block including mux and DFF.

An offset elimination mode in which the first data equalizer block, the first edge equalizer block, the second data equalizer block, and the second edge equalizer block remove offsets through an adder included in each equalizer block. And performing an equalization mode for performing data equalization through the first data equalizer block and the second data equalizer block, and performing edge equalization through the first edge equalizer block and the second edge equalizer block. It is characterized by.

The adder of the first unit block and the adder of the second unit block according to the present invention are characterized by including two switched capacitors.

In the offset elimination mode according to the present invention, the adder of the first unit block outputs the result of ((vcm1) + (VCM2 + CV)-(INN)) of the 1-1 switched capacitor and ((vcm1) + 1-2 switched capacitor outputting (poutp1) the result of + (VCM2-CV)-(INP)), and the adder of the second unit block has ((vcm1) + (VCM2 + CV)-(INN A 2-1 switched capacitor that outputs the result of ()) and a 2-2 switched capacitor that outputs the result of ((vcm1) + (VCM2-CV)-(INP)) (noutp1). The control voltage value CV may have different values for each of the first data equalizer block, the second data equalizer block, the first edge equalizer block, and the second edge equalizer block.

In the offset cancellation mode according to the present invention, the adder of the first unit block and the adder of the second unit block have a control voltage value such that the probability of 0 and 1 is 0.5 in the capacitor negative output value or the capacitor positive output value, respectively, under the condition that INN = INP. The offset mode may be performed by changing the CV.

The first clock value and the third clock value are input to the adder of the first data equalizer block according to the present invention, the second clock value is input to the sampler of the first data equalizer block, and the second clock value is input to the sampler of the first data equalizer block. The second clock value is input to the DFF, the second clock value and the fourth clock value are input to the adder of the first edge equalizer block, and the third clock value is input to the sampler of the first edge equalizer block. A third clock value is input to the DFF of the one edge equalizer block, a third clock value and a first clock value are input to the adder of the second data equalizer block, and a fourth clock is input to the sampler of the second data equalizer block. A value is input, a fourth clock value is input to the DFF of the second data equalizer block, a fourth clock value and a second clock value are input to the adder of the second edge equalizer block, and the second edge equalizer block is input. The first clock value is input to the sampler of the second edge equalizer. DFF has the lock is characterized in that the first clock input value.

In the equalizing mode according to the present invention, the adder of the first data equalizer block uses a switched capacitor. When the first clock value is low and the third clock value is high in the 1-1 switched capacitor, the adder of the first data equalizer block is changed. If the VCM1 is output to the sampler and the first clock value is high and the third clock value is low, the VCM1 + VCM2-INN + tap weight (a1) values are output, and the first clock value is output from the 1-2 switch capacitor. Is low and the third clock value is high, VCM1 is output to the sampler of the first data equalizer block. If the first clock value is high and the third clock value is low, VCM1 + VCM2-INP-tap weight (a1). Value is output, and when the first clock value is low and the third clock value is high in the 2-1 switched capacitor, VCM1 is output to the sampler of the first data equalizer block, and the first clock value is high and the third value is increased. If the clock value is low, VCM1 + VCM2-INN-tap The output value a1 and output the VCM1 to the sampler of the first data equalizer block if the first clock value is low and the third clock value is high in the 2-2 switched capacitor. When the third clock value is high and the third clock value is low, VCM1 + VCM2-INP + tap weight value a1 is output.

Here, a low clock value means a case where the clock value is 0, and a high clock value means a case where the clock value is 1. The same expression is used below.

In the equalization mode according to the present invention, the tap weight a1 is determined as a value obtained by adding the weight control value a''1 to the voltage control values CV and a'1 determined in the offset mode of the first data equalizer block. Where a''1 is equal to the weight control value a''2 of the second data equalizer block such that data ISI is removed.

In the equalizing mode according to the present invention, the adder of the second data equalizer block uses a switched capacitor. When the third clock value is low and the first clock value is high in the 1-1 switched capacitor, the adder of the second data equalizer block is changed. If the VCM1 is output to the sampler, and the third clock value is high and the first clock value is low, the VCM1 + VCM2-INN + tap weight value a2 is output, and the third clock value is output from the 1-2 switch capacitor. Is low and the first clock value is high, VCM1 is output to the sampler of the second data equalizer block. If the third clock value is high and the first clock value is low, VCM1 + VCM2-INP-tap weight value (a2). If the third clock value is low and the first clock value is high in the 2-1 switched capacitor, VCM1 is output to the sampler of the second data equalizer block, and the third clock value is high and the first clock value is increased. If the clock value is low, VCM1 + VCM2-INN-tap The output value a2 and output the VCM1 to the sampler of the second data equalizer block when the third clock value is low and the first clock value is high in the 2-2 switched capacitor. When the first clock value is high and the first clock value is low, VCM1 + VCM2-INP + tap weight value a2 is output.

In the equalization mode according to the present invention, the tap weight a2 is determined as a2 = voltage control value CV, a'2 + weight control value a''2 determined in the offset mode of the second data equalizer block, a''2 is equal to the weight control value a''1 of the first data equalizer block such that data ISI is removed.

In the equalization mode according to the present invention, the adder of the first edge equalizer block in the equalization mode uses a switched capacitor, and the first edge equalization is performed when the second clock value is low and the fourth clock value is high in the 1-1 switched capacitor. When the second clock value is high and the fourth clock value is low, VCM1 is output to the sampler of the previous block, and when the second clock value is high, the VCM1 + VCM2-INN + tap weight value b1 is output. If the second clock value is low and the fourth clock value is high, VCM1 is output to the sampler of the first edge equalizer block. If the second clock value is high and the fourth clock value is low, VCM1 + VCM2-INP-tap weight. The value b1 is outputted, and when the second clock value is low and the fourth clock value is high in the 2-1 switched capacitor, VCM1 is outputted to the sampler of the first edge equalizer block, and the second clock value is If high and the fourth clock value is low, VCM1 + VCM2-INN- When the tap weight value b1 is output, and when the second clock value is low and the fourth clock value is high in the 2-1 switched capacitor, VCM1 is output to the sampler of the first edge equalizer block, and the second clock is generated. When the value is high and the fourth clock value is low, VCM1 + VCM2-INP + tap weight value b1 is output.

In the equalization mode according to the present invention, the tap weight b1 is determined as a value obtained by adding the weight control value b''1 to the voltage control values CV and b'2 determined in the offset mode of the first edge equalizer block. B ″ 1 is equal to the weight control value b ″ 2 of the second edge equalizer block such that the edge ISI is removed.

In the equalization mode according to the present invention, the adder of the second edge equalizer block in the equalization mode uses a switched capacitor, and if the fourth clock value is low and the second clock value is high in the 1-1 switched capacitor, the second edge equalization is performed. If VCM1 is output to the sampler of the previous block, and if the fourth clock value is high and the second clock value is low, VCM1 + VCM2-INN + tap weight value (b2) is output, and the first to second switch capacitors 4 If the clock value is low and the second clock value is high, VCM1 is output to the sampler of the second edge equalizer block. If the fourth clock value is high and the second clock value is low, VCM1 + VCM2-INP- tap weight The value b2 is outputted, and when the fourth clock value is low and the second clock value is high in the 2-1 switched capacitor, VCM1 is outputted to the sampler of the second edge equalizer block, and the fourth clock value is If high and the second clock is low, VCM1 + VCM2-INN- When the weight value b2 is output, and when the first clock value is low and the third clock value is high in the 2-2 switched capacitor, VCM1 is output to the sampler of the second edge equalizer block. If the third clock value is high and VCM1 + VCM2-INP + tap weight value b2 is output.

In the equalization mode according to the present invention, the tap weight b2 is determined as a value obtained by adding the weight control value b''2 to the voltage control values CV and b'2 determined in the offset mode of the second edge equalizer block. B ″ 2 is equal to the weight control value b ″ 1 of the first edge equalizer block such that edge ISI is removed.

In the equalization mode according to the present invention, the value output from the adder of the first data equalizer block is sampled by the second clock and output as two sample signals, and is applied to the final signals outp3 and outn3 of the second data equalizer block. Therefore, the final sample signal is selected from the two sample signals in the mux.

In the equalization mode according to the present invention, the second data equalizer block has a value output from the adder sampled by the fourth clock and output as two sample signals, and is applied to the final signals outp1 and outn1 of the first data equalizer block. Therefore, the final sample signal is selected from the two sample signals in the mux.

In the equalization mode according to the present invention, the first edge equalizer block has a value output from the adder sampled by a third clock and output as two sample signals, and is applied to the final signals outp3 and outn3 of the second data equalizer block. Therefore, the final sample signal is selected from the two sample signals in the mux.

In the equalization mode according to the present invention, the second edge equalizer block has a value output from the adder sampled by the first clock and output as two sample signals, and is applied to the final signals outp1 and outn1 of the first data equalizer block. Therefore, the final sample signal is selected from the two sample signals in the mux.

In the equalization mode according to the present invention, the first data equalizer block has a value output from the adder sampled by the second clock and output as two sample signals, and a signal selected from the mux of the second data equalizer block ( sel 3). The final sample signal sel 1 is selected from the two sample signals in the MUX.

In the equalization mode according to the present invention, the second data equalizer block has a value output from the adder sampled by a fourth clock and output as two sample signals, and a signal selected from the mux of the first data equalizer block ( sel 1). The final sample signal sel 3 is selected from the two sample signals in the MUX.

In the equalization mode according to the present invention, the first edge equalizer block has a value output from the adder sampled by a third clock and output as two sample signals, and a signal selected from the mux of the second data equalizer block ( sel 3). The final sample signal is selected from the two sample signals in the mux according to.

In the equalization mode according to the present invention, the second edge equalizer block has a value output from the adder sampled by the first clock and output as two sample signals, and a signal selected from the mux of the first data equalizer block ( sel 1). The final sample signal is selected from the two sample signals in the mux according to.

The decision feedback equalizer block and the receiver using the decision feedback equalizer block used in the receiver of the voltage mode driver according to the present invention have the following effects.

First, the performance of the receiver is high by removing the voltage offset from the adder of the equalizer of the receiver.

Second, equalization is performed not only at the data ISI but also at the edge ISI at the equalizer of the receiver, thereby reducing data distortion due to high speed operation.

Third, by providing an equalizer using ground base signaling, it is possible to use in a low power circuit.

Fourth, high-speed operation is possible by designing a circuit based on NMOS while using ground base.

Fifth, while designing a circuit with an NMOS base, using a switched capacitor (capsitor), it is possible to manufacture a low-power receiver with a simple structure without a separate level shifter.

The effects of the present invention are not limited to those mentioned above, and other effects not mentioned can be clearly understood by those skilled in the art from the following description.

1 is a block diagram illustrating a decision feedback equalizer block and an offset operation according to an embodiment of the present invention.
2 is a circuit diagram illustrating the operation of the switched capacitor according to the present invention.
3 is a block diagram illustrating a decision feedback equalizer block according to the first equalization scheme of the present invention.
4 is a block diagram showing the structure of an entire receiver using a decision feedback equalizer according to the first equalization scheme of the present invention.
5 is a timing diagram of a sampler, a mux, and a data flip-flop (DFF) according to the first equalization method of the present invention.
6 (a) shows a feedback path according to the first equalization scheme of the present invention, and FIG. 6 (b) shows a feedback path according to the second equalization scheme.
7 is a block diagram illustrating a path for explaining that the effective space of the MUX output is not 2 * T _MUX .
8 is a block diagram illustrating a decision feedback equalizer block according to a second equalization scheme of the present invention.
9 is a block diagram showing the structure of a receiver using a decision feedback equalizer according to the second equalization scheme of the present invention.
10 is a timing diagram of a sampler, a mux, and a DFF according to the second equalization method of the present invention.

In the equalization scheme according to the present invention described below, the equalization is performed in a manner in which a general decision feedback equalizer operates, except for a portion which is a feature of the present invention. Therefore, the part which can be fully understood by those skilled in the art will be omitted.

The present invention provides low power circuit design by making I / O using GND base signaling, eliminates voltage offset from the equalizer, and equalizes not only data ISI but also edge ISI. The key feature is that it does not require a level shifter while designing with NMOS.

Hereinafter, a decision feedback equalizer block used in a receiver of a voltage mode driver according to the present invention and a receiver using the decision feedback equalizer block will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a decision feedback equalizer block and an offset operation according to an embodiment of the present invention.

First, the decision feedback equalizer block used in the receiver of the voltage mode driver according to the present invention will be described.

The decision feedback equalizer block according to the present invention includes an adder for removing an offset from an input signal, a sampler connected to the adder to output a sample signal for the input signal, and a sampler connected to the sampler according to a determination result signal. And a first unit block and a second unit block, the equalizer unit block including a mux for selecting the final sample signal and a DFF connected to the mux.

The adder of the present invention is characterized by including two switched-capacitors. The two signals output from the two switched capacitors are input to the sampler of the unit block.

First, the offset removing method according to the present invention will be described. The voltage offset at the receiver degrades the receiver's performance because it lowers the accuracy of the data bits. In addition, the minimum input voltage magnitude that the CDR can accurately detect increases, resulting in duty cycle distortion. This reduces the overall margin of data resiliency and increases the bit error rate (BER). Therefore, the offset cancellation capability at the receiving end is necessary.

The basic structure for offset elimination is shown in FIG. In FIG. 1, a'1 corresponds to the following control voltage value CV.

The adder of the first unit block has a 1-1 switched capacitor that outputs the result of ((vcm1) + (VCM2 + CV)-(INN)) (poutn1) and ((vcm1) + (VCM2-CV)-( And a 1-2 switched capacitor for outputting the result value of INP).

The adder of the second unit block has a 2-1 switched capacitor that outputs (noutn1) the result of ((vcm1) + (VCM2 + CV)-(INN)) and ((vcm1) + (VCM2-CV)-( And a 2-2 switched capacitor for outputting the result of INP)) (noutp1).

Here, VCM1 is a first input voltage value, VCM2 is a second input voltage value, CV is a control voltage value, INN is a negative input signal value, and INP is a positive input signal value.

In this case, when the equalization function is performed in the decision feedback equalizer block, the adder of the second unit block switches 2-1 to output (noutn1) the result of ((vcm1) + (VCM2-CV)-(INN)). Capacitors and

and a 2-2 switched capacitor that outputs (noutp1) the result of ((vcm1) + (VCM2 + CV)-(INP)).

When a'1 = 0 with INN = INP, poutn1 = poutp1 = noutn1 = noutp1 = vcm1 + vcm2-inn, so the probability that outp1 is 0 and 1 is ideally 0.5. However, if there is an offset due to a mismatch, outp1 is zero or one.

In the state of INN = INP, poutn1 = noutn1 = vcm1 + vcm2-inn + a'1 and poutp1 = noutp1 = vcm1 + vcm2-inn-a'1 according to the control voltage, so the probability that outp1 is 0 and 1 is 0.5. The offset can be removed by changing the value of a'1 as much as possible.

That is, in the equalizer block of the present invention, the adder of the first unit block and the adder of the second unit block have a control voltage such that the probability of 0 and 1 is 0.5 in the capacitor negative output value or the capacitor positive output value, respectively, under the condition that INN = INP. The offset may be performed by changing the value CV.

The receiver using the decision feedback equalizer according to the present invention includes adders 111 and 121 for removing an offset from an input signal, samplers 112 and 122 for outputting a sample signal for the input signal, and a sampler output according to a first data determination result signal. A first data equalizer block including a first unit block 110 and a second unit block 120 that are equalizer unit blocks including mux 113 and 123 and a DFF 114 and 124 for selecting a final sample signal among sample signals. (100), adders 311 and 321 for removing an offset from the input signal, samplers 312 and 322 for outputting a sample signal for the input signal, and a final sample signal selected from the sample signals output by the sampler according to the first edge determination result signal The first edge equalizer block 300 including the first unit block 310 and the second unit block 320, which are equalizer unit blocks including the mux 313 and 323 and the DFFs 314 and 324, offset from an input signal. To remove Adders 211 and 221, Samplers 212 and 222 for outputting sample signals for input signals, MUX 213 and 223 for selecting the final sample signal among sample signals output by the sampler according to the second data determination result signal, and connected DFFs 214 and 224. The second data equalizer block 200 including the first unit block 210 and the second unit block 220, which are equalizer unit blocks including an adder, and adders 411 and 421 for removing an offset from an input signal, an input signal. An equalizer unit block including samplers 412 and 422 for outputting a sample signal for a signal, a mux 413 and 423 for selecting a final sample signal among sample signals output by the sampler according to a second edge determination result signal, and a DFF 414 and 424 A second edge equalizer block 400 including a first unit block 410 and a second unit block 420 is included.

The equalization scheme differs depending on the source of the first data determination result signal, the second data determination result signal, the first edge determination result signal, and the second edge determination result signal. Details will be described later.

The first data equalizer block 100, the first edge equalizer block 300, the second data equalizer block 200, and the second edge equalizer block 400 are connected through adders included in each equalizer block. Offset equalization mode, each of which removes an offset, and data equalization through a first data equalizer block and a second data equalizer block, and edge equalization through a first edge equalizer block and a second edge equalizer block. Perform an equalization mode to do it. The offset elimination mode is performed in the same manner as described above.

The first clock value ck1 and the third clock value ck3 are input to the adders 111 and 121 of the first data equalizer block, and the second clock value ck2 to the samplers 112 and 122 of the first data equalizer block. The second clock value is input to the DFFs 114 and 124 of the first data equalizer block, and the second clock value and the fourth clock value ck4 are input to the adders 311 and 321 of the first edge equalizer block. The third clock value is input to the samplers 312 and 322 of the first edge equalizer block, and the third clock value is input to the DFFs 314 and 324 of the first edge equalizer block. The third clock value and the first clock value are input to the adders 211 and 221, the fourth clock value is input to the samplers 212 and 222 of the second data equalizer block, and the fourth clock value is input to the DFFs 214 and 224 of the second data equalizer block. The fourth clock value is input, and the fourth clock value and the second clock value are input to the adders 411 and 421 of the second edge equalizer block, and the second edge is input. A sampler (412 422), the first clock value is input to the DFF 2 (414,424) of the edge of the equalizer block equalizer block is characterized in that the first clock input value.

Here, a low clock value refers to a ground terminal (VSS) state having a clock value of 0, and a high clock value refers to a voltage terminal (VDD) state having a clock value of 1. The same meaning is used below.

The present invention has a first equalization scheme and a second equalization scheme, in which the clock value inputs described above are common. The difference between the first equalization scheme and the second equalization scheme is in the feedback path.

First equalization

2 is a circuit diagram illustrating the operation of the switched capacitor according to the present invention. 3 is a block diagram illustrating a decision feedback equalizer block according to the first equalization scheme of the present invention. 4 is a block diagram showing the structure of an entire receiver using a decision feedback equalizer according to the first equalization scheme of the present invention. 3 and 4, the switched capacitor in the adder of the second data equalizer block, the first edge equalizer block, and the second edge equalizer block is not shown.

As a double data rate receiving end structure, data is sampled by the clocks of the first clock ck1 and the third clock ck3 of the adder, and the edges are sampled by the clocks of the second clock ck2 and the fourth clock ck4. The CDR can determine if the clock and data are aligned correctly.

In the equalization mode, when the adders 111 and 121 of the first data equalizer block 100 use a switched capacitor, when the first clock value is low and the third clock value is high in the 1-1 switched capacitor 111-1, The VCM1 is output to the sampler of the first data equalizer block. When the first clock value is high and the third clock value is low, the value of (VCM1 + VCM2-INN + tap weight a1) is output.

In the 1-2 switched capacitor 111-2, when the first clock value is low and the third clock value is high, VCM1 is output to the sampler of the first data equalizer block, and the first clock value is high and the third clock is high. If the value is low, the value (VCM1 + VCM2-INP-tap weight a1) is output.

In the 2-1 switched capacitor 121-1, when the first clock value is low and the third clock value is high, VCM1 is output to the sampler of the first data equalizer block, and the first clock value is high and the third clock is high. If the value is low, (VCM1 + VCM2-INN-tap weight value a1) is outputted.

In the second-2 switched capacitor 122-2, when the first clock value is low and the third clock value is high, VCM1 is output to the sampler of the first data equalizer block, and the first clock value is high and the third clock is generated. If the value is low, (VCM1 + VCM2-INP + tap weight value a1) is outputted.

Set a1 '' = a2 '' to remove the data ISI of the channel well and b1 '' = b2 '' to remove the timing ISI well.

Tap weight is set by adding a1 ', a2', b1 ', b2' and a1, b1 obtained in the offset elimination mode. That is, the tap weight is set to a1 = a1 '' + a1 ', b1 = b1''+b1', a2 = a1 '' + a2 ', b2 = b1''+b2'. vcm2 + a1 and vcm2-a1 correspond to the previous bits of the DFE.

In the equalization mode according to the present invention, the adders 211 and 221 of the second data equalizer block 200 use a switched capacitor so that the third clock value is low in the 1-1 switched capacitor 211-1 and the first clock value. In this case, VCM1 is outputted to the sampler of the second data equalizer block, and when the third clock value is high and the first clock value is low, (VCM1 + VCM2-INN + tap weight value a2) is output. When the third clock value is low and the first clock value is high in the 1-2 switched capacitor 211-2, VCM1 is output to the sampler of the second data equalizer block, and the third clock value is high. If one clock value is low, (VCM1 + VCM2-INP-tap weight value (a2)) is output, and the third clock value is low and the first clock value is high in the 2-1 switched capacitor 221-1. In this case, VCM1 is output to the sampler of the second data equalizer block, and the third clock value is high and the first clock value is low. In the case of (VCM1 + VCM2-INN-tap weight value a2), the second clock value is low and the second data is high in the 2-2 switched capacitor 221-2. When the VCM1 is output to the sampler of the equalizer block, and the third clock value is high and the first clock value is low, (VCM1 + VCM2-INP + tap weight value a2) is output.

Here, the tap weight a2 is determined by the offset mode of the second data equalizer block (voltage control value CV, a'2 + weight control value a''2), where a''2 is data. It is characterized in that the same as the weight control value (a''1) of the first data equalizer block so that ISI is removed.

In the equalization mode according to the present invention, the adders 311 and 321 of the first edge equalizer block 300 use a switched capacitor to have a low second clock value and a fourth clock value in the 1-1 switched capacitor 311-1. In this case, VCM1 is outputted to the sampler of the first edge equalizer block, and when the second clock value is high and the fourth clock value is low, (VCM1 + VCM2-INN + tap weight value b1) is output. When the second clock value is low and the fourth clock value is high in the 1-2 switched capacitor 311-2, VCM1 is output to the sampler of the first edge equalizer block, and the second clock value is high. When the 4 clock value is low, (VCM1 + VCM2-INP-tap weight value (b1)) is outputted, and the 2nd-1 clock value is low and the 4th clock value is high by the 2-1 switched capacitor 321-1. VCM1 is output to the sampler of the first edge equalizer block, and when the second clock value is high and the fourth clock value is low, CM1 + VCM2-INN-tap weight value b1), and when the second clock value is low and the fourth clock value is high in the 2-2 switched capacitor 321-2, the first edge equalizer block VCM1 is output to the sampler, and when the second clock value is high and the fourth clock value is low, (VCM1 + VCM2-INP + tap weight value b1) is output.

The tap weight is determined by b1 = voltage control value CV, b'2 + weight control value b''1 determined in the offset mode of the first edge equalizer block, where b''1 is such that the edge ISI is removed. And the weight control value b " 2 of the second edge equalizer block.

In the equalization mode according to the present invention, the adders 411 and 421 of the second edge equalizer block 400 use a switched capacitor to have a low fourth clock value and a second clock value in the 1-1 switched capacitor 411-1. In this case, VCM1 is output to the sampler of the second edge equalizer block, and when the fourth clock value is high and the second clock value is low, (VCM1 + VCM2-INN + tap weight value (b2)) is output. When the fourth clock value is low and the second clock value is high in the 1-2 switched capacitor 411-2, VCM1 is output to the sampler of the second edge equalizer block, and the fourth clock value is high. If the second clock value is low, (VCM1 + VCM2-INP-tap weight value (b2)) is output, and the second clock value is low and the second clock value is high at the 2-1 switched capacitor 421-1. In this case, VCM1 is output to the sampler of the second edge equalizer block, and when the fourth clock value is high and the second clock value is low ( VCM1 + VCM2-INN-tap weight value b2), and when the first clock value is low and the third clock value is high in the 2-2 switched capacitor 421-2, the second edge equalizer block VCM1 is output to the sampler, and when the first clock value is high and the third clock value is low, (VCM1 + VCM2-INP + tap weight value b2) is output.

Where the tap weight is determined by the voltage control value CV, b'2 and the weight control value b''2 determined in the offset mode of the second edge equalizer block, where b''2 is the edge ISI removed. It is characterized in that the same as the weight control value (b '1) of the first edge equalizer block.

In the first equalization scheme, the decision result signal in which the mux selects the final sample signal depends on the final signal of each equalizer block.

That is, the values output from the adders 111 and 121 of the first data equalizer block are sampled by the second clock and output as two sample signals, and the final signals outp3 and outn3 of the second data equalizer block 200 are output. The final sample signal is selected from the two sample signals in the mux.

In the second data equalizer block, values output from the adders 211 and 221 are sampled by the fourth clock and output as two sample signals, and according to the final signals outp1 and outn1 of the first data equalizer block 100. The final sample signal is selected from the two sample signals in the mux.

In the first edge equalizer block, the values output from the adders 311 and 321 are sampled by the third clock and output as two sample signals, and according to the final signals outp3 and outn3 of the second data equalizer block 200. The final sample signal is selected from the two sample signals in the mux.

In the second edge equalizer block, the values output from the adders 411 and 421 are sampled by the first clock and output as two sample signals, and according to the final signals outp1 and outn1 of the first data equalizer block 100. The final sample signal is selected from the two sample signals in the mux.

5 is a timing diagram of a sampler, a mux, and a DFF according to the first equalization scheme of the present invention.

The poutp1, poutn1 / noutp1, and noutn1 output from the switched capacitor described above are sampled by ck2 so that after the delay of the sampler, the outputs of the two samplers come out as aH and aL. This signal is selected as the waveform of MUX outut1 by selecting the proper value of aH or aL from MUX by the output (e) of another branch (path out3). This signal becomes a signal for selection (bH, bL) of the MUX of the path where the next out3 comes out in synchronization with ck2.

Second equalization

6 (a) shows a feedback path according to the first equalization scheme of the present invention, and FIG. 6 (b) shows a feedback path according to the second equalization scheme.

In the second equalization scheme, the weight control value selection process through the offset mode and the switched capacitor is the same as the first equalization scheme.

In the structure of the DFE, the result of the final signal is fed back to the input of the adder, which makes it difficult to operate at high speed to remove the ISI within one period. The conventional method widely used to make such a high-speed operation DFE is not to receive the result of the final signal as an input, but to make two branches through the final signal result of the other branch with the result of the previous data (0,1). Selecting one of them using MUX reduces the feedback delay.

However, the delay between MUX and DFF must be within 1 UI (Unit Interval) and the set-up time of the DFF must be secured. Time delay: T _DATA > T _MUX + T _{DFF - setup} + T _DFF There is a limit. When the DFE is used in a high-speed application, a large power consumption in the DFF cannot be avoided because a DFF such as a true single phase clock (TSPC) with a very short delay and set-up time must be used. In the first equalization method, a DFF such as a TSPC must be used for low power high speed operation.

When using the same structure as the second equalization method, since only MUX exists in the feedback structure, it can be seen that high speed operation is possible because only the MUX delay needs to be secured to 1UI. In addition, if the delayed clock is used to secure the setup margin of the DFF, this DFE can secure a large timing margin. Therefore, as in the conventional method, a large power consumption DFF such as a TSPC with a very short delay and set-up time is not used. This eliminates the need to design low power, high speed DFEs.

The interval for which the MUX output from Method 2 is valid is not determined as 2 * T _MUX . Since the MUX output by the odd path is the MUX select signal of the even path, the MUX output of the even path is determined. Since the output of the determined MUX is the MUX select signal of the odd path, the output of the odd MUX is changed, and since the MUX output of the even path may change according to the change of the MUX select signal of the even path, the valid section of the MUX output is 2 *. It can be thought of as T _MUX . However, as a result of the change of the MUX output of a path, the output of the MUX of that path does not change after 2 * T _MUX .

7 illustrates a path for explaining that the effective space of the MUX output is not 2 * T _MUX . The case considered before is when all of (1), (2) and (3) below are satisfied. x [n-1] is the previous bit and x [n] is the current bit.

(1) The result of path1 is different from that of path3 = ISI occurrence = 0 (x [n-1]) 1 (x [n]), 1 (x [n-1]) 0 (x [n]) The case of a pattern.

(2) The change of the select signal of the even path = the result of the odd path = the mux input of the odd path is different. That is, input1 = 1, input2 = 0 or input1 = 0, input2 = 1.

(3) input1: Assuming previous bit is 0, input2: assuming previous bit is 1, so it occurs only when input1> = input2.

Consider the cases where input1 = 1 and input2 = 0 in (2) and (3) for the two cases shown in (1). The well-defined MUX select of the even path results in the MUX output of the even path corresponding to each case, which becomes the MUX select signal of the odd path and the MUX output of the odd path. In both cases, however, you can see that this output does not change. That is, the output of the even path does not occur when the mux select signal of the even path is changed again to change the even path result.

8 is a block diagram illustrating a decision feedback equalizer block according to a second equalization scheme of the present invention, and FIG. 9 is a block diagram showing a structure of a receiver using a decision feedback equalizer according to the second equalization scheme of the present invention. .

8 and 9, in the second equalization scheme, each data determination result signal and each edge determination result signal are based on the value selected by the mux, not the final signal of the equalizer block. This reduces the delay time.

Specifically, in the first data equalizer block 100, the values output from the adders 111 and 121 are sampled by the second clock and output as two sample signals, and the muxes 213 and 223 of the second data equalizer block 200 are output. The final sample signal sel 1 is selected from the two sample signals in the mux according to the signal sel 3 selected in.

In the second data equalizer block 200, the values output from the adders 211 and 221 are sampled by the fourth clock and output as two sample signals, and the mux 113 and 123 of the first data equalizer block 100 are selected. The final sample signal sel 3 is selected from the two sample signals in the mux according to the signal sel 1.

In the first edge equalizer block 300, values output from the adders 311 and 321 are sampled by the third clock and output as two sample signals, and selected from the muxes 213 and 223 of the second data equalizer block 200. The final sample signal is selected from the two sample signals in the mux according to the signal sel 3.

In the second edge equalizer block 400, values output from the adders 411 and 421 are sampled by the first clock and output as two sample signals, and selected from the mux 113 and 123 of the first data equalizer block 100. The final sample signal is selected from the two sample signals in the mux according to the signal sel 1.

10 is a timing diagram of a sampler, a mux, and a DFF according to the second equalization method of the present invention.

Poutp1, poutn1 / noutp1, and noutn1, which are obtained in the same way as the first equalization method, are sampled by ck2, and after the delay of the sampler, the outputs of the two samplers come out as a-H and a-L. This signal is selected as the waveform of MUX outut1 by selecting the proper value of a-H or a-L from MUX by MUX output (e) of other branch. Since the section where MUX output3 and sampler output1 overlap is 1UI + MUX delay, it is valid during this period, but 2UI- (1UI + MUX delay) = 1UI-MUX delay is not valid.

Sampling clock of DFF can use conventional DFF to secure set-up time within this valid interval. This eliminates the need for a DFF for high speed operation, thereby minimizing power consumption by the DFF.

Unlike the first equalization scheme, since the DFF is excluded from the feedback loop, only the MUX delay is a feedback loop delay, thereby overcoming the high-speed operation limit of the DFE.

The embodiments and drawings attached to this specification are merely to clearly show some of the technical ideas included in the present invention, and those skilled in the art can easily infer within the scope of the technical ideas included in the specification and drawings of the present invention. Modifications that can be made and specific embodiments will be apparent that all fall within the scope of the present invention.

100: first data equalizer block
110: first unit block of the first data equalizer block
111: the adder of the first unit data block
111-1: First-first switched capacitor of adder of first data equalizer block first unit block
111-2: 1-2 switched capacitor of the adder of the first unit of the first data equalizer block
112: sampler of the first unit block of the first data equalizer block
113: mux of first unit block of first data equalizer
114: DFF of the first data block of the first data equalizer block
120: second unit block of the first data equalizer block
121: the adder of the first data equalizer block and the second unit block
121-1: First-first switched capacitor of adder of first data equalizer block second unit block
121-2: 1-2 switch capacitor of the adder of the second unit block of the first data equalizer block
122: sampler of the second unit block of the first data equalizer block
123: mux of the first data equalizer block second unit block
124: DFF of the second unit block of the first data equalizer block
200: second data equalizer block
210: first unit block of the second data equalizer block
211: adder of the first unit block of the second data equalizer block
211-1: First-first switched capacitor of adder of second data equalizer block first unit block
211-2: 1-2 switched capacitor of the adder of the first unit block of the second data equalizer block
212: Sampler of the first unit block of the second data equalizer block
213: mux of the first unit block of the second data equalizer block
214: DFF of the first unit block of the second data equalizer block
220: second unit block of the second data equalizer block
221: adder of the second data block of the second data equalizer block
221-1: First-first switched capacitor of adder of second data equalizer block second unit block
221-2: 1-2 switched capacitor of the adder of the second data block of the second data equalizer block
222: Sampler of the second unit block of the second data equalizer block
223: mux of second data block of second data equalizer block
224: DFF of the second data block of the second data equalizer block
300: first edge equalizer block
310: first unit block of the first edge equalizer block
311: adder of first unit block of first edge equalizer
311-1: First-first switched capacitor of the adder of the first edge equalizer block first unit block
311-2: 1-2-2 switched capacitor of the adder of the first unit of the first edge equalizer block
312: Sampler of the first unit block of the first edge equalizer block
313: mux of the first unit block of the first edge equalizer
314: DFF of the first edge equalizer block first unit block
320: second unit block of the first edge equalizer block
321: Adder of the first edge equalizer block second unit block
321-1: First-first switched capacitor of adder of first edge equalizer block second unit block
321-2: 1-2 switched capacitor of the adder of the second unit block of the first edge equalizer block
322: Sampler of the first edge equalizer block second unit block
323: mux of the first edge equalizer block second unit block
324: DFF of the first edge equalizer block second unit block
400: second edge equalizer block
410: First unit block of the second edge equalizer block
411: Adder of first unit block of second edge equalizer block
411-1: First-first switched capacitor of the adder of the second edge equalizer block first unit block
411-2: 1-2 switched capacitor of the adder of the first unit block of the second edge equalizer block
412: Sampler of the first unit block of the second edge equalizer block
413: mux of the first unit block of the second edge equalizer block
414: DFF of the first unit block of the second edge equalizer block
420: second unit block of the second edge equalizer block
421: Adder of second edge equalizer block second unit block
421-1: First-first switched capacitor of adder of second edge equalizer block second unit block
421-2: 1-2 switch capacitor of the adder of the second unit block of the second edge equalizer block
422: Sampler of the second unit block of the second edge equalizer block
423: mux of the second edge equalizer block second unit block
424: DFF of the second edge equalizer block second unit block

Claims (26)

In the decision feedback equalizer block for a receiver of a voltage mode driver,
An adder for removing the offset from the input signal;
A sampler connected to the adder to output a sample signal for an input signal;
A mux connected to the sampler to select a final sample signal among sample signals output by the sampler according to a determination result signal; And
Equalizer unit block including the DFF connected to the mux
A decision feedback equalizer block for use in a receiver of a voltage mode driver, comprising a first unit block and a second unit block. The method of claim 1,
And the adder comprises two switched capacitors. The method of claim 2,
The adder of the first unit block is
a 1-1 switched capacitor that outputs (poutn1) the result of ((vcm1) + (VCM2 + CV)-(INN)), and
a 1-2 switched capacitor which outputs (poutp1) the result of ((vcm1) + (VCM2-CV)-(INP)),
The adder of the second unit block is
a 2-1 switched capacitor which outputs (noutn1) the result of ((vcm1) + (VCM2-CV)-(INN)), and
A decision feedback equalizer block for use in the receiver of a voltage mode driver, comprising a 2-2 switched capacitor for outputting (noutp1) the result of ((vcm1) + (VCM2 + CV)-(INP)). .
(VCM1 is the first input voltage value, VCM2 is the second input voltage value, CV is the control voltage value, INN is the negative input signal value, and INP is the positive input signal value.) The method of claim 3,
The adder of the first unit block and the adder of the second unit block have a control voltage value (CV) such that a probability of 0 and 1 is 0.5 in the capacitor negative output value or the capacitor positive output value, respectively, under the condition that INN and INP are the same value. The decision feedback equalizer block used in the receiver of the voltage mode driver, characterized in that for performing an offset by changing the. In a receiver using a decision feedback equalizer,
An equalizer including an adder for removing an offset from an input signal, a sampler for outputting a sample signal for the input signal, a mux and a DFF for selecting a final sample signal among sample signals output by the sampler according to a first data determination result signal Unit Blocks
A first data equalizer block comprising a first unit block and a second unit block;
An equalizer including an adder for removing an offset from an input signal, a sampler for outputting a sample signal for the input signal, a mux and a DFF for selecting a final sample signal among sample signals output by the sampler according to a first edge determination result signal Unit Blocks
A first edge equalizer block comprising a first unit block and a second unit block;
An adder for removing an offset from an input signal, a sampler for outputting a sample signal for the input signal, a mux for selecting a final sample signal among sample signals output by the sampler according to a second data determination result signal, and a connected DFF Equalizer Unit Block In
A second data equalizer block including a first unit block and a second unit block; And
An equalizer including an adder for removing an offset from an input signal, a sampler for outputting a sample signal for the input signal, a mux and a DFF for selecting a final sample signal among sample signals output by the sampler according to a second edge determination result signal Unit Blocks
And a second edge equalizer block comprising a first unit block and a second unit block. The method of claim 5,
The first data equalizer block, the first edge equalizer block, the second data equalizer block and the second edge equalizer block are
An offset elimination mode for removing an offset through an adder included in each equalizer block, and
An equalization mode that performs data equalization through the first data equalizer block and the second data equalizer block, and performs edge equalization through the first edge equalizer block and the second edge equalizer block. And a receiver using a decision feedback equalizer. The method of claim 5,
And the adder of the first unit block and the adder of the second unit block include two switched capacitors. The method of claim 7, wherein
The adder of the first unit block in the offset cancellation mode
a 1-1 switched capacitor that outputs (poutn1) the result of ((vcm1) + (VCM2 + CV)-(INN)), and
a 1-2 switched capacitor which outputs (poutp1) the result of ((vcm1) + (VCM2-CV)-(INP)),
The adder of the second unit block is
a 2-1 switched capacitor that outputs (noutn1) the result of ((vcm1) + (VCM2 + CV)-(INN)), and
a 2-2 switched capacitor that outputs (noutp1) the result of ((vcm1) + (VCM2-CV)-(INP)),
The control voltage value CV may have a different value for each of the first data equalizer block, the second data equalizer block, the first edge equalizer block, and the second edge equalizer block. Receiver using equalizer.
(VCM1 is the first input voltage value, VCM2 is the second input voltage value, CV is the control voltage value, INN is the negative input signal value, and INP is the positive input signal value.) The method of claim 8,
The adder of the first unit block and the adder of the second unit block have a control voltage value (CV) such that the probability of 0 and 1 is 0.5 in the capacitor negative output value or the capacitor positive output value, respectively, under the condition that INN and INP are the same value. A receiver using the decision feedback equalizer, characterized in that for performing an offset mode. 10. The method of claim 9,
The first clock value and the third clock value are input to the adder of the first data equalizer block, the second clock value is input to the sampler of the first data equalizer block, and the second clock value is input to the DFF of the first data equalizer block. The clock value is entered.
The second clock value and the fourth clock value are input to the adder of the first edge equalizer block, the third clock value is input to the sampler of the first edge equalizer block, and the third clock value is input to the DFF of the first edge equalizer block. The clock value is entered.
The third clock value and the first clock value are input to the adder of the second data equalizer block, the fourth clock value is input to the sampler of the second data equalizer block, and the fourth clock value is input to the DFF of the second data equalizer block. The clock value is entered.
The fourth clock value and the second clock value are input to the adder of the second edge equalizer block, the first clock value is input to the sampler of the second edge equalizer block, and the first clock value is input to the DFF of the second edge equalizer block. A receiver using a decision feedback equalizer, characterized in that a clock value is input. The method of claim 10,
The adder of the first data equalizer block in the equalization mode uses the switched capacitor,
In the first-first switched capacitor, when the first clock value is 0 and the third clock value is 1, VCM1 is output to the sampler of the first data equalizer block, and the first clock value is 1 and the third clock value. If 0, the value (VCM1 + VCM2-INN + tap weight (a1)) is output.
In the 1-2 switched capacitor, when the first clock value is 0 and the third clock value is 1, VCM1 is output to the sampler of the first data equalizer block, and the first clock value is 1 and the third clock value. If 0, the value (VCM1 + VCM2-INP-tap weight (a1)) is output.
When the first clock value is 0 and the third clock value is 1 in the 2-1 switched capacitor, VCM1 is output to the sampler of the first data equalizer block, and the first clock value is 1 and the third clock value is set. If 0, (VCM1 + VCM2-INN-tap weight value (a1)) is output.
In the 2-2 switched capacitor, when the first clock value is 0 and the third clock value is 1, VCM1 is output to the sampler of the first data equalizer block, and the first clock value is 1 and the third clock value. If 0, (VCM1 + VCM2-INP + tap weight value a1) is output. The receiver using the decision feedback equalizer, characterized in that the output. The method of claim 11,
The tap weight a1 is determined as a value obtained by adding a weight control value a''1 to a voltage control value CV and a'1 determined in the offset mode of the first data equalizer block.
a''1 is equal to the weight control value (a''2) of the second data equalizer block such that data ISI is removed. The method of claim 10,
In the equalization mode, the adder of the second data equalizer block uses the switched capacitor,
In the first-first switched capacitor, when the third clock value is 0 and the first clock value is 1, VCM1 is output to the sampler of the second data equalizer block, the third clock value is 1, and the first clock is If the value is 0, (VCM1 + VCM2-INN + tap weight value (a2)) is output.
In the 1-2 switched capacitor, when the third clock value is 0 and the first clock value is 1, the VCM1 is output to the sampler of the second data equalizer block, the third clock value is 1, and the first clock. If the value is 0, (VCM1 + VCM2-INP-tap weight value (a2)) is outputted.
In the 2-1 switched capacitor, when the third clock value is 0 and the first clock value is 1, the VCM1 is output to the sampler of the second data equalizer block, the third clock value is 1, and the first clock is If the value is 0, (VCM1 + VCM2-INN-tap weight value (a2)) is outputted.
In the 2-2 switched capacitor, when the third clock value is 0 and the first clock value is 1, VCM1 is output to the sampler of the second data equalizer block, the third clock value is 1, and the first clock is If the value is 0, (VCM1 + VCM2-INP + tap weight value (a2)) is output, the receiver using a decision feedback equalizer. The method of claim 13,
The tap weight a2 is determined as a value obtained by adding the weight control value a''2 to the voltage control values CV and a'2 determined in the offset mode of the two data equalizer blocks.
a''2 is equal to the weight control value (a''1) of the first data equalizer block such that data ISI is removed. The method of claim 10,
In the equalization mode, the adder of the first edge equalizer block uses the switched capacitor,
If the second clock value is 0 and the fourth clock value is 1 in the 1-1 switched capacitor, VCM1 is output to the sampler of the first edge equalizer block, and the second clock value is 1 and the fourth clock value is If 0, (VCM1 + VCM2-INN + tap weight value (b1)) is outputted,
When the second clock value is 0 and the fourth clock value is 1 in the 1-2 switched capacitor, VCM1 is output to the sampler of the first edge equalizer block, and the second clock value is 1 and the fourth clock value is If 0, (VCM1 + VCM2-INP-tap weight value (b1)) is output.
When the second clock value is 0 and the fourth clock value is 1 in the 2-1 switched capacitor, VCM1 is output to the sampler of the first edge equalizer block, and the second clock value is 1 and the fourth clock value is If 0, (VCM1 + VCM2-INN-tap weight value (b1)) is outputted,
When the second clock value is 0 and the fourth clock value is 1 in the 2-1 switched capacitor, VCM1 is output to the sampler of the first edge equalizer block, and the second clock value is 1 and the fourth clock value is If 0, (VCM1 + VCM2-INP + tap weight value (b1)) is output, the receiver using the decision feedback equalizer. The method of claim 13,
The tap weight b1 is determined as a value obtained by adding the weight control value b''1 to the voltage control values CV and b'2 determined in the offset mode of the first edge equalizer block.
b''1 is equal to the weight control value (b''2) of the second edge equalizer block such that edge ISI is removed. The method of claim 10,
The adder of the second edge equalizer block in the equalization mode uses the switched capacitor,
When the fourth clock value is 0 and the second clock value is 1 in the 1-1 switched capacitor, VCM1 is output to the sampler of the second edge equalizer block, and the fourth clock value is 1 and the second clock value is If 0, (VCM1 + VCM2-INN + tap weight value (b2)) is outputted,
When the fourth clock value is 0 and the second clock value is 1 in the 1-2 switched capacitor, VCM1 is output to the sampler of the second edge equalizer block, and the fourth clock value is 1 and the second clock value is If 0, (VCM1 + VCM2-INP- tap weight value (b2)) is output.
When the fourth clock value is 0 and the second clock value is 1 in the 2-1 switched capacitor, VCM1 is output to the sampler of the second edge equalizer block, and the fourth clock value is 1 and the second clock value is If 0, (VCM1 + VCM2-INN-tap weight value (b2)) is output.
If the fourth clock value is 0 and the second clock value is 1 in the 2-2 switched capacitor, VCM1 is output to the sampler of the second edge equalizer block, and the fourth clock value is 1 and the second clock value is If 0, (VCM1 + VCM2-INP + tap weight value (b2)) is output, the receiver using a decision feedback equalizer. The method of claim 13,
The tap weight b2 is determined as a value obtained by adding the weight control value b''2 to the voltage control values CV and b'2 determined in the offset mode of the second edge equalizer block.
b''2 is equal to the weight control value (b''1) of the first edge equalizer block such that edge ISI is removed. The method of claim 12,
The value output from the adder of the first data equalizer block is sampled by a second clock and output as two sample signals.
And a final feedback signal of the two sample signals is selected in the MUX according to the final signals (outp3, outn3) of the second data equalizer block. 15. The method of claim 14,
In the second data equalizer block, a value output from an adder is sampled by a fourth clock and output as two sample signals.
And a final feedback signal of the two sample signals is selected in the MUX according to the final signals (outp1, outn1) of the first data equalizer block. The method of claim 16,
In the first edge equalizer block, a value output from an adder is sampled by a third clock and output as two sample signals.
And a final feedback signal of the two sample signals is selected in the MUX according to the final signals (outp3, outn3) of the second data equalizer block. 19. The method of claim 18,
In the second edge equalizer block, a value output from an adder is sampled by a first clock and output as two sample signals.
And a final feedback signal of the two sample signals is selected in the MUX according to the final signals (outp1, outn1) of the first data equalizer block. The method of claim 12,
In the first data equalizer block, a value output from an adder is sampled by a second clock and output as two sample signals.
And a final feedback signal ( sel 1) of the two sample signals is selected in the mux according to the signal ( sel 3) selected in the mux of the second data equalizer block. 15. The method of claim 14,
In the second data equalizer block, a value output from an adder is sampled by a fourth clock and output as two sample signals.
And a final feedback signal ( sel 3) of the two sample signals is selected in the mux according to the signal ( sel 1) selected in the mux of the first data equalizer block. The method of claim 16,
In the first edge equalizer block, a value output from an adder is sampled by a third clock and output as two sample signals.
And a final feedback signal of the two sample signals is selected in the mux according to the signal ( sel 3) selected in the mux of the second data equalizer block. 19. The method of claim 18,
In the second edge equalizer block, a value output from an adder is sampled by a first clock and output as two sample signals.
And a final feedback signal of the two sample signals is selected in the mux according to the signal sel 1 selected in the mux of the first data equalizer block.

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