KR101131221B1 - Receiving system receving radio frequency signal to convert into baseband signal, digital down converter and method of digital down converting - Google Patents

Abstract

The present invention relates to a receiving system for receiving a radio frequency signal and converting it into a baseband signal. The receiving system of the present invention consists of an analog-to-digital converter for digitizing a received radio frequency signal, and a digital down converter for converting the digitized signal into a baseband signal. The digital down converter downgrades the output of the digitized signal and the carrier of the digitized signal to multiply the digital sine wave corresponding to the selected carrier frequency, the first low pass filter to low pass filter the output of the multiplier, and the first low pass filter. A first decimator to sample, a second low pass filter to low pass filter the output of the first decimator, and a second decimator to downsample the output of the second low pass filter.

Description

RECEIVING SYSTEM RECEVING RADIO FREQUENCY SIGNAL TO CONVERT INTO BASEBAND SIGNAL, DIGITAL DOWN CONVERTER AND METHOD OF DIGITAL DOWN CONVERTING}

The present invention relates to a receiving system for receiving a radio frequency signal and converting it into a baseband signal, a digital down converter, and a digital down converting method.

The present invention is derived from the research conducted as part of the IT growth engine technology development project of the Korea Communications Commission [Task Management Number: 2008-S-005-02, Title: Development of IP-based ultra-high speed multimedia transmission technology in HFC network ].

A radio frequency (RF) signal represents a signal having a frequency corresponding to about 3 KHz to 300 GHz band. Radio frequency signals are used to transmit information in communication networks such as cellular telephone networks, high-speed Internet networks, digital cable broadcasting networks, and the like.

When a radio frequency signal is received, the received signal is provided to an RF tuner. In the RF tuner, the received signal is converted to a baseband signal. Thereafter, the converted baseband signal is digitized and demodulated. However, in a radio frequency reception system, the RF tuner is a major cause of increasing system complexity. Accordingly, there is a need for a method of reducing the number of RF tuners and a receiving system having a reduced number of RF tuners.

It is an object of the present invention to provide a radio frequency signal receiving system, a digital down converter, and a digital down converting method having a reduced complexity.

A reception system according to an embodiment of the present invention for receiving a radio frequency signal and converting the signal into a baseband signal comprises: an analog-digital converter for digitizing the received radio frequency signal; And a digital down converter for converting the digitized signal into a baseband signal, the digital down converter comprising: a multiplier for multiplying a digital sine wave corresponding to a selected carrier frequency of the digitized signal and carriers of the digitized signal; A first low pass filter for low pass filtering the output of the multiplier; A first decimator for downsampling the output of the first low pass filter; A second low pass filter for low pass filtering the output of the first decimator; And a second decimator for downsampling the output of the second low pass filter.
In an embodiment, the product of the first decimation rate of the first decimator and the second decimation rate of the second decimator corresponds to the down converting rate of the digital down converter.
In an embodiment, the first decimator is configured to provide a plurality of decimation rates, and one of the plurality of decimation rates is activated according to the bandwidth of the received signal.
In example embodiments, the first low pass filter is configured to provide a plurality of pass bands corresponding to a plurality of decimation rates of the first decimator, respectively, and the plurality of pass bands according to a bandwidth of the received signal. One of them is selected.
According to another embodiment of the present invention, a digital down converter includes: a first low pass filter and a decimator configured to low pass filter an input signal to a first pass band and to decimate a result of the low pass filtering at a first ratio; And a second low pass filter and a decimator configured to low pass filter the outputs of the first low pass filter and the decimator to a second pass band and to decimate at a second rate, wherein the first rate and the second rate Gives the product of as the target down-converting ratio.
In an embodiment, the first low pass filter and the decimator are configured to vary the first pass band and the first ratio according to the bandwidth of the input signal.
In an embodiment, the second low pass filter and the decimator may include at least two low pass filters and decimators connected in a chain structure.
In an embodiment, the first passband is set to prevent aliasing from occurring during decimation according to the first ratio, and the second passband is decimated according to the second ratio. It is set to prevent the occurrence of aliasing at the time.
Digital down converting method according to an embodiment of the present invention comprises the steps of receiving a target signal; And performing at least two times the low pass filtering and decimating the received target signal, wherein the product of the decimation ratios of the decimations performed at least twice corresponds to a target ratio of the digital down converting. And the pass bands of the low pass filterings performed at least twice are set to prevent the occurrence of aliasing during the decimations performed at least twice.
In exemplary embodiments, after receiving the target signal, selecting the decimation ratios of the at least two decimations performed and the passbands of the at least two low pass filterings respectively according to the bandwidth of the target signal. It further includes.

According to the present invention, the radio frequency signal is converted into a baseband signal after being digitized. Thus, there is provided a receiving system, a digital down converter, and a digital down converting method with reduced complexity by an RF tuner.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. . Identical components will be referred to using the same reference numerals. Similar components will be referred to using similar reference numerals.

1 is a block diagram showing a cable system 10 according to an embodiment of the present invention. Referring to FIG. 1, the cable system 10 includes a cable network 100, first to third receivers 200a to 200c, and a broadcasting unit 300.

The cable network 100 is a network formed based on the cable. The cable network 100 provides a channel between components connected to the cable network 100.

The first to third receivers 200a to 200c are connected to the cable network 100, respectively. The first to third receivers 200a to 200c are configured to receive content broadcast through the cable network 100 and output the received broadcast content.

The broadcast unit 300 is connected to the cable network 100. The broadcast unit 300 broadcasts broadcast content through the cable network 100. The broadcasted content is delivered to the first to third receivers 200a to 200c.

For example, the broadcasting unit 300 and the first to third receivers 200a to 200c may perform bidirectional communication. For example, the signal transmitted from the broadcasting unit 300 to the first to third receivers 200a to 200c may be a downlink signal. For example, the downlink signal may include a broadcast signal. For example, the signal transmitted from the first to third receivers 200a to 200c to the broadcasting unit 300 may be an uplink signal. For example, the uplink signal may include a channel subscription signal and a channel selection signal.

2 is a diagram showing the frequency characteristics of the channel provided by the cable network 100 of FIG. In Figure 2, the horizontal axis represents frequency and the unit is MHz. The vertical axis represents the magnitude of the signal.

2, the total bandwidth of the channel provided by the cable network 100 is shown to correspond to 5MHz to 65MHz. The total bandwidth of the channel provided by the cable network 100 may vary depending on the characteristics of the cable network 100, data transmission protocol, and the like, and is not limited to specific values.

The cable network 100 will provide a plurality of channels within the total bandwidth. For example, the first to fourth channels CH1 to CH4 are shown within the total bandwidth. However, the cable network 100 is not limited to providing the first to fourth channels CH1 to CH4.

In FIG. 2, the bandwidths of the first to fourth channels CH1 to CH4 are shown to be the same. However, the cable network 100 may provide channels with different bandwidths. For example, the bandwidth of the channel provided by the cable network 100 may be one of 5.12 MHz, 2.56 MHz, 1.28 MHz, 0.64 MHz, 0.32 MHz, and 0.16 MHz. As an example, each of the bandwidths described above will represent a symbol rate of the channel.

In exemplary embodiments, the bandwidth of the channel may be a sum of a symbol rate and a roll-off factor. For example, the roll-off factor will act as a guard band to prevent interchannel interference. For example, the roll-off factor may be defined as the ratio of symbol rate. For example, when the roll-off factor is 0.25, the bandwidth of the channel may be one of 6.4 MHz, 3.2 MHz, 1.6 MHz, 0.8 MHz, 0.4 MHz, and 0.2 MHz. In the following, the bandwidth of the channel will represent either the symbol rate or the bandwidth considering the roll-off factor.

3 is a block diagram illustrating a receiving system 400 used in the cable system 10 of FIG. For example, the reception system 400 may be a reception system of the broadcasting unit 300 or may be a reception system of each of the first to third receivers 200a to 200c. For brevity, it is assumed that the reception system 400 of FIG. 3 is a reception system of an uplink signal. That is, it is assumed that the reception system 400 is a reception system of the broadcast unit 300.

Referring to FIG. 3, the reception system 400 includes an amplifier 410, an analog to digital (AD) converter 420, first to m th digital downconverters 500_1 to 500_m, and first to m th match filters. 430_1 to 430_m, first to mth tuner and demodulators 440_1 to 440_m, and first to mth channel decoders 450_1 to 450_m.

The amplifier 410 receives a radio frequency (RF) signal from the cable network 100. Amplifier 410 amplifies the received radio frequency (RF) signal. The amplified radio frequency (RF) signal is passed to the AD converter 420.

AD converter 420 digitizes a radio frequency (RF) signal received from amplifier 410. For example, the AD converter 420 samples the received radio frequency (RF) signal based on a preset sampling rate. The output signal of the AD converter 420 is called a sample signal s [n]. In exemplary embodiments, the AD converter 420 may further perform quantization. In this case, the sample signal s [n] may be a signal obtained by sampling and quantizing a radio frequency (RF) signal.

In FIG. 2, it is assumed that the total bandwidth supported by the cable network 100 corresponds to 5 MHz to 65 MHz. If the sampling rate Fs of the AD converter 420 is 130 MHz or more, aliasing will be prevented. For example, assume that the sampling rate Fs of the AD converter is 163.84 MHz.

The first to m th digital down converters 500_1 to 500_m receive the output s [n] of the AD converter 420. In exemplary embodiments, the first to m th digital down converters 500_1 to 500_m may correspond to channels supported by the cable network 100, respectively. For example, when the first to fourth channels CH1 to CH4 are provided in the cable network 100, the first to fourth digital downconverters 500_1 to 500_4 may be provided to the reception system 400. will be.

In exemplary embodiments, the first digital down converter 500_1 extracts a signal including a signal component corresponding to the first channel CH1 of the received sample signal s [n]. In exemplary embodiments, the first digital down converter 500_1 extracts a signal including a signal component corresponding to the first channel CH1 as a baseband signal. In exemplary embodiments, the first digital down converter 500_1 may further perform an operation of downsampling the sample signal s [n] to reduce the amount of information. That is, the first digital down converter 500_1 corresponds to the first channel CH1 and outputs a baseband signal having a reduced amount of information than the sample signal s [n]. For example, the output signal of the first digital down converter 500_1 may include adjacent channel components other than the first channel CH1 component.

Similarly, the i-th digital down converter 500_i may output a baseband signal corresponding to the i-th channel CHi and having a reduced amount of information than the sample signal s [n]. In exemplary embodiments, the output signal of the i-th digital down converter 500_i may include adjacent channel components other than the i-th channel CHi component.

The first to m th match filters 430_1 to 430_m respectively receive outputs of the first to m th digital downconverters 500_1 to 500_m. Each of the first to m th match filters 430_1 to 430_m may filter channel components that do not match the corresponding channel from the received signal. For example, the i th match filter 430_i may remove channel components other than the i th channel CHi from the received signal. In addition, each of the first to m th match filters 430_1 to 430_m may suppress and output noise of a received signal. For example, the first to m th match filters 430_1 to 430_m may be square root raised cosine (SRRC) filters.

The first to m th sync and demodulators 440_1 to 440_m respectively receive outputs of the first to m th match filters 430_1 to 430_m. Each of the first to m th synchronization and demodulators 440_1 to 440_m performs synchronization and demodulation of the received signal.

The first to m th channel decoders 450_1 to 450_m respectively receive outputs of the first to m th synchronization and demodulators 440_1 to 440_m. Each of the first to m th channel decoders 450_1 to 450_m may channel decode the received signal.

As described above, the radio frequency (RF) signal received from the cable network 100 is digitized and converted into baseband signals by the first to mth digital downconverters 500_1 to 500_m. Since no RF tuner is required at the receiving system 400, the system complexity of the receiving system 400 is reduced.

For example, the amplifier 410, the AD converter 420, the first to mth match filters 430_1 to 430_m, the first to mth sync and demodulators 440_1 to 440_m, and the first to mth The channel decoders 450_1 to 450_m may be components known to those having ordinary skill in the art.

FIG. 4 is a block diagram illustrating one of the first to m th digital down converters 500_1 to 500_m of FIG. 3. Referring to FIG. 4, the digital down converter 500_k includes a numerically controlled oscillator 510 (NCO, Numerically Controlled Oscillator), a phase shifter 520, first and second multipliers 530 and 540, first and second Switches 550, 560, quadrature signal processor 570, and in-phase signal processor 580.

For example, it is assumed that the digital down converter 500_k corresponds to the fourth channel CH4. It is assumed that the carrier frequency of the fourth channel CH4 is 40.96 MHz. However, the channel and carrier frequency corresponding to the digital down converter 500_k are not limited.

The numerically controlled oscillator 510 is configured to generate a sinusoidal wave (eg, digital sinusoidal wave) having a preset frequency. For example, the numerically controlled oscillator 510 will generate a sinusoidal wave (eg, a digital sinusoidal wave) corresponding to the frequency of a carrier wave of the received sample signal s [n]. By way of example, since the carrier frequency of the fourth channel CH4 is 40.96 MHz, the numerically controlled oscillator 510 will generate a sine wave (eg, digital sine wave) having a frequency of 40.96 MHz. The generated sinusoidal wave (eg, digital sinusoidal wave) is passed to the second multiplier 540 and the phase converter 520.

Phase converter 520 receives a sinusoidal wave (eg, a digital sinusoidal wave) from numerically controlled oscillator 510. Phase converter 520 converts the phase of the received sinusoidal wave (eg, a digital sinusoidal wave). For example, phase converter 520 converts the phase of the received sinusoid (eg, digital sinusoid) by 90 degrees. For example, phase converter 520 delays the phase of the received sinusoid (eg, digital sinusoid) by 90 degrees. The phase-converted sinusoidal wave (eg, digital sinusoidal wave) is delivered to the first multiplier 530.

The first multiplier 530 multiplies the sample signal s [n] and the phase shifted sinusoid (eg, digital sinusoid). The second multiplier 540 multiplies the sample signal s [n] and a sinusoidal wave (eg, a digital sinusoidal wave). That is, the first multiplier 530 converts the sample signal s [n] such that the fourth channel CH4 component of the sample signal s [n] corresponds to the base band, and the quadrature phase ( Output quadrature phase components. The output of the first multiplier 530 is called a quadrature phase shift signal Q1 [n].

The second multiplier 540 converts the sample signal s [n] such that the fourth channel CH4 component of the sample signal s [n] corresponds to the base band, and in-phase of the converted signal (in−). phase) Outputs the component. The output of the second multiplier 540 is called an in-phase transition signal I1 [n]. Quadrature phase shift signal Q1 [n] and in-phase shift signal I1 [n] are transmitted to first and second switches 550 and 560, respectively.

Each of the first and second switches 550 and 560 switches a signal transmission path according to the bandwidth of the fourth channel CH4. The switching operation of the first and second switches 550 and 560 is described in more detail with reference to quadrature phase signal processor 570 and in-phase signal processor 580.

The quadrature phase signal processor 570 receives the quadrature phase shift signal Q1 [n] through the first switch 550. Quadrature phase signal processor 570 includes first to third low pass filters 571 to 573, and first to third decimators 574 to 576.

The first low pass filter 571 has a pass band corresponding to Fs / 8, and the first decimator 574 performs 1/8 downsampling. The second low pass filter 572 has a pass band corresponding to Fs / 16, and the second decimator 575 performs 1/16 downsampling. The third low pass filter 573 has a pass band corresponding to Fs / 32, and the third decimator 576 performs 1/32 downsampling.

The quadrature phase signal processor 570 removes unnecessary information from the received signal Q1 [n]. For example, quadrature phase signal processor 570 performs downsampling.

The bandwidth of the fourth channel CH4 may be one of 5.12 MHz, 2.56 MHz, 1.28 MHz, 0.64 MHz, 0.32 MHz, and 0.16 MHz. By the way, the sampling rate Fs of the quadrature phase shift signal Q1 [n] is set to 163.84 MHz. Compared with the bandwidth of the fourth channel CH4, the sampling rate Fs is very high.

By adjusting the appropriate sampling rate Fs according to the bandwidth of the fourth channel CH4, it is possible to reduce the sampling rate Fs while maintaining the fourth channel CH4 information. When the sampling rate Fs is reduced, the amount of data computation of the digital signal processing circuit can be reduced. That is, while maintaining the fourth channel CH4 information, the amount of data computation can be reduced.

For example, it is assumed that in the fourth channel CH4, the sampling rate Fs is adjusted to 4 samples per symbol. However, the sampling rate Fs is not limited to being adjusted to 4 samples per symbol.

If the sampling rate Fs is adjusted to 4 samples per symbol when the bandwidth of the fourth channel CH4 is 5.12 MHz, the adjusted sampling rate Fs' corresponds to 5.12 * 4 MHz, i.e. 20.48 MHz. That is, the sampling rate Fs is adjusted from 163.84 MHz to 20.48 MHz, which is 1/8. In this case, aliasing may occur due to components higher than 20.48 MHz among frequency components of the original signal (for example, the quadrature phase shift signal Q1 [n]). Thus, before downsampling is performed, low pass filtering with a pass band equal to or lower than 20.48 MHz is performed.

When the bandwidth of the fourth channel CH4 corresponds to 5.12 MHz, the first switch 550 selects the first low pass filter 571. The first low pass filter 571 performs low pass filtering with a pass band of Fs / 8, that is, 20.48 MHz. The output Q2 [n] of the first low pass filter 571 is delivered to a first decimator 574. The first decimator 574 downsamples the received signal by one eighth. That is, the first decimator 574 outputs a signal Q5 [n] having a sampling rate of 20.48 MHz corresponding to four samples per symbol.

The bandwidth of the output signal Q5 [n] of the first decimator 564 is 20.48 MHz. The bandwidth of the fourth channel CH4 is 5.12 MHz. Therefore, the output signal Q5 [n] may include a component of the fourth channel CH4 and a component of another adjacent channel. The output signal Q5 [n] is passed to the match filter 430_k. Components of other adjacent channels will be removed by match filter 430_k.

When the bandwidth of the fourth channel CH4 corresponds to 2.56 MHz, the first switch 550 selects the second low pass filter 572. The second low pass filter 572 performs low pass filtering with a pass band of Fs / 16, that is, 10.24 MHz. Output Q3 [n] of second low pass filter 572 is passed to a second decimator 575. The second decimator 575 downsamples the received signal 1/16. That is, the second decimator 575 outputs a signal Q6 [n] having a sampling rate of 10.24 MHz corresponding to four samples per symbol.

The bandwidth of the output signal Q6 [n] of the second decimator 565 is 10.24 MHz. The bandwidth of the fourth channel CH4 is 2.56 MHz. Accordingly, the output signal Q6 [n] may include a component of the fourth channel CH4 and a component of another adjacent channel. The output signal Q6 [n] is passed to the match filter 430_k. Components of other adjacent channels will be removed by match filter 430_k.

When the bandwidth of the fourth channel CH4 corresponds to 1.28 MHz, the first switch 550 selects the third low pass filter 573. The third low pass filter 573 performs low pass filtering with a pass band of Fs / 32, that is, 5.12 MHz. The output Q4 [n] of the third low pass filter 573 is delivered to a third decimator 576. The third decimator 576 downsamples the received signal 1/32. That is, the third decimator 576 outputs a signal Q7 [n] having a sampling rate of 5.12 MHz corresponding to four samples per symbol.

The bandwidth of the output signal Q7 [n] of the third decimator 576 is 5.12 MHz. The bandwidth of the fourth channel CH4 is 1.28 MHz. Accordingly, the output signal Q7 [n] may include a component of the fourth channel CH4 and a component of another adjacent channel. The output signal Q7 [n] is passed to the match filter 430_k. Components of other adjacent channels will be removed by match filter 430_k.

In exemplary embodiments, the outputs Q5 [n], Q6 [n], and Q7 [n] of the quadrature signal processor 570 may be transferred to a switch circuit (not shown). The switch circuit will be configured to select the same signal path as the signal path selected by the first switch 500. And, the output from the selected signal path will be passed to the match filter 430_k.

The in-phase signal processor 580 is configured in the same manner as the quadrature phase signal processor 570 except for receiving an in-phase transition signal I1 [n]. The first low pass filter 581 and the first decimator 584 of the in-phase signal processor 580 correspond to the first low pass filter and the first decimator 574 of the quadrature phase signal processor 570. The second low pass filter 582 and the second decimator 585 of the in-phase signal processor 580 are coupled to the second low pass filter 572 and the second decimator 575 of the quadrature phase signal processor 570. Corresponds. In addition, the third low pass filter 583 and the third decimator 586 of the in-phase signal processor 580 may include the third low pass filter 573 and the third decimator 576 of the quadrature phase signal processor 570. ) Therefore, detailed description of the in-phase signal processor 580 is omitted.

As described above, the digital down converter 500_k converts the selected channel component among the channel components of the sample signal s [n] into a baseband signal. Each baseband signal is then adjusted to have a lower sampling rate than the sample signal s [n]. Thus, the amount of computation of the digital processing circuit can be reduced by corresponding to the reduced sampling rate.

In FIG. 4, quadrature signal processor 570 and in-phase signal processor 580 are shown as having low pass filters and decimators corresponding to three bandwidths, respectively. However, depending on the bandwidth that a corresponding channel (eg, CH4) may have, the number of lowpass filters and decimators of quadrature downconverter 570 and in-phase signal processor 580 may be adjusted. .

In exemplary embodiments, when a bandwidth of 0.64 MHz is additionally supported for a corresponding channel (eg, CH4), each of the quadrature signal processor 570 and the in-phase signal processor 580 may provide a bandwidth corresponding to Fs / 64. It will further include a low pass filter having a decimator to perform 1/64 downsampling. When a bandwidth of 0.32 MHz is additionally supported for the corresponding channel (eg, CH4), each of the quadrature signal processor 570 and in-phase signal processor 580 has a low pass filter having a bandwidth corresponding to Fs / 128. And a decimator to perform 1/128 downsampling. When a bandwidth of 0.16 MHz is additionally supported for the corresponding channel (e.g., CH4), each of the quadrature signal processor 570 and in-phase signal processor 580 has a low pass filter having a bandwidth corresponding to Fs / 256. And a decimator to perform 1/256 downsampling.

5 is a block diagram illustrating a quadrature phase signal processor 670 according to a second embodiment of the present invention. Referring to FIG. 5, the quadrature phase signal processor 670 includes a first filter unit 671, a first decimator unit 673, a second filter unit 675, and a second decimator unit 677. do.

Illustratively, quadrature phase signal processor 670 is shown corresponding to bandwidths of 0.64 MHz, 0.32 MHz, and 0.16 MHz. For example, a signal path consisting of a 1a low pass filter F1a, a 1a decimator D1a, a 1b low pass filter F1b, and a 1b decimator D1b may correspond to a bandwidth of 0.64 MHz. will be. The signal path consisting of the 2a low pass filter F2a, the 2a decimator D2a, the 2b low pass filter F2b, and the 2b decimator D2b will correspond to a bandwidth of 0.32 MHz. The signal path consisting of the third a low pass filter F3a, the third a decimator D3a, the third b low pass filter F3b, and the third b decimator D3b will correspond to a bandwidth of 0.16 MHz.

As an example, the signal received by quadrature signal processor 670 will be converted to have 4 samples per symbol.

If the bandwidth of the fourth channel CH4 corresponds to 0.16 MHz, the sampling rate adjusted to have 4 samples per symbol would be 0.64 MHz. That is, 1/256 downsampling will be performed. In order to prevent aliasing, Fs / 256, i.e. 0.64 MHz low pass filtering will be performed before 1/256 downsampling is performed. 0.64MHz lowpass filtering requires a very high number of filter taps. As an example, a 0.64 MHz low pass filter would have 10362 taps.

In order to prevent the complexity of the filter from increasing due to the high number of taps, a multistage filtering and downsampling method and apparatus are provided. For example, in FIG. 5, two decimations are performed on the input signal. The sampling rate of the input signal is called Fs, and the sampling rate of the first decimated signal is called Fs'.

By the third decimator D3a, the input signal is 1/16 downsampled. The sampling rate of the downsampled signal is Fs' (e.g., Fs / 16). Since Fs / 16 low pass filtering is performed by the 3a low pass filter F3a before downsampling, aliasing is prevented.

Thereafter, 1/16 downsampling is performed by the third b decimator D3b. Since Fs' / 16 low pass filtering is performed by the third b low pass filter F3b before downsampling, aliasing is prevented.

It is to be understood that when downsampling of the 3a decimator D3a and the 3b decimator D3b is combined, 1/256 downsampling is performed by the 3a decimator D3a and the 3b decimator D3b. Can be. Alising due to 1/256 downsampling is prevented by a 3a low pass filter F3a with a pass band of Fs / 16 and a 3b low pass filter F3b with a pass band of Fs' / 16. do.

The third a low pass filter F3a having a pass band of Fs / 16 and the third b low pass filter F3b having a pass band of Fs' / 16 may be implemented with 648 taps. That is, the sum of the number of taps of the 3a and 3b low pass filters F3a and F3b is 1296. Compared to the number of taps 10362 of the low pass filter having a bandwidth of Fs / 256, that is, 0.64 MHz, the sum of the number of taps of the third and third low pass filters F3a and F3b is much smaller. Thus, the total complexity of the low pass filters is greatly reduced.

As described above, according to the present invention, low pass filtering and downsampling are performed in stages. Thus, the complexity of the low pass filters is reduced. In the above-described embodiment, low pass filtering and down sampling have been described as being performed in two steps, respectively. However, low pass filtering and down sampling are not limited to being performed in two steps, respectively. For example, low pass filtering and down sampling can be performed in at least three steps.

Similarly, when the bandwidth of the fourth channel CH4 corresponds to 0.32 MHz, the second a low pass filter F2a having a bandwidth of Fs / 8, the second a decimator D1a performing F / 8 downsampling, and the Fs A second b lowpass filter F2b having a bandwidth of '/ 16, and a second b decimator D2b performing 1/16 downsampling are selected. A total of 1/128 downsampling is performed by the 2a and 2b decimators D2a and D2b, and Fs / 128, or 1.28 MHz, by the 2a decimator D2a and the 2b low pass filter F2b. Downsampling with a bandwidth of is performed. Thus, a signal having 4 samples per symbol and unaffected by aliasing is output.

When the bandwidth of the fourth channel CH4 corresponds to 0.64 MHz, the first a low pass filter F1a having a bandwidth of Fs / 8, the first a decimator D1a performing 1/8 downsampling, and Fs' / A first b lowpass filter F1b having a bandwidth of eight and a first b decimator D1b performing 1/8 downsampling are selected. A total of 1/64 downsampling is performed by the 1a and 1b decimators D1a and D1b, and the Fs / 64, i.e., 2.56 MHz, by the 1a decimator D1a and the 1b low pass filter F1b. Downsampling with a bandwidth of is performed. Thus, a signal having 4 samples per symbol and unaffected by aliasing is output.

In exemplary embodiments, the outputs of the quadrature signal processor 670 may be delivered to a switch circuit (not shown). The switch circuit will be configured to select the same signal path as the signal path selected by the first switch 500. And, the output from the selected signal path will be passed to the match filter 430_k.

As described with reference to FIG. 4, the quadrature signal processor 570 and the in-phase signal processor 580 are configured in the same manner. Thus, quadrature phase illustratively, when in-phase transition signal I1 [n] is input to quadrature phase signal processor 670, quadrature phase signal processor 670 will operate as an in-phase signal processor.

6 is a block diagram illustrating a quadrature phase signal processor 770 according to a third embodiment of the present invention. Referring to FIG. 6, the quadrature signal processor 770 includes a decimator unit including a first low pass filter 771, a first switch 772, and first to third decimators 774 to 776. 773, a second switch 777, a second low pass filter 778, and a fourth decimator 779.

The first low pass filter 771 has a pass band corresponding to Fs / 8, that is, 20.48 MHz. Since Fs / 8 low pass filtering is performed in the first low pass filter 771, aliasing will not occur even if 1/8 or less downsampling is performed after the first low pass filter 771.

The first switch 772 selects one of the first to third decimators 774 to 776 according to the bandwidth of the fourth channel CH4. In exemplary embodiments, when the bandwidth of the output of the fourth channel CH4 is 5.12 MHz, 2.56 MHz, and 1.28 MHz, the first switch 772 may select the first to third decimators 774 to 776, respectively. Will choose.

The first decimator 774 downsamples the filtered signal S1 [n] by half. The grand sampled signal S2 [n] is transmitted to the second switch 777. The second decimator 775 downsamples the filtered signal S1 [n] by a quarter. The downsampled signal S3 [n] is passed to the second switch 777. The third decimator 776 downsamples the filtered signal S1 [n] by one eighth. The downsampled signal S4 [n] is passed to the second switch 777.

The second switch 777 selects one of the outputs S2 [n] to S4 [n] of the first to third decimators 774 to 776. For example, the second switch 777 will select the decimator selected by the first switch 772. The selected signal S5 [n] is passed to the second low pass filter 778.

The second low pass filter 778 filters the selected signal S5 [n] into the pass band of Fs' / 4. Therefore, even if downsampling of 1/4 or less is performed at the rear end of the second low pass filter 778, aliasing does not occur.

Considering the downsampling rate 1/2 of the first decimator 774, the second low pass filter 778 will be understood to filter the filtered signal S1 [n] to Fs / 8, i.e. 20.48 MHz. Can be. Considering the downsample rate 1/4 of the second decimator 774, the second low pass filter 778 may be understood to filter the filtered signal S1 [n] to Fs / 16, i.e., 10.24 MHz. Can be. Considering the downsampling rate 1/8 of the third decimator 774, the second low pass filter 778 may be understood to filter the filtered signal S1 [n] to Fs / 32, i.e., 5.12 MHz. Can be. That is, by varying the decimation rate of the decimator unit 773, an effect such that the pass band of the second low pass filter 778 is variable can be obtained. Thus, multiple filters are not required for quadrature signal processor 770. In addition, the taps (or number of taps) of the filters can be maintained even if the bandwidth of the corresponding channel (eg CH4) varies.

The fourth decimator 779 downsamples the filtered signal S6 [n] 1/4. The downsampled signal has 4 samples per symbol. The downsampled signal S7 [n] is passed to the match filter 430_k.

FIG. 7 is a table illustrating operating characteristics of the quadrature signal processor 700 of FIG. 6. 6 and 7, when the symbol rate of the corresponding channel (e.g., CH4) is 5.12 MHz, the bandwidth of the channel is set to 6.4 MHz. When the symbol rate of the channel is 5.12 MHz, the first and second switches 772 and 777 select the first decimator 774.

For example, the bandwidth of the channel is a bandwidth having a roll-off factor added to the symbol rate. The first low pass filter 771 performs Fs / 8 filtering. The first decimator 774 performs half downsampling. The second low pass filter 778 performs Fs' / 4 filtering. If the downsampling rate 1/2 of the first decimator 774 is reflected, it is understood that the second low pass filter 778 performs Fs / 8 filtering. The fourth decimator 779 performs 1/4 decimation.

Fs / 8, or 20.48 MHz, filtering is performed by the first low pass filter 771, and Fs / 8, or 20.48 MHz, filtering is performed by the second low pass filter 778. That is, when the first decimator 774 is selected, low pass filtering with a bandwidth of 20.48 MHz is performed.

Half downsampling is performed by the first decimator 774 and quarter decimation is performed by the fourth decimator 779. That is, when the first decimator 774 is selected, the quadrature phase signal processor 770 outputs a signal having a sampling rate of Fs / 8, that is, 20.48 MHz. Since Fs / 8 low pass filtering is performed before 1/8 downsampling is performed, the output signal is not affected by aliasing and has 4 samples per symbol.

When the symbol rate of the corresponding channel (e.g., CH4) is 2.56 MHz, the bandwidth of the channel is set to 3.2 MHz. When the symbol rate of the channel is 2.56 MHz, the first and second switches 772 and 777 select the second decimator 775.

The first low pass filter 771 performs Fs / 8 filtering. The second decimator 775 performs quarter downsampling. The second low pass filter 778 performs Fs' / 4 filtering. If the downsampling rate 1/4 of the second decimator 775 is reflected, it is understood that the second low pass filter 778 performs Fs / 16 filtering. The fourth decimator 779 performs 1/4 decimation.

Fs / 8, or 20.48 MHz, filtering is performed by the first low pass filter 771, and Fs / 16, that is, 10.24 MHz, filtering is performed by the second low pass filter 778. That is, when the first decimator 774 is selected, low pass filtering with a bandwidth of 10.24 MHz is performed.

Quarter downsampling is performed by the first decimator 774 and quarter decimation is performed by the fourth decimator 779. That is, when the first decimator 774 is selected, the quadrature phase signal processor 770 outputs a signal having a sampling rate of Fs / 16, that is, 10.24 MHz. Since Fs / 16 low pass filtering is performed before 1/16 downsampling is performed, the output signal is not affected by aliasing and has 4 samples per symbol.

When the symbol rate of the corresponding channel (e.g., CH4) is 1.28 MHz, the bandwidth of the channel is set to 1.6 MHz. When the symbol rate of the channel is 1.28 MHz, the first and second switches 772 and 777 select the third decimator 776.

The first low pass filter 771 performs Fs / 8 filtering. The third decimator 776 performs 1/8 downsampling. The second low pass filter 778 performs Fs' / 4 filtering. When the downsampling rate 1/8 of the third decimator 775 is reflected, it is understood that the second low pass filter 778 performs Fs / 32 filtering. The fourth decimator 779 performs 1/4 decimation.

Fs / 8, or 20.48 MHz, filtering is performed by the first low pass filter 771, and Fs / 32, or 5.12 MHz filtering, is performed by the second low pass filter 778. That is, when the first decimator 774 is selected, low pass filtering with a bandwidth of 5.12 MHz is performed.

1/8 downsampling is performed by the first decimator 774 and quarter decimation is performed by the fourth decimator 779. That is, when the first decimator 774 is selected, the quadrature phase signal processor 770 outputs a signal having a sampling rate of Fs / 32, that is, 5.12 MHz. Since Fs / 32 low pass filtering is performed before 1/32 downsampling is performed, the output signal is not affected by aliasing and has 4 samples per symbol.

As described above, according to the present invention, radio frequency (RF) signals are digitized. The target channel component of the channel components of the digitized signal is converted into a baseband signal. Frequency components other than the target channel component are filtered out. And, the sampling rate is adjusted as corresponding to the reduced amount of information. Accordingly, various types of digital downconverters having low complexity are provided.

In the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope and spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the claims of the following.

1 is a block diagram illustrating a cable system according to an exemplary embodiment of the present invention.

2 is a diagram showing the frequency characteristics of the channel provided by the cable network of FIG.

3 is a block diagram illustrating a receiving system used in the cable system of FIG. 1.

4 is a block diagram illustrating one of the first to m th digital downconverters of FIG. 3.

5 is a block diagram illustrating a quadrature signal processor according to a second embodiment of the present invention.

6 is a block diagram illustrating a quadrature phase signal processor according to a third embodiment of the present invention.

FIG. 7 is a table illustrating operating characteristics of the quadrature signal processor of FIG. 6.

Claims (10)

In a receiving system for receiving a radio frequency signal and converting it into a baseband signal: An analog-to-digital converter for digitizing the received radio frequency signal; And A digital down converter for converting the digitized signal into a baseband signal, The digital down converter A multiplier that multiplies a digital sine wave corresponding to a selected carrier frequency of the digitized signal and carriers of the digitized signal; A first low pass filter for low pass filtering the output of the multiplier; A first decimator for downsampling the output of the first low pass filter; A second low pass filter for low pass filtering the output of the first decimator; And A second decimator for downsampling the output of the second low pass filter, The first low pass filter has a pass band that prevents aliasing from occurring during down sampling of the first decimator, And the second low pass filter has a pass band that prevents aliasing from occurring during down sampling of the second decimator. The method of claim 1, The product of the first decimation rate of the first decimator and the second decimation rate of the second decimator corresponds to the down converting rate of the digital down converter. The method of claim 1, And wherein the first decimator is configured to provide a plurality of decimation rates, wherein one of the plurality of decimation rates is activated according to a bandwidth of a received signal. The method of claim 3, wherein The first low pass filter is configured to provide a plurality of pass bands respectively corresponding to a plurality of decimation rates of the first decimator, wherein one of the plurality of pass bands is selected according to the bandwidth of the received signal. Receiving system. A first low pass filter and a decimator configured to low pass filter the input signal into a first pass band and decimate the result of the low pass filtering at a first rate; And A second low pass filter and a decimator configured to low pass filter the output of the first low pass filter and the decimator to a second pass band and to decimate at a second rate; Providing a product of the first ratio and the second ratio as a target down converting ratio, The first low pass filter has a pass band that prevents aliasing from occurring during down sampling of the first decimator, And the second low pass filter has a pass band that prevents aliasing from occurring during down sampling of the second decimator. The method of claim 5, And a first low pass filter and a decimator are configured to vary the first pass band and the first ratio according to the bandwidth of the input signal. The method of claim 5, And the second low pass filter and the decimator comprise at least two low pass filters and decimators connected in a chain structure. The method of claim 5, The first pass band is set to prevent aliasing from occurring during decimation according to the first ratio, and the second pass band is aliased during decimation according to the second ratio. A digital down converter configured to prevent the occurrence of alising. In the digital down-conversion method: Receiving a target signal; And Performing at least twice the low pass filtering and decimating the received target signal, The product of the decimation ratios of the decimations performed at least twice corresponds to a target ratio of the digital down converting, The first low pass filtering has a pass band that prevents aliasing from occurring in the first decimation, and the second low pass filtering has a pass band that prevents aliasing from occurring in the second decimation. Digital down-conversion method set. The method of claim 9, After receiving the target signal, further comprising selecting respective decimation ratios of the decimations performed at least twice and passbands of the at least two performed low pass filterings in accordance with the bandwidth of the target signal. Digital down converting method.

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