KR101124282B1 - Parallel compression tester of a memory device - Google Patents

Abstract

There is provided a parallel compression test circuit for reading a plurality of different bits, reading the same, compressing and outputting the read data, and verifying whether or not the memory cell is defective without providing a separate additional test circuit.

Description

[0001] The present invention relates to a parallel compression tester of a memory device,

1 is an example of a conventional parallel compression test apparatus.

2 is an example of a parallel compression test apparatus according to the present invention.

3 is a truth table explaining the operation of FIG.

The present invention relates to a parallel compression test apparatus for a memory device, and more particularly to a parallel compression test apparatus for performing a test through data compression of a memory device to verify operation of the memory device.

Generally, in order to check whether a memory cell fails, a read operation is performed after writing data to a memory cell to check whether the read data is the same as the originally written data, thereby verifying whether or not the memory cell fails. A device that verifies whether a failure has occurred is a test device.

Hereinafter, a method of verifying whether data read from a memory device fails using a test equipment in a wafer state will be briefly described.

In general, for example, assume that there are eight test pins of the test equipment and X8 operation of the tested memory device. In this case, since the memory device has eight data pins, one memory device can be tested at a time using a test device having eight test pins. However, testing only one memory device with eight test pins from the test equipment is a very inefficient test method.

A parallel compression test method has been proposed to correct this inefficient test method.

In the parallel compression test method, a plurality of identical data are written to a memory cell and then read, and the read data is combined into a logic gate, and the result is output through one data pin.

Hereinafter, a general parallel compression test method will be described with reference to FIG.

In Fig. 1, signals IN1, IN2, IN3, and IN4 represent data read from a memory cell by a read operation. Here, the Q terminal is connected to the data pin of the memory device.

As can be seen from FIG. 1, in the case of using the parallel compression test method, since 4-bit data is written / read, only two data pins can be tested. As a result, four memory devices can be tested simultaneously using test equipment with eight test pins, reducing the test time by a quarter.

However, the parallel compression test method using the conventional parallel compression test circuit shown in FIG. 1 has the following problems.

1) Data that is applied to and read from a memory cell must first be applied at the same logic level. That is, the conventional test method only checks whether the data to be written are all the same. Therefore, when all of the logical levels of the written data are inverted and outputted, there is a problem that the failure can not be verified.

2) Further, there is a problem that, in order to solve the problem of 1), there is a problem that an additional testing process is required to rewrite data having different logic levels by reading and reading data to fail the memory cell.

SUMMARY OF THE INVENTION The present invention has been proposed in order to solve the above-described problems, and provides a circuit capable of performing parallel compression test on data having different logic levels in addition to data having the same logic level.

The apparatus for testing parallel compression of a memory device of the present invention includes: a first compression unit for compressing data of N bits so as to verify whether binary data values of N bits all have the same logic level; And a second compression unit for compressing the N bits of data so as to verify whether any one of the first to third compression levels has a different logic level, To the data pins of the memory.

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Here, the second compression unit is an OR gate, and the third compression unit is an AND gate.

(Example)

Hereinafter, an embodiment of the present invention will be described in detail with reference to Fig.

The apparatus for testing parallel compression of a memory device according to the present invention includes compressors 201, 202, and 203 for compressing binary data IN1 to IN4 of N bits, compressors 201, 202 and 203 for compressing N bits of binary data IN1 to IN4, Unit 204, and a compression unit 205 for compressing the binary data IN1 to IN4 of N bits.

The compression units 201, 202 and 203 include an AND gate 201 for receiving N-bit binary data IN1 to IN4, a NOR gate 202 for receiving N-bit binary data IN1 to IN4, And an OR gate 203 for receiving the output signal of AND gate 201 and the output signal of NO gate.

The compression unit 204 is an OR gate for receiving N-bit binary data IN1 to IN4 and the compression unit 205 is an AND gate for receiving N-bit binary data IN1 to IN4.

The output of the O gate 203 which is the output of the compression unit 203 is output to the data pin Q through the switch 207 when the control signal TM1 is at the high level.

The output of the O gate 204 which is the output of the compression unit 204 is output to the data pin Q through the switch 209 when the control signal TM2 is at the high level.

The output of the O gate 203 which is the output of the compression unit 203 is output to the data pin Q through the switch 211 when the control signal TM3 is at the high level.

Figure 3 is a truth table of the output signal of the device shown in Figure 2;

As shown in the figure, when the control signals TM1 are enabled, the compression units 201 to 203 output the high level data through the Q terminal (for example, 0000 and 1111) The logic signal of level 1 is output, and if not, the logic signal of low level 0 is output. Here, the low level logic signal indicates that a fail has occurred.

When any one of the N bits of binary data IN1 to IN4 is at a high level (for example, 0001, 0010, 0011, 0111, etc.) and the control signal TM2 is enabled, The logic signal of the high level 1 is outputted, and if not, the logic signal of the low level 0 is outputted. Here, the low level logic signal indicates that a fail has occurred.

When all of the N binary data IN1 to IN4 are at a high level (for example, 1111) and the control signal TM3 is enabled, the compression unit 205 outputs a logic signal of high level (1) And otherwise outputs a logic signal of low level (0). Here, the low level logic signal indicates that a fail has occurred.

As described above, in the case of using the apparatus of the present invention, it is possible to verify whether or not a memory cell fails when data having the same logic level is applied or data not having the same logic level is applied.

The present invention compresses a plurality of bits of data having various logic levels and verifies whether a memory cell fails by using the result.

Claims (4)

A parallel compression test apparatus for a memory device, A first compression unit for compressing the N bits of data so as to verify whether binary data values of N bits all have the same logic level, And second and third compression units for compressing the N-bit data so as to verify whether any one of the N-bit binary data values has a different logic level, And outputting the output signals of the first through third compression units to one data pin according to a control signal. delete delete Claim 4 has been abandoned due to the setting registration fee. The method according to claim 1, Wherein the second compression unit is an OR gate, and the third compression unit is an AND gate.

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