KR101116857B1 - Solar cell and method of fabricating the same - Google Patents

Abstract

The solar cell includes a substrate, a first conductive semiconductor layer, an intrinsic semiconductor layer, a second conductive semiconductor layer, a first electrode, and a second electrode. A plurality of nanostructures are formed on the substrate, a first conductive semiconductor layer is formed to cover the nanostructures, an intrinsic semiconductor layer is formed on the first conductive semiconductor layer, and a second conductive semiconductor is formed on the intrinsic semiconductor layer. A layer is formed. The first electrode is formed on the second conductivity type semiconductor layer.

Description

SOLAR CELL AND METHOD OF MANUFACTURING THEREOF {SOLAR CELL AND METHOD OF FABRICATING THE SAME}

The present invention relates to a solar cell and a method for manufacturing the same, and more particularly, to a solar cell and a method for manufacturing the same improved the energy production efficiency.

Photovoltaic power generation is an infinite and clean power generation technology that generates electricity from sunlight. It is a solar cell that generates electricity by receiving sunlight, a power regulator that converts the generated direct current electricity into alternating current, and stores electricity generated during the day. It consists of peripheral devices, such as a storage battery.

Solar cells are basically diodes composed of pn junctions, and are classified into various types according to materials used as light absorbing layers. That is, a solar cell using silicon as a light absorbing layer is largely divided into a crystalline (polycrystalline) substrate type solar cell and a thin film (crystalline, amorphous) solar cell.

However, recently developed low-dimensional nanomaterials are synthesized in the form of single crystal without crystallographically more influenced than thin film type material, and show very few defects inside the nanomaterials. have. In particular, it has the advantage of a process that can be manufactured in large area with cheap raw materials by using a simple process and existing thin film growth equipment.

Nanomaterials with various shapes, such as nanoparticles, nanowires, nanorods, and nanobelts, have been proposed, and research on synthesis development is underway. Nanowires and nanorods having a one-dimensional structure are used for next-generation optoelectronic nanostructures. It is a nano structure that has received the most attention as a process advantage of furnace electrode formation. However, the conventional silicon (Si) nanowire solar cell has to etch a PIN stack grown or formed by VLS (Vapor Liquid Solid) method by using a catalyst such as gold (Au). The minority carrier life time by is a problem.

Accordingly, it is an object of the present invention to provide a solar cell and a manufacturing method thereof having improved energy production efficiency.

A solar cell according to an embodiment of the present invention includes a substrate, a first conductive semiconductor layer, an intrinsic semiconductor layer, and a second conductive semiconductor layer.

A plurality of nanostructures are formed on the substrate. The first conductive semiconductor layer covers the nanostructures, the intrinsic semiconductor layer is provided on the first conductive semiconductor layer, and the second conductive semiconductor layer is provided on the intrinsic semiconductor layer.

A method of manufacturing a solar cell according to another embodiment of the present invention is as follows.

First, a substrate on which a plurality of nanostructures are formed is provided, and a first conductive semiconductor layer is formed to cover the nanostructures. Thereafter, an intrinsic semiconductor layer is formed on the first conductive semiconductor layer, and a second conductive semiconductor layer is formed on the intrinsic semiconductor layer.

According to such a solar cell, the seeds are disposed on the substrate on which the conductive layer is formed, and the nanostructures are grown on the seeds to form a three-dimensional "light trapping" structure. By forming a PIN semiconductor layer on the structure, the light receiving area is increased in the same area as compared to the conventional thin film solar cell to improve the performance compared to the area.

1 is a cross-sectional view of a solar cell according to an embodiment of the present invention.
2A to 2E are perspective views illustrating a method of manufacturing the solar cell of FIG. 1.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

1 is a cross-sectional view of a solar cell 1 according to an embodiment of the present invention.

Referring to FIG. 1, the solar cell 1 includes a substrate 10, a conductive layer 20, a seed 30, a nanostructure 40, a first conductive semiconductor layer 50, and an intrinsic semiconductor layer. 60, a second conductivity type semiconductor layer 70, a first electrode 80, and a second electrode 90.

The substrate 10 is formed of a transparent material having high transmittance of sunlight to transmit incident sunlight. Specifically, the substrate 10 is not limited thereto, but may be an amorphous substrate, for example, an organic substrate or a substrate coated with indium tin oxide (ITO), a substrate coated with a silicon oxide film, or a polymer substrate. .

An anti-reflection film (not shown) may be formed on a surface on which the solar light is incident on the substrate 10 to minimize reflection loss of the incident sunlight. In this case, the anti-reflection film may include MgF ₂ .

The conductive layer 20 may include a transparent conductive material. For example, the conductive layer 20 may include a transparent conductive oxide (TCO). The transparent conductive oxide may be formed to have a rough surface in order to scatter sunlight incident on the incident surface. To this end, the transparent conductive oxide may be textured, and the texturing method may include a direct deposition method using CVD (Chemical Vapor Deposition), a chemical etching method after sputtering, and the like.

Specifically, the transparent conductive oxide is indium tin oxide (ITO), zinc oxide (ZnO), silicon oxide (SiO ₂ ), fluorine-doped tin dioxide (SnO ₂ : F) or zinc oxide doped with aluminum. (ZnO: Al) and the like.

The conductive layer 20 may be formed by depositing zinc oxide as a target using an RF sputtering method, a reactive sputtering method using zinc metal, a metal organic chemical vapor deposition (MOCVD) method, or the like. It can form using. In this case, the sputtering method refers to a method of sputtering a material to be deposited from the target by impinging particles having high kinetic energy, that is, ions accelerated by a voltage difference, onto the target, and depositing the sputtered material on a substrate. .

The seed 30 is formed in an island shape on the conductive layer 20. The seed 30 may be a zinc oxide metal oxide, and in addition, metal impurities such as gallium (Ga), aluminum (Al), indium (In), phosphorus (P), or magnesium (Mg) may be added to the metal oxide. Can be. The seed 30 may be formed using a sputtering method. When the seed 30 is formed of zinc oxide, the target for forming the seed 30 may be zinc oxide.

The nanostructure 40 may include a VLS (Vapor Liquid Solid) method using a catalyst, a VS method without a catalyst, a plasma-enhanced chemical vapor deposition (PECVD) method, a pulsed laser deposition (PLD) method, or a MOVPE method. It is formed on the seed 30 using a (MetalOrganic Vapor Phase Epitaxy) method.

The nanostructure 40 may be in the form of nanorods, nanowires, and the like. The nanostructure 40 may be a zinc oxide metal oxide. In addition, the nanostructure 40 may be formed by adding metal impurities, and the metal impurities may be gallium (Ga), aluminum (Al), indium (In), phosphorus (P), or magnesium (Mg). The metal impurities increase the amount of deformation of the deposition material so that the nanostructures 40 can grow in the form of rods or wires.

The nanostructure 40 has an anti-reflection function that prevents reflection of incident sunlight and a “light trap” function that accumulates incident sunlight.

Plasma treatment after the formation of the nanostructure 40 may improve the electrical and optical properties of the conductive layer 20 and the nanostructure 40, thereby improving efficiency of the solar cell 1. In addition, although four nanostructures 40 (two of which are not shown in cross-section) are grown on one seed 30 in FIG. 1, the number of nanostructures grown on one seed is shown in the embodiment. Subject to change.

Although not shown, a buffer layer may be formed along the nanostructure 40. The buffer layer may be any one of ZnS, CdS, ZnSe, InS, InOOH, and ZnOOH, and may be formed by a chemical bath deposition (CBD) method or an RF sputtering method.

The first conductivity type semiconductor layer 50 is provided to cover the conductive layer 20 and the nanostructure 40. The first conductivity-type semiconductor layer 50 is a P-type semiconductor layer, and specifically, may be formed to increase the number of holes by doping boron (B) or arsenic (As) in amorphous silicon. In FIG. 1, the first conductivity-type semiconductor layer 50 is formed in the form of a film having substantially the same thickness along the outer shape of the nanostructure 40, but according to an embodiment, the first conductivity-type semiconductor layer 50 may be It may be formed in a shape that fills the space between the nanostructure 40.

In this case, the bandgap energy of the first conductivity-type semiconductor layer 50 is greater than the bandgap energy of the intrinsic semiconductor layer 60 so as to cause a photoelectric effect in the intrinsic semiconductor layer 60 without loss of possible solar energy. It is desirable to be large. In order for the bandgap energy of the first conductive semiconductor layer 50 to be greater than the bandgap energy of the intrinsic semiconductor layer 60, the first conductive semiconductor layer 50 includes hydride and carbon ( C) and the like can be added. For example, the first conductivity type semiconductor layer 50 is P-type hydrogenated amorphous silicon (a-Si: H).

Although not shown, a buffer layer may be inserted on the first conductivity type semiconductor layer 50 to improve interfacial properties.

The intrinsic semiconductor layer 60 is provided on the first conductivity type semiconductor layer 50, and the upper portion of the intrinsic semiconductor layer 60 does not appear on the top surface of the intrinsic semiconductor layer 60. It can be formed flat. The intrinsic semiconductor layer 60 is formed of silicon in a state where the number of electrons and holes is about the same, for example, hydrogenated amorphous silicon (a-Si: H).

When the intrinsic semiconductor layer 60 receives sunlight, silicon atoms constituting the intrinsic semiconductor layer 60 absorb light energy. When the silicon atoms absorb light energy, the outermost electrons of the silicon atoms are excited to become free electrons.

The second conductivity type semiconductor layer 70 is provided on the intrinsic semiconductor layer 60. The second conductivity-type semiconductor layer 70 is an N-type semiconductor layer, and specifically, may be formed to increase the number of electrons by doping phosphorus (P) in amorphous silicon. Preferably, the second conductivity type semiconductor layer 70 is N-type hydrogenated amorphous silicon (a-Si: H).

The semiconductor layers 50, 60, and 70 may be formed using a PECVD method using SiH ₄ and H ₂ gases, and various deposition methods such as photo-CVD and hot wire CVD to improve the properties of materials and to increase the stability. This can be used.

When amorphous silicon is used for the semiconductor layers 50, 60, and 70, the diffusion length of the carrier is much lower than that of crystalline silicon due to the characteristics of the amorphous silicon itself. Therefore, as shown in FIG. 1, an intrinsic semiconductor layer to which impurities are not added is inserted between the first and second conductivity-type semiconductor layers 50 and 70 as a light absorbing layer. In this case, the intrinsic semiconductor layer 60 may be depletion by the first and second conductivity-type semiconductor layers 50 and 70 positioned at upper and lower portions and having a high doping concentration, and an electric field is generated therein. do. Accordingly, the electron-hole pairs generated by sunlight in the intrinsic semiconductor layer 60 drift by the internal electric field rather than by diffusion, thereby generating a current.

In the above, the PIN structure as the basic structure of the solar cell has been described, but is not necessarily limited thereto, and the intrinsic semiconductor layer is formed after the second conductive semiconductor layer 70 is formed on the NIP structure, that is, the conductive layer 20. 60 and the first conductivity type semiconductor layer 50 may be formed. However, in the case of the NIP structure, in view of the fact that sunlight is incident from the P side, unlike in FIG. 1, since sunlight is incident from the opposite side of the substrate 10, in this case, the substrate 10 is necessarily made of a transparent material such as glass. There is no need to do this, and translucent or opaque substrates such as silicon or metal materials can be used.

The first electrode 80 is provided on the second conductive semiconductor layer 70. The first electrode 80 may be any metal used as an electrode, but, for example, a light reflectance to reflect the light incident from the substrate 10 and transmitted through the semiconductor layers back to the substrate 10 side. It is preferable to use this high metal. In detail, the first electrode 80 may include Ag, Al, ZnO / Ag, or ZnO / Al.

The second electrode 90 is provided on the conductive layer 20 spaced apart from the first electrode 80 on a plane. The second electrode 90 functions as an opposite electrode to the first electrode 80.

2A to 2E are perspective views illustrating a method of manufacturing the solar cell 1 of FIG. 1.

Referring to FIG. 2A, first, the conductive layer 20 including the transparent conductive material is formed on the transparent substrate 10. As described above, the conductive layer 20 may be formed using a method of depositing zinc oxide as a target using an RF sputtering method, a reactive sputtering method using a zinc metal, or a MOCVD method. Thereafter, the seed 30 is formed in an island shape on the conductive layer 20.

Referring to FIG. 2B, after the seed 30 is formed, the nanostructure 40 is grown on the seed 30. As described above, the nanostructure 40 may be formed using a VLS method using a catalyst, a VS method without a catalyst, a PECVD method, a pulse laser deposition method, or a MOVPE method.

Next, referring to FIG. 2C, the first conductive semiconductor layer 50 is formed to cover the conductive layer 20 and the nanostructure 40. As shown in FIG. 1, the first conductive semiconductor layer 50 is formed in the form of a film having substantially the same thickness along the outer shape of the nanostructure 40. The shape in which the layer 50 is formed may vary depending on the embodiment.

Referring to FIG. 2D, the intrinsic semiconductor layer 60 is formed on the first conductive semiconductor layer 50, and the second conductive semiconductor layer 70 is formed on the intrinsic semiconductor layer 60. For simplicity of the drawings, the seed 30 and the nanostructure 40 included in the first conductivity-type semiconductor layer 50 are not shown in FIG. 2D.

As shown, the upper portion of the intrinsic semiconductor layer 60 may be formed flat so that the step of the first conductive semiconductor layer 50 does not appear on the upper surface of the intrinsic semiconductor layer 60. As described above, the semiconductor layers 50, 60, and 70 may be formed using a PECVD method using SiH ₄ and H ₂ gases. In order to improve the properties of materials and to increase the stability, photo-CVD and heating may be performed. Various deposition methods such as CVD can be used.

Lastly, referring to FIG. 2E, the first electrode 80 is formed on the second conductive semiconductor layer 70, and the second electrode 90 is spaced apart from the first electrode 80. It is formed on the conductive layer 20.

Although not shown, the substrate 10 may be removed from the conductive layer 20 in the final step of the solar cell manufacturing process. In this case, since the conductive layer 20 directly absorbs light, for example, ultraviolet rays, which are blocked by the substrate 10, the absorption rate of solar light may be increased and may be useful for manufacturing a flexible solar cell. have.

In addition, this method is an oxide-based oxide having a transparent conductivity as compared to a method of manufacturing a solar cell by manufacturing a PIN diode while growing silicon into nanowires or a method of manufacturing a solar cell by etching after fabricating a PIN structure diode. Nanowires are used to fabricate anti-reflection film nanostructures and use them as templates to fabricate silicon nanowire PIN diodes.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be. In addition, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, and all technical ideas which fall within the scope of the following claims and equivalents thereof should be interpreted as being included in the scope of the present invention .

1: solar cell 10: substrate
20: conductive layer 30: seed
40: nanostructure 50: first conductive semiconductor layer
60: intrinsic semiconductor layer 70: second conductivity type semiconductor layer
80: first electrode 90: second electrode

Claims (20)

A transparent substrate;
A nanostructure formed on the transparent substrate;
A first conductive semiconductor layer covering the nanostructure;
An intrinsic semiconductor layer provided on the first conductivity type semiconductor layer; And
The second conductivity type semiconductor layer provided on the intrinsic semiconductor layer Solar cell included. The method of claim 1,
The first conductive semiconductor layer is a solar cell, characterized in that provided in the form of a film along the appearance of the nanostructures. The method of claim 2,
The intrinsic semiconductor layer is a solar cell, characterized in that it is provided flat so that the step of the first conductive semiconductor layer does not appear on the upper surface. The method of claim 1,
The solar cell further comprises a conductive layer provided between the transparent substrate and the nanostructures. The method of claim 4, wherein
The conductive layer is a solar cell, characterized in that the transparent conductive oxide. The method of claim 4, wherein
The solar cell further comprises a plurality of seeds provided on the conductive layer to grow the nanostructures. The method of claim 6,
The nanostructures are solar cells, characterized in that four nanostructures are arranged to be located in one of the seeds. The method of claim 1,
The transparent substrate is a solar cell, characterized in that the glass or plastic of a transparent material. The method of claim 1,
The nanostructures are any one of nanorods or nanowires. The method of claim 1,
The first conductive semiconductor layer is a P-type hydrogenated amorphous silicon layer, the intrinsic semiconductor layer is a hydrogenated amorphous silicon layer, the second conductive semiconductor layer is an N-type hydrogenated amorphous silicon layer, characterized in that battery. Providing a transparent substrate;
Growing nanostructures on the transparent substrate;
Forming a first conductive semiconductor layer to cover the nanostructures;
Forming an intrinsic semiconductor layer on the first conductive semiconductor layer; And
The method of manufacturing a solar cell comprising the step of forming a second conductive semiconductor layer on the intrinsic semiconductor layer. The method of claim 11,
The first conductive semiconductor layer is a solar cell manufacturing method, characterized in that provided in the form of a film along the appearance of the nanostructures. The method of claim 12,
The intrinsic semiconductor layer is a manufacturing method of a solar cell, characterized in that provided on the upper surface so that the step of the first conductive semiconductor layer is not flat. The method of claim 11,
And forming a conductive layer between the transparent substrate and the nanostructures. The method of claim 14,
The conductive layer is a method of manufacturing a solar cell, characterized in that the transparent conductive oxide. The method of claim 14,
Forming a plurality of seeds for growing the nanostructures on the conductive layer further comprises a solar cell manufacturing method. The method of claim 16,
The nanostructures are solar cell manufacturing method characterized in that the four nanostructures are arranged in one of the seeds. The method of claim 11,
The transparent substrate is a manufacturing method of a solar cell, characterized in that the glass or plastic of a transparent material. The method of claim 11,
The nanostructures are any one of nanorods or nanowires manufacturing method of a solar cell. The method of claim 11,
The first conductive semiconductor layer is a P-type hydrogenated amorphous silicon layer, the intrinsic semiconductor layer is a hydrogenated amorphous silicon layer, the second conductive semiconductor layer is an N-type hydrogenated amorphous silicon layer, characterized in that Method for producing a battery.

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