KR101110114B1 - Method and circuit for synchronization, and data synchronization apparatus having the same - Google Patents

Abstract

A data synchronization device is disclosed. The apparatus comprises: a transmitting circuit for delaying each of the sequentially input N-bit data during an M-clock cycle of a first clock signal to output (N * M) -bit data every M-clock cycle; And receiving the (N * M) -bit data in response to a second clock signal, sequentially receiving the (N * M) -bit data in N-bit units during the M-clock cycle of the second clock signal. A receiving circuit for outputting.

Synchronization, data loss, synchronizer

Description

Data synchronization method, data synchronization circuit, and data synchronization apparatus including the same {Method and circuit for synchronization, and data synchronization apparatus having the same}

An embodiment according to the concept of the present invention relates to a synchronization device and a method, and to an apparatus and a method capable of transmitting data without data loss between systems using different frequencies.

When transmitting data between systems using different frequencies as operating frequencies, for example, when the frequency of the receiver is much higher than the frequency of the transmitter, it is very unlikely that the data output from the transmitter will be lost at the receiver during data synchronization. low. However, when the frequency of the transmitting end and the frequency of the receiving end are similar to each other, the data output from the transmitting end is likely to be lost at the receiving end.

Accordingly, an aspect of the present invention is to provide a data synchronization device, a data synchronization method, and the data synchronization device that enable the receiver to accurately detect data output from the transmitter when the frequency of the transmitter and the receiver are different from each other. It is to provide a data synchronization system that includes.

The data synchronization device according to an embodiment of the present invention outputs (N * M) -bit data for each M-clock cycle by delaying each N-bit data sequentially input during the M-clock cycle of the first clock signal. Receive the (N * M) -bit data in response to a second clock signal, and receive the received (N * M) -bit data during the M-clock cycle of the second clock signal. It includes a receiving circuit for sequentially outputting in bit units.

The transmission circuit includes a delay block including a plurality of serially connected latch blocks for latching the respective N-bit data in response to the first clock signal, a transmission control signal and a first clock signal. In response to each of the M-clock cycles of the first clock signal, N-bit data input to the first latch block and each N-bit data output from each of the plurality of latch blocks are output. And a data transport block for outputting as the (N * M) -bit data.

The receiving circuit includes a data receiving block for receiving the (N * M) -bit data in response to the second clock signal, and the (N * M) stored in the data receiving block in response to a plurality of selection signals. And a selector for sequentially outputting bit data in the N-bit unit during the M-clock cycle of the second clock signal.

A data processing system according to an embodiment of the present invention includes a first data processing device for outputting respective N-bit data in response to a first clock signal; Delaying the respective N-bit data output from the first data processing apparatus during the M-clock cycle of the first clock signal to generate (N * M) -bit data every M-clock cycle of the first clock signal. A transmission circuit for outputting; Receive the (N * M) -bit data in response to a second clock signal, and sequentially output the received (N * M) -bit data in N-bit units during the M-clock cycle of the second clock signal. Receiving circuitry; And a second data processing device for processing data sequentially output in the N-bit units from the receiving circuit in response to the second clock signal.

According to another aspect of the present invention, a data synchronization device includes a plurality of serially connected latches, each of which is operated in response to a first clock signal; A plurality of first latches for latching input data of a first latch and output data of each of the plurality of latches among the plurality of latches in response to a transmission control signal and the first clock signal; A plurality of second latches, each latching an output signal of each of the plurality of first latches in response to a second clock signal; And a selector for sequentially outputting an output signal of each of the plurality of second latches in response to selection signals.

The data synchronization circuit may include a first AND gate for ANDing the first clock signal and the data enable signal; A counter for outputting count values according to the output signal of the first AND gate; And a second AND gate for outputting the transmission control signal by performing an AND operation on the count values.

The data synchronization method according to an embodiment of the present invention outputs (N * M) -bit data for each M-clock cycle by delaying each N-bit data sequentially input during an M-clock cycle of a first clock signal. Making; And receiving the (N * M) -bit data in response to a second clock signal, sequentially receiving the (N * M) -bit data in N-bit units during the M-clock cycle of the second clock signal. Outputting.

The data synchronization method and the data synchronization circuit according to an embodiment of the present invention have the effect of transmitting data without data loss regardless of the frequency of the transmitter and the receiver.

Specific structural and functional descriptions of embodiments according to the concepts of the present invention disclosed in this specification or application are merely illustrative for the purpose of illustrating embodiments in accordance with the concepts of the present invention, The examples may be embodied in various forms and should not be construed as limited to the embodiments set forth herein or in the application.

Embodiments in accordance with the concepts of the present invention can make various changes and have various forms, so that specific embodiments are illustrated in the drawings and described in detail in this specification or application. However, this is not intended to limit the embodiments in accordance with the concept of the present invention to a particular disclosed form, it should be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and / or second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another, for example, without departing from the scope of rights in accordance with the inventive concept, and the first component may be called a second component and similarly The second component may also be referred to as the first component.

When a component is said to be "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that another component may exist in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features It should be understood that it does not exclude in advance the possibility of the presence or addition of numbers, steps, operations, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined herein. Do not.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a data processing system according to an exemplary embodiment of the present invention. Referring to FIG. 1, a data processing system 1 includes a first processor 3, a second processor 5, and a data synchronization device 10.

The first processor 3 refers to a data processing apparatus capable of processing data in response to the first clock signal SCK despite its name, and the second processor 5 despite the name refers to a second clock. A data processing device capable of processing data in response to the signal DCK. The frequency of the first clock signal SCK and the frequency of the second clock signal DCK are different from each other. According to an embodiment, the frequency of the second clock signal DCK is higher than the frequency of the first clock signal SCK. According to an embodiment, the data synchronization device 10 may be a synchronizer.

According to an embodiment, the first processor 3 may be an image sensor capable of converting an optical signal into an electrical signal. The first processor 3 may transmit the input data SD, which is an electrical signal, to the data synchronization device 10 in response to the first clock signal SCK.

Here, the input data SD may be sequentially transmitted in response to at least one of the rising edge and the falling edge of the first clock signal SCK, as shown in FIG. 6. d, e, f, g, and h). Where N is a natural number.

The second processor 5 may be an image signal processor capable of receiving and processing the data DD restored by the data synchronization device 10. For example, the second processor 5 may receive the data from the data synchronization device 10 in response to at least one of a rising edge and a falling edge of the second clock signal DCK having a frequency different from that of the first clock signal SCK. The output data DD may be received and processed.

The data synchronization device 10 according to the exemplary embodiment of the present invention shown in FIGS. 1 and 2 has (N * M) -bits output from the first processor 3 every M-cycles of the first clock signal SCK. The data sd_r4 may be latched in response to the second clock signal DCK.

FIG. 2 shows a block diagram of the data synchronization device 10 shown in FIG.

Referring to FIG. 2, the data synchronization device 10 includes a transmission circuit 20, a reception circuit 70, and a data bus connected between the transmission circuit 20 and the reception circuit 70.

The transmitting circuit 20 receives each N-bit data SD sequentially input in response to the first clock signal SCK, namely a, b, c, d, e, f, g, and h) may be delayed during the M-clock cycle of the first clock signal SCK to output (N * M) -bit data sd_r4 for each M-clock cycle. N and M are natural numbers.

2 and 6 illustrate the case where M is 4 for convenience of description, but the technical spirit of the present invention is not limited to the value of M. FIG.

The transmission circuit 20 includes a delay block 30, a data transmission block 40, a transmission control signal generation circuit 50, and a first logic circuit 60. According to an embodiment, the transmitting circuit 20 may further include a masking circuit 42 capable of masking the first clock signal SCK in response to the transmission control signal EN. The masking circuit 42 may be implemented with an AND gate.

Delay block 30 includes a plurality of latch blocks 30-1, 30-2, and 30-3 connected in series. Each of the plurality of latch blocks 30-1, 30-2, and 30-3 includes one or a plurality of N-latches.

Each latch block 30-1, 30-2, and 30-3 is input to each latch block 30-1, 30-2, and 30-3 in response to the rising edge of the first clock signal SCK. Latches each of the N-bit data SD, sd_r1, and sd_r2.

For example, referring to FIGS. 2 and 6, the first latch block 30-1 receives the N-bit input data SD = a in response to the rising edge of the first clock signal SCK. Latched as data sd_r1, the second latch block 30-2 receives the first N-bit data sd_r1 output from the first latch block 30-1 in response to the first clock signal SCK. The second N-bit is latched as the second N-bit data sd_r2 and the third latch block 30-3 is output from the second latch block 30-2 in response to the first clock signal SCK. The data sd_r2 may be latched as the third N-bit data sd_r3.

The data transmission block 40 is configured to receive the N-bit data input to the first latch block 30-1 in response to the clock signal generated by the logical combination of the first clock signal SCK and the transmission control signal EN. SD-d and each of the N-bit data (sd_r1 = c, sd_r2 = b, and sd_r3 = a) output from the latch blocks 30-1, 30-2, and 30-3 are transferred to the data bus. . The data transfer block 40 includes a plurality of latch blocks. Each of the plurality of latch blocks may latch N-bit data in response to a clock signal output from the masking circuit 42.

That is, the data transfer block 40 may output 4N-bit data (sd_r4 = abcd) to the data bus every four clock cycles of the first clock signal SCK.

The masking circuit 42 outputs a clock signal for controlling the latch operation of each of the plurality of latch blocks included in the data transfer block 40 in response to the transmission control signal EN and the first clock signal SCK. .

The transmission control signal generation circuit 50 outputs the transmission control signal EN in response to the first clock signal SCK and the data enable signal SD_EN. According to an embodiment, the masking circuit 42 may be implemented as part of the transmission control signal generation circuit 50.

The transmission control signal generation circuit 50 includes a first AND gate 51, a counter 53, and a second AND gate 55.

The first AND gate 51 performs a logical multiplication of the first clock signal SCK and the data enable signal SD_EN. The counter 53 outputs count values in response to the output signal of the first AND gate 51. For example, the counter 53 may be implemented as a 2-bit counter.

The second AND gate 53 performs an AND operation on the count values and outputs a transmission control signal EN. For example, when the count values are 11, since the second AND gate 53 outputs a transmission control signal EN having a high level, the masking circuit 42 may output the first clock signal SCK to the data transmission block 40. Can be sent. Accordingly, the data transfer block 40 selects each N-bit data (SD = d, sd_r1 = c, sd_r2 = b, and sd_r3 = a) in response to the output signal of the masking circuit 42 to one 4N-bit data. Can be transferred to the data bus.

FIG. 3 shows a circuit diagram of the first logic circuit shown in FIG. 2. An operation of the first logic circuit 60 will be described with reference to FIGS. 2 and 3 as follows.

The first logic circuit 60 outputs a data enable signal sd_r4_EN in response to the first clock signal SCK and the transmission control signal EN. The data enable signal sd_r4_EN is an active high signal for instructing the receiving circuit 70 that 4N-bit data on the data bus is valid data.

The first logic circuit 60 includes a first latch 61, a second latch 63, and a logic circuit 65. The first latch 61 latches the transmission control signal EN in response to the first clock signal SCK. The second latch 63 latches the output signal of the first latch 61 in response to the first clock signal SCK. The OR circuit 65 performs an OR operation on the output signal of the first latch 61 and the output signal of the second latch 63 to generate a data enable signal sd_r4_EN.

Referring back to FIG. 2, in response to the rising edge of the second clock signal DCK, the receiving circuit 70 receives 4N-bit data sd_r4 = abcd and receives the received 4N-bit data sd_r4 = abcd. During the 4-clock cycle of the second clock signal DCK, the signals are sequentially output in units of N-bits.

Receive circuit 70 includes a receive block 80 and a selector 89. The receiving circuit 70 may further include a trigger circuit 90, a second logic circuit 100, and an output latch block 110.

The reception block 80 latches 4N-bit data sd_r4 = abcd in response to the second clock signal DCK. Receive block 80 may include M-, e.g., four latch blocks. Each of the four latch blocks includes N-latches. Each of the four latch blocks includes N-bit data (dd0 = a, dd1 = b, dd2 = c, and dd3 = d) among 4N-bit data sd_r4 = abcd in response to the second clock signal DCK. Can be latched.

For example, dd0 corresponds to sd_r3 (eg sd_r3 = a in FIG. 6), dd1 corresponds to sd_r2 (eg sd_r2 = b in FIG. 6), and dd2 corresponds to sd_r1 (eg sd_r1 = c in FIG. 6). And dd3 may correspond to SD (eg, SD = d in FIG. 6).

The selector 89 selects the 4N-bit data dd0, dd1, dd2, and dd3 stored in the reception block 80 in response to the plurality of sequentially selected selection signals SEL. Can output sequentially in N-bit units during a 4-clock cycle. The selector 89 may be implemented as a multiplexer.

4 shows a circuit diagram of the trigger circuit shown in FIG. 2. The operation of the trigger circuit 90 will be described with reference to FIGS. 2 and 4 as follows.

The trigger circuit 90 generates a trigger signal sd_trig in response to the data enable signal sd_r4_EN and the second clock signal DCK. The trigger signal sd_trig is a signal for controlling the operation of the second logic circuit 100.

The trigger circuit 90 includes a third latch 91, a fourth latch 93, an inverter 95, and a third AND gate 97. The third latch 91 latches the data enable signal sd_r4_EN output from the first logic circuit 60 in response to the second clock signal DCK. The fourth latch 93 latches the output signal of the third latch 91 in response to the second clock signal DCK. The first inverter 95 inverts the output signal of the fourth latch 93. The third AND gate 97 performs an AND operation on the output signal of the first inverter 95 and the output signal of the third latch 91 to output the trigger signal sd_trig.

FIG. 5 is a circuit diagram of the second logic circuit shown in FIG. 2. The operation of the second logic circuit 100 will be described with reference to FIGS. 2 and 5 as follows.

The second logic circuit 100 outputs the plurality of selection signals SEL in response to the trigger signal sd_trig and the second clock signal DCK, and inverts any one of the plurality of selection signals SEL. The data output enable signal DD_EN is output.

The second logic circuit 100 includes a selection signal generator 101, a second inverter 103, and a fifth latch 105.

The selection signal generator 101 outputs a plurality of selection signals SEL in response to the second clock signal DCK and the trigger signal sd_trig. The selection signal generator 101 may be implemented with a 3-bit counter. The plurality of selection signals SEL are bits except for the MSB among three bits output from the 3-bit counter.

The second inverter 103 inverts the most significant bit MSB among the bits output from the 3-bit counter. The fifth latch 110 outputs an output signal of the second inverter 103 as an output data enable signal DD in response to the second clock DCK.

The output latch block 110 may latch N-bit data DD sequentially output from the selector 89 in response to the second clock signal DCK.

FIG. 6 is a timing diagram of control signals and data for controlling the operation of the data synchronization device shown in FIG. 2.

2 to 6, the data enable signal SD_EN is a signal for indicating a section in which valid data exists. Each N-bit data a, b, c, and d is transmitted to the input terminal of the first latch block 30-1 in response to the rising edge of the first clock signal SCK.

The first latch block 30-1 latches the first N-bit data in response to the first rising edge of the first clock signal SCK after the data enable signal SD_EN becomes high. Sd_r1 = a. At this time, the count value of the 2-bit counter 53 is 1 (= 01).

The second latch block 30-2 latches N-bit data output from the first latch block 30-1 in response to the second rising edge of the first clock signal SCK. Sd_r2 = a. At the same time, the first latch block 30-1 latches the second N-bit data b in response to the second rising edge. Sd_r1 = b and SD = c. At this time, the count value of the 2-bit counter 53 is 2 (= 10).

Each latch block 30-1, 30-2, and 30-3 latches c, b, and a in response to the third rising edge of the first clock signal SCK. That is, sd_r3 = a, sd_r2 = b, sd_r1 is c, and d is input to the input terminal of the first latch block 30-1. At this time, the count value of the 2-bit counter 53 is 3 (= 11).

The latch blocks of the data transfer block 40 receive sd_r3 (= a), sd_r2 (= b), sd_r1 (= c), and SD (= d) in response to the fourth rising edge of the first clock signal SCK. Latch At this time, the count value of the 2-bit counter 53 is 0 (= 00). Accordingly, the data transfer block 40 transmits 4N-bit data sd_r4 = abcd to the receiving circuit 70 through the data bus in response to the first clock signal SCK.

Each N-bit data e, f, g, and h is sequentially shifted through each latch block 30-1, 30-2, and 30-3 in response to the first clock signal SCK. It is output in units of 4N bits.

4N-bit data sd_r4 = abcd received via the data bus is latched in the receiving block 80 in response to the rising edge of the second clock signal DCK. Each latch block included in the reception block 80 latches N-bit data dd0 (= a), dd1 (= b), dd2 (= c), and dd3 (= d).

The selector 89 stores each N-bit data dd0 (= a), dd1 (= b), dd2 (= c), and dd3 (=) latched in each latch block in response to the plurality of selection signals SEL. d)) is output sequentially.

For example, when the selection signals SEL output from the second logic circuit 100 change sequentially to 0 (= 00), 1 (= 01), 2 (= 10), and 3 (= 11), the selector Reference numeral 89 sequentially outputs each N-bit data dd0 (= a), dd1 (= b), dd2 (= c), and dd3 (= d). At this time, the output data enable signal DD_EN has a high level.

Accordingly, the output latch block 110 responds to each of the N-bit data dd0 (= a), dd1 (= b), dd2 (= c), and dd3 (= d) in response to the second clock signal DCK. Can be latched sequentially.

7 is a flowchart illustrating a data synchronization method according to an embodiment of the present invention. The operation method of the data synchronization device will now be described with reference to FIGS. 2 to 7.

The transmission circuit 20 receives the N-bit data a, b, c, and d sequentially input in response to the rising edge of the first clock signal SCK, and M-clock of the first clock signal SCK. By delaying the cycle, the (N * M) -bit data sd_r4 is output to the data bus every M-clock cycle (S10).

The receiving circuit 70 receives (N * M) -bit data (sd_r4 = abcd) in response to the second clock signal DCK and removes the received (N * M) -bit data (sd_r4 = abcd). The N-bit data a, b, c, and d are sequentially output during the M-clock cycle of the 2-clock signal DCK (S20).

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 is a block diagram of a data processing system according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram of the data synchronization device shown in FIG. 1.

FIG. 3 shows a circuit diagram of the first logic circuit shown in FIG. 2.

4 shows a circuit diagram of the trigger circuit shown in FIG. 2.

FIG. 5 shows a circuit diagram of the second logic circuit shown in FIG. 2.

FIG. 6 is a timing diagram of control signals and data for controlling the operation of the data synchronization device shown in FIG. 2.

7 is a flowchart illustrating a data synchronization method according to an embodiment of the present invention.

Claims (14)

delete A transmission circuit for delaying each of the N-bit data sequentially input during the M-clock cycle of the first clock signal to output (N * M) -bit data every M-clock cycle; And Receive the (N * M) -bit data in response to a second clock signal, and sequentially receive the received (N * M) -bit data in N-bit units during the M-clock cycle of the second clock signal. A receiving circuit for outputting, The transmission circuit, A delay block, each delay block including a plurality of latch blocks connected in series for latching the respective N-bit data in response to the first clock signal; And In response to the transmission control signal and the first clock signal, the N-bit data input to the first latch block of the plurality of latch blocks and the respective N-bit data output from each of the plurality of latch blocks are read. And a data transmission block for outputting as the (N * M) -bit data for each M-clock cycle of a first clock signal. A transmission circuit for delaying each of the N-bit data sequentially input during the M-clock cycle of the first clock signal to output (N * M) -bit data every M-clock cycle; And Receive the (N * M) -bit data in response to a second clock signal, and sequentially receive the received (N * M) -bit data in N-bit units during the M-clock cycle of the second clock signal. A receiving circuit for outputting, The receiving circuit, A data receiving block for receiving the (N * M) -bit data in response to the second clock signal; And And a selector for sequentially outputting the (N * M) -bit data stored in the data receiving block in the N-bit unit during the M-clock cycle of the second clock signal in response to a plurality of selection signals. Data synchronization device. delete A first data processing device for outputting respective N-bit data in response to the first clock signal; Delaying the respective N-bit data output from the first data processing apparatus during the M-clock cycle of the first clock signal, thereby generating (N * M) -bit data every M-clock cycle of the first clock signal. A transmission circuit for outputting a; Receive the (N * M) -bit data in response to a second clock signal, and sequentially receive the received (N * M) -bit data in N-bit units during the M-clock cycle of the second clock signal. A receiving circuit for outputting; And A second data processing device for processing data sequentially output in the N-bit units from the receiving circuit in response to the second clock signal, The transmission circuit, A delay circuit each comprising a plurality of latch blocks connected in series for latching the respective N-bit data in response to the first clock signal; And In response to the transmission control signal and the first clock signal, the N-bit data input to the first latch block of the plurality of latch blocks and the respective N-bit data output from each of the plurality of latch blocks are read. And a data transfer block for outputting as the (N * M) -bit data for each M-clock cycle of the first clock signal. The method of claim 5, wherein the receiving circuit, A data receiving block for receiving the (N * M) -bit data in response to the second clock signal; And And a selector for sequentially outputting the (N * M) -bit data stored in the data receiving block in the N-bit unit during the M-clock cycle of the second clock signal in response to a plurality of selection signals. Data processing system. delete A plurality of latches connected in series each of which operates in response to a first clock signal; A plurality of first latches for latching input data of a first latch and output data of each of the plurality of latches in response to a transmission control signal and the first clock signal; A plurality of second latches, each latching an output signal of each of the plurality of first latches in response to a second clock signal; A selector for sequentially outputting an output signal of each of the plurality of second latches in response to selection signals; A first AND gate for ANDing the first clock signal and the data enable signal; A counter for outputting count values according to the output signal of the first AND gate; And And a second AND gate for outputting the transmission control signal by performing an AND operation on the count values. The data synchronization circuit of claim 8, wherein the data synchronization circuit comprises: And a first logic circuit for outputting a data enable signal based on the first clock signal and the transmission control signal. The method of claim 9, wherein the first logic circuit, A first latch for latching the transmission control signal in response to the first clock signal; A second latch for latching an output signal of the first latch in response to the first clock signal; And And a logical sum circuit for logically combining the output signal of the first latch and the output signal of the second latch. The method of claim 10, wherein the data synchronization circuit, A trigger circuit for outputting a trigger signal in response to an output signal of the OR circuit and the second clock signal; And And a second logic circuit for outputting the selection signals in response to the second clock signal and the trigger signal. The method of claim 11, wherein the trigger circuit, A third latch for latching an output signal of the OR circuit in response to the second clock signal; A fourth latch for latching an output signal of the third latch in response to the second clock signal; A first inverter for inverting the output signal of the fourth latch; And And a third AND gate for outputting the trigger signal by ANDing the output signal of the inverter and the output signal of the third latch. The method of claim 11, wherein the second logic circuit, A counter enabled in response to the trigger signal, the counter outputting count values in response to the second clock signal, And the selection signals comprise some of the counter values. delete

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