KR101107699B1 - Apparatus and method for driving liquid crystal display device - Google Patents

Abstract

The present invention relates to a driving device and a driving method of a liquid crystal display device which can display a PAL video signal more naturally on an NTSC type liquid crystal panel.

The driving apparatus of the liquid crystal display according to the present invention displays more image signals of more scan lines than the scan lines on a liquid crystal panel having a plurality of scan lines and a plurality of data lines that cross vertically to form a liquid crystal cell region. In a liquid crystal display device; A timing controller for dividing and arranging the video signal of one frame into odd field data and even field data, and generating a gate control signal for missing the video signal at positions of different scan lines in the odd and even fields; A data driver converting field data and even field data into an analog image signal and supplying the data lines to correspond to each field; and a scan signal missing at different positions in the odd and even fields in response to the gate control signal. And a gate driver generating and supplying the scan lines to the scan lines.

NTSC, PAL, Scan Signal, Missing, Odd Field, Even Field

Description

Driving apparatus and driving method of liquid crystal display device {APPARATUS AND METHOD FOR DRIVING LIQUID CRYSTAL DISPLAY DEVICE}

1 is a diagram illustrating a PAL image signal displayed on a liquid crystal panel according to a method of driving a liquid crystal display according to a related art.

2 is a diagram illustrating a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 3 shows the timing controller shown in FIG. 2; FIG.

FIG. 4 is a diagram illustrating a gate control signal generator shown in FIG. 3. FIG.

FIG. 5 is a diagram illustrating a gate shift clock generation unit illustrated in FIG. 4.

FIG. 6 is a waveform diagram illustrating a gate control signal for an odd field generated by the gate control signal generator shown in FIG. 4. FIG.

7 is a waveform diagram illustrating a gate control signal for an even field generated by the gate control signal generator shown in FIG. 4.

FIG. 8 is a diagram illustrating a gate output enable signal generator shown in FIG. 4. FIG.

9 is a diagram illustrating a PAL image signal displayed on a liquid crystal panel according to a driving apparatus and a driving method of a liquid crystal display according to an exemplary embodiment of the present invention.

<Explanation of Signs of Major Parts of Drawings>

102: liquid crystal panel 104: data driver

106: gate driver 108: timing controller

120: data processing unit 122: data control signal generation unit

124: gate control signal generator 130: clock signal generator

140: GSC generation unit 150: GOE generation unit

141, 151: counter 142, 152: flip-flop

144, 146: logical sum gate 154, 156: logical product gate

148, 158: field selector

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a driving device and a driving method of a liquid crystal display device for more naturally displaying a PAL image signal on an NTSC type liquid crystal panel.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have emerged. Examples of such flat panel display devices include a liquid crystal display, a field emission display, a plasma display panel, and a light emitting display.

A typical liquid crystal display among flat panel displays displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal panel having a liquid crystal cell matrix for displaying an image, and a driving circuit for driving the liquid crystal panel. Active matrix type liquid crystal displays that independently drive liquid crystal cells using thin film transistors are widely used for televisions as well as display devices of personal computers (PCs).

Although a liquid crystal display displays a television signal or a personal computer signal, since various standards exist for these signals, it is usually necessary to manufacture a liquid crystal panel in accordance with each standard. That is, the liquid crystal panel of the liquid crystal display device is manufactured based on NTSC (National Television System Committee) method or based on PAL (Phrase Alternative by Line) method.

Comparing the NTSC method and the PAL method, the NTSC signal has a video signal of 240 scan lines per field, and the PAL method has a video signal of 280 scan lines per field.

For example, when a liquid crystal panel having 234 scan lines is manufactured, the entire NTSC video signal may be normally displayed on the liquid crystal panel. However, since the PAL video signal has a video signal of 280 scan lines in one field, the liquid crystal panel cannot display 280 scan lines.

Therefore, when the PAL video signal is displayed on the liquid crystal panel manufactured based on the NTSC system, the PAL video signal is not displayed every 6 to 8 scan lines. In other words, in order to display more image signals than the scan lines of the liquid crystal panel on the liquid crystal panel, one scan line is omitted every 6 to 8 scan lines.

For example, when an NTSC system image signal corresponding to a diagonal line is displayed on a liquid crystal panel manufactured based on the NTSC system, a diagonal line is continuously displayed naturally on the liquid crystal panel.

However, in the PAL video signal, one scan line is missed every 6 to 8 scan lines, so that a diagonal line is displayed discontinuously (step shape) as shown in FIG. 2.

In the driving method of the liquid crystal display according to the related art, a clear horizontal line (horizontal dim) is generated at a portion where a PAL image signal is missing from the scan line at the same position in odd and even fields. Image quality deteriorates.

Therefore, the driving method of the liquid crystal display device according to the related art has a problem in that a natural PAL image signal cannot be displayed on the liquid crystal panel manufactured by the NTSC method.

Accordingly, in order to solve the above problems, the present invention is to provide a driving device and a driving method of a liquid crystal display device that can display a PAL video signal more naturally on the NTSC type liquid crystal panel.

A driving device of a liquid crystal display according to an exemplary embodiment of the present invention for achieving the above object is a scan line on a liquid crystal panel having a plurality of scan lines and a plurality of data lines vertically intersecting to form a liquid crystal cell region. A liquid crystal display for displaying more image signals of a scanning line than these; A timing controller for dividing and arranging the video signal of one frame into odd field data and even field data, and generating a gate control signal for missing the video signal at positions of different scan lines in the odd and even fields; A data driver converting field data and even field data into an analog image signal and supplying the data lines to correspond to each field; and a scan signal missing at different positions in the odd and even fields in response to the gate control signal. And a gate driver generating and supplying the scan lines to the scan lines.

In the driving apparatus of the liquid crystal display, the scan signal is missing for every N (where N is a positive integer) scan lines in the odd field, and for every N + 1 scan lines in the even field. .

In the driving device of the liquid crystal display, the liquid crystal panel has scan lines corresponding to the NTSC (National Television System Committee) method, and displays an image signal of PAL (Phrase Alternative by Line).

According to an exemplary embodiment of the present invention, a method of driving a liquid crystal display device includes an image of more scan lines than the scan lines on a liquid crystal panel having a plurality of scan lines and a plurality of data lines vertically intersecting to form a liquid crystal cell region. A liquid crystal display for displaying a signal; Dividing and arranging the video signal of one frame into odd field data and even field data, generating scan signals that are missing at different positions in the odd and even fields, and supplying the scan signals to the scan lines; And converting the odd field data and the even field data into an analog image signal so as to be synchronized with the scan signal supplied to the line, and supplying the odd field data to the data lines so as to correspond to each field.

In the method of driving the liquid crystal display, the scan signal is missing for every N (where N is a positive integer) scan lines in the odd field and is lost for every N + 1 scan lines in the even field. .

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

2 is a view schematically illustrating a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a driving apparatus of a liquid crystal display according to an exemplary embodiment of the present invention may include a plurality of scan lines GL1 through GLn and a plurality of data lines DL1 through DLm that vertically intersect to form a liquid crystal cell region. A liquid crystal display for displaying image signals RGB of more scan lines than the scan lines GL1 to GLn on the liquid crystal panel 102; The image signal is received and arranged in odd field and even field data odata and edata, and a data control signal DCS for supplying an analog image signal to data lines DL1 to DLm is generated. A timing controller 108 for generating a gate control signal GCS for supplying a scan signal to the scan line GL such that the analog image signals at different scan line positions in the even field are missing; and the timing controller 108 Data driver 104 for converting odd and even field data (odata, edata) from &lt; RTI ID = 0.0 &gt;) &lt; / RTI &gt; And a gate driver 106 for supplying a scan signal to the scan line GL in accordance with GCS.

The liquid crystal panel 102 includes a thin film transistor TFT formed at a portion where each of the scan lines GL1 to GLn and the data lines DL1 to DLm cross each other, and liquid crystal cells connected to the thin film transistor TFT. The thin film transistor TFT supplies an analog image signal from the data lines DL1 to DLm to the liquid crystal cell in response to a scan signal from the scan lines GL1 to GLn. The liquid crystal cell is composed of a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT, so that the liquid crystal cell may be equivalently represented as a liquid crystal capacitor Clc. The liquid crystal cell includes a storage capacitor Cst for maintaining the analog image signal charged in the liquid crystal capacitor Clc until the next analog image signal is charged. Here, the liquid crystal panel 102 is manufactured based on the NTSC (National Television System Committee) method.

The data driver 104 stores the odd field data and the even field data edata, respectively, from the timing controller 108 in accordance with the data control signal DCS supplied from the timing controller 108. Convert to video signal. Accordingly, the data driver 104 supplies the odd-field analog video signal to the data lines DL1 to DLm in the odd field of one frame, and the even-field analog video signal in the even field. DL1 to DLm).

The gate driver 106 is a gate control signal GCS from the timing controller 108, that is, a gate start pulse GSP, a gate shift clock GSC, and a gate output enable signal. According to GOE, a scan signal for turning on and off the thin film transistors TFTs connected to the scan lines GL1 to GLn is generated and supplied to the scan lines GL1 to GLn. In this case, the gate driver 106 generates a scan signal for dropping the analog image signal at different scan line positions in the odd and even fields according to a gate control signal GCS to generate the scan lines GL1 to GLn. To feed.

The timing controller 108 divides the image signal RGB having more scan lines from the outside than the scan lines of the liquid crystal panel 102 into odd field data odata and even field data edata. In addition, the timing controller 108 uses the main clock MCLK, the data enable signal ED, and the horizontal and vertical synchronization signals Hsync and Vsync input from the outside, and the data control signal DCS and the gate control signal ( GCS) is generated to control the driving timing of each of the data driver 4 and the gate driver 6.

To this end, the timing controller 108 includes a data processor 120 for dividing and arranging the image signal RGB input from the outside into odd field data odata and even field data edata; A data control signal for generating a data control signal DCS and a gate control signal GCS using a main clock MCLK, a data enable signal ED, and horizontal and vertical synchronization signals Hsync and Vsync. The generator 122 and the gate control signal generator 124 are provided.

The data processor 120 divides the video signal RGB from the outside, that is, the PAL (Phrase Alternative by Line) video signal RGB into odd field data odata and even field data edata, Each of the odd-numbered field data odata and even-field data edata is supplied to the data driver 104 for each field.

The data control signal generator 122 uses a main clock MCLK, a data enable signal DE, and horizontal and vertical synchronization signals Hsync and Vsync, which are input from an external source, to the source start pulse SSP. And generate a data control signal (DCS) including a source shift clock (SSC), a source output signal (SOC), and a polarity signal (POL) to the data driver 104. do.

The gate control signal generator 122 uses the data enable signal DE, the horizontal and vertical synchronizing signals Hsync and Vsync, which are input from the outside, to the gate start pulse GSP, the gate shift clock GSC, and the gate output. The gate control signal GCS including the signal GOE is generated and supplied to the gate driver 106. In this case, the gate control signal generator 122 generates different gate shift clocks GSC and gate output enable signals GOE according to the method of the image signal RGB supplied to the timing controller 108.

In detail, the gate control signal generator 122 generates the first reference gate shift clock GSC1 to generate a scan signal corresponding to the image signal RGB supplied to the timing controller 108 as shown in FIG. 4. And the clock signal generator 130 for generating the first reference gate output enable signal GOE1 and the gate shift clock GSC according to the first reference gate shift clock GSC1. A gate output enable signal for generating a gate output enable signal GOE according to the gate shift clock generator 140 and a first reference gate output enable signal GOE1 and supplying the gate output enable signal to the gate driver 106. The generation unit 150 is provided.

The clock signal generation unit 130 displays the NTSC video signal RGB on the liquid crystal panel 102 using the data enable signal DE and horizontal and vertical synchronization signals Hsync and Vsync. The first reference gate shift clock GSC1 is generated. In addition, the clock signal generation unit 130 displays the NTSC video signal RGB on the liquid crystal panel 102 using the main clock MCLK and horizontal and vertical synchronization signals Hsync and Vsync. A first reference gate output enable signal GOE1 is generated.

The gate shift clock generator 140 generates a second reference gate shift clock GSC2 by counting the first reference gate shift clock GSC1 from the clock signal generator 130 as shown in FIG. 5. A first flip for delaying the second reference gate shift clock GSC2 output from the first counter 141 according to the first counter 141 and the clock signal CLK to generate the third reference gate shift clock GSC3. A first logic sum gate 144 for generating an odd field gate shift clock GSCo by performing a logical sum operation on the flop 142 and the first and second reference gate shift clocks GSC1 and GSC2; A second logical sum gate 146 for generating a gate shift clock GSCe for even fields by performing a logical sum operation on the third reference gate shift clocks GSC1 and GSC3 and a field selection signal corresponding to the vertical synchronization signal Vsync. Gate shift for odd and even fields according to (Fs) A first field selector 148 is provided to select one of the clocks GSCo and GSCe as the gate shift clock GSC and to supply the gate driver 106 to the gate driver 106.

As illustrated in FIG. 6, the first counter 141 counts the first reference gate shift clock GSC1 from the clock signal generation unit 130 in units of N (where N is a positive integer) to determine the second reference. The gate shift clock GSC2 is generated and output.

The first flip-flop 142 is reset by the vertical synchronization signal Vsync, and the second reference gate shift clock GSC2 from the first counter 141 according to the clock signal CLK as shown in FIG. 7. Delays by one clock to generate a third reference gate shift clock GSC3 and supply it to the second logic sum gate 146.

The first logic sum gate 144 generates a gate shift clock GSCo for the odd field shown in FIG. 6 by performing a logic sum operation on the first and second reference gate shift clocks GSC1 and GSC2 to generate a first field selector. Supply to 148.

The second logic sum gate 146 generates the even field gate shift clock GSCe shown in FIG. 7 by performing a logic sum operation on the first and third reference gate shift clocks GSC1 and GSC3 to generate a first field selector. Supply to 148.

The first field selector 148 may use the odd-field gate shift clock GSCo and the second logic sum from the first logic sum gate 144 according to the field select signal Fs corresponding to the vertical synchronization signal Vsync. One of the even field gate shift clock GSCe from the gate 146 is selected as the gate shift clock GSC and supplied to the gate driver 106.

The gate shift clock generator 140 generates different gate shift clocks GSC in the odd and even fields, respectively, and supplies them to the gate driver 106. That is, the gate shift clock generator 140 generates a gate shift clock GSC for dropping the analog image signal at different scan line positions in the odd and even fields and supplies the gate shift clock GSC to the gate driver 106.

Meanwhile, as illustrated in FIG. 8, the gate output enable signal generator 150 counts the first reference gate output enable signal GOE1 from the clock signal generator 130 to enable the second reference gate output enable. The second reference gate output signal GOE2 output from the second counter 151 according to the clock signal CLK and the second counter 151 generating the signal GOE2 are delayed to output the third reference gate. The gate output enable signal GOEo for the odd field by performing a logical multiplication on the second flip-flop 152 generating the enable signal GOE3 and the first and second reference gate output enable signals GOE1 and GE2. A second logical product gate 154 for generating a PDU and a second gate output enable signal (GOEe) for generating an even field by performing a logical multiplication on the first and third reference gate output enable signals (GOE1 and GOE3). Logical product gate 156 and vertical sync signal Vsync A second to select one of the odd and even field gate output enable signals GOEo and GOEe as the gate output enable signal GOE and supply it to the gate driver 106 according to the corresponding field selection signal Fs. And a field selector 158.

As illustrated in FIG. 6, the second counter 151 counts the first reference gate output enable signal GOE1 from the clock signal generator 130 in units of N (where N is a positive integer). A two reference gate output enable signal GOE2 is generated and output.

The second flip-flop 152 is reset by the vertical synchronization signal Vsync, and as shown in FIG. 7, the second reference gate output enable signal from the second counter 151 according to the clock signal CLK (see FIG. 7). By delaying GOE2 by one clock, the third reference gate output enable signal GOE3 is generated and supplied to the second logical product gate 156.

The first logical product gate 154 generates a gate output enable signal GOEo for the odd field shown in FIG. 6 by performing a logical multiplication on the first and second reference gate output enable signals GOE1 and GOE2. It supplies to the two field selection part 158.

The second logical product gate 156 generates a gate output enable signal GOEe for the even field shown in FIG. 7 by performing a logical multiplication on the first and third reference gate output enable signals GOE1 and GOE3. It supplies to the two field selection part 158.

The second field selector 158 and the gate output enable signal GOEo for the odd field from the first logical product gate 154 and the second in accordance with the field select signal Fs corresponding to the vertical synchronization signal Vsync. One of the even field gate output enable signal GOEe from the logical product gate 156 is selected as the gate output enable signal GOE and supplied to the gate driver 106.

The gate output enable signal generator 150 generates a different gate output enable signal GOE in each of the odd field and the even field, and supplies the generated gate output enable signal GOE to the gate driver 106. That is, the gate output enable signal generator 150 generates a gate output enable signal GOE for dropping analog image signals of different scan line positions in the odd and even fields and supplies the gate output enable signal GOE to the gate driver 106. do.

As such, when the image signal RGB of more scan lines than the scan lines of the liquid crystal panel 102 is supplied from the outside, the timing controller 108 outputs an analog image signal every N scan lines in an odd field of one frame. An odd fill gate shift clock (GSCo) and a gate output enable signal (GOEo) are generated and supplied to the gate driver 106 for omission, while in an even field of one frame, an analog image every N + 1 scan lines. An even fill gate shift clock GSCe and a gate output enable signal GOEe for dropping the signal are generated and supplied to the gate driver 106.

Referring to FIG. 2 and FIG. 6 and FIG. 7, a driving device and a driving method of a liquid crystal display according to an exemplary embodiment of the present invention will be described.

First, when the image signals RGB of more scan lines than the scan lines of the liquid crystal panel 102 are displayed in the odd field of one frame, the timing controller 108 corresponds to the odd field as shown in FIG. 6. The odd field gate shift clock GSCo and the odd field gate output enable signal GOEo are generated and supplied to the gate driver 106 by the field selection signal Fs. Accordingly, the gate driver 106 generates a scan signal for omitting the analog image signals at the N scan line positions and supplies the scan signal to the scan lines GL1 to GLn. That is, in the odd field of one frame, the gate driver 106 does not supply the scan signal for every N scan lines in response to the gate output enable signal GOEo for the odd field. As a result, since no scan signal is supplied every N scan lines in the odd field of one frame, the image signal RGB of more scan lines is lost for every N scan lines than the scan lines of the liquid crystal panel 102. Is indicated at 102.

In addition, in the case of displaying in the even field of one frame, the timing controller 108 may use the even field gate shift clock GSCe and the even field by the field selection signal Fs corresponding to the even field, as shown in FIG. 7. The gate output enable signal GOEe is generated and supplied to the gate driver 106. Accordingly, the gate driver 106 generates a scan signal for dropping the analog video signal at the N + 1 scan line positions and supplies the scan signal to the scan lines GL1 to GLn. That is, in the even field of one frame, the gate driver 106 does not supply the scan signal for every N + 1 scan lines in response to the even field gate output enable signal GOEe. As a result, the scan signal is not supplied every N + 1 scan lines in the even field of one frame, so that the image signals RGB of more scan lines per N + 1 scan lines than the scan lines of the liquid crystal panel 102 are. It is missing and displayed on the liquid crystal panel 102.

As described above, the driving apparatus and the driving method of the liquid crystal display according to the exemplary embodiment of the present invention may generate more image signals RGB of more scan lines (PAL) than the scan lines (NTSC) of the liquid crystal panel 102. In the case of displaying, the image quality can be prevented by dropping analog video signals at positions of different scan lines in odd and even fields. As a result, in the driving apparatus and driving method of the liquid crystal display according to the exemplary embodiment of the present invention, when the diagonal line shape of the PAL method is displayed on the liquid crystal panel 102 of the NTSC method, the diagonal line shape is continuous as shown in FIG. 9. Displayed naturally, the picture quality is greatly improved.

Meanwhile, in the driving apparatus and driving method of the liquid crystal display according to the exemplary embodiment of the present invention, the video signal of the odd field is omitted for every N scan lines, and the video signal of the even field is omitted for every N + 1 scan lines. Instead, various substitutions, modifications, and changes are possible within the range in which the odd and even field video signals are omitted for different scan lines.

Accordingly, the present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those skilled in the art.

The driving apparatus and method of the liquid crystal display according to the embodiment of the present invention as described above, when the PAL image signal is displayed on the NTSC type liquid crystal panel, positions of different scan lines in odd and even fields of one frame By omitting the video signal, the PAL video signal can be displayed more naturally on the liquid crystal panel.

Claims (16)

A liquid crystal display for displaying an image signal of more scan lines than the scan lines on a liquid crystal panel having a plurality of scan lines and a plurality of data lines perpendicularly intersecting to form a liquid crystal cell area; A timing controller for dividing and arranging the video signal of one frame into odd field data and even field data and generating a gate control signal for missing the video signal at positions of different scan lines in the odd and even fields; A data driver converting the odd field data and the even field data into an analog image signal and supplying the data lines to the respective data lines so as to correspond to each field; A gate driver configured to generate scan signals missing at different positions in the odd and even fields in response to the gate control signal, and supply the scan signals to the scan lines; The timing controller includes a gate control signal generation unit configured to generate the gate control signal including different gate shift clocks and gate output enable signals according to the odd and even fields, and supply the gate control signal to the gate driver. The gate control signal generator generates a first reference gate shift clock and a first reference gate output enable signal using a data enable signal and a synchronization signal from an external device, and the first reference gate shift clock. A gate shift clock generator for generating an odd field gate shift clock and an even field gate shift clock using the first reference gate output enable signal, and an odd field gate output enable signal and an even field And a gate output enable signal generator for generating a gate output enable signal. The method of claim 1, And the scan signal is missing for every N (where N is a positive integer) scan lines in the odd field and for every N + 1 scan lines in the even field. The method of claim 1, The timing controller, A data processor for dividing the video signal of one frame into odd field data and even field data, and providing the data signal to the data driver; And a data control signal generator for generating a data control signal for controlling the data driver. delete The method of claim 1, The gate driver generates the scan signal according to the gate shift clock for the odd field during the odd field, and supplies the scan signal to the scan lines according to the gate output enable signal for the odd field, and supplies the scan field for the even field during the even field. And generating the scan signal according to a gate shift clock and supplying the scan signal to the scan lines according to the gate output enable signal for the even field. The method of claim 5, The gate shift clock generator, A first counter for counting the first reference gate shift clock to generate a second reference gate shift clock for each set value; A first delayer generating a third reference gate shift clock by delaying a second reference gate shift clock from the first counter according to a clock signal; A first logic sum gate for generating a gate shift clock for the odd field by performing a logic sum operation on the first and second reference gate shift clocks; A second logic sum gate for generating a gate shift clock for the even field by performing a logic sum operation on the first and third reference gate shift clocks; A first field selector for selecting an odd field gate shift clock from the first logic sum gate and an even field gate shift clock from the second logic sum gate and supplying the gate shift clock to the gate driver according to a field selection signal; A drive device for a liquid crystal display device, characterized in that. The method of claim 6, The gate output enable signal generator, A second counter counting the first reference gate output enable signal to generate a second reference gate output enable signal for each set value; A second delayer configured to delay a second reference gate output enable signal from the second counter to generate a third reference gate output enable signal according to a clock signal; A first logical product gate configured to perform a logical multiplication on the first and second reference gate output enable signals to generate the gate output enable signal for the odd field; A second logical product gate configured to logically multiply the first and third reference gate output enable signals to generate the even output gate output enable signal; A second field for selecting an odd field gate output enable signal from the first logical product gate and an even field gate output enable signal from the second logical product gate according to a field selection signal, and supplying the gate output enable signal to the gate driver A drive device for a liquid crystal display device comprising a selection unit. The method of claim 7, wherein And the first and second retarders are reset by a vertical synchronization signal. The method of claim 1, The liquid crystal panel has scan lines corresponding to the NTSC (National Television System Committee) method, and displays a PAL (Phrase Alternative by Line) video signal. A liquid crystal display for displaying an image signal of more scan lines than the scan lines on a liquid crystal panel having a plurality of scan lines and a plurality of data lines perpendicularly intersecting to form a liquid crystal cell area; Dividing and sorting the video signal of one frame into odd field data and even field data; Generating scan signals that are missed at different positions in the odd and even fields and supplying them to the scan lines; and Converting the odd field data and the even field data into an analog image signal so as to be synchronized with the scan signal supplied to the scan line, and supplying the odd field data to the data lines so as to correspond to each field; The generating of the scan signal may include generating a first reference gate shift clock and a first reference gate output enable signal using a data enable signal and a synchronization signal from an external source, and generating the first reference gate shift clock. Generating an odd field gate shift clock and an even field gate shift clock by using the first reference gate output enable signal and an odd field gate output enable signal and an even field gate output enable signal by using the first reference gate output enable signal Method of driving a liquid crystal display device comprising the step of generating. 11. The method of claim 10, And the scan signal is missing for every N (where N is a positive integer) scan lines in the odd field and for every N + 1 scan lines in the even field. delete 11. The method of claim 10, The generating of the scan signal and supplying the scan signal to the scan lines may include: Generating the scan signal according to the gate shift clock for the odd field during the odd field, and supplying the generated scan signal to the scan lines according to the gate output enable signal for the odd field; Generating the scan signal according to the even field gate shift clock during the even field, and supplying the generated scan signal to the scan lines according to the gate output enable signal for the even field. A method of driving a liquid crystal display device. The method of claim 13, Generating the odd field gate shift clock and the even field gate shift clock, Generating a second reference gate shift clock for each set value by counting the first reference gate shift clock; Generating a third reference gate shift clock by delaying the second reference gate shift clock according to a clock signal; Generating a gate shift clock for the odd field by performing a logical sum operation on the first and second reference gate shift clocks; Generating a gate shift clock for the even field by performing a logical sum operation on the first and third reference gate shift clocks; And selecting and outputting the odd field gate shift clock and the even field gate shift clock according to a field selection signal. The method of claim 13, Generating the odd field gate output enable signal and the even field gate output enable signal, Counting the first reference gate output enable signal to generate a second reference gate output enable signal for each set value; Generating a third reference gate output enable signal by delaying the second reference gate output enable signal according to a clock signal; Generating a gate output enable signal for the odd field by performing a logical multiplication on the first and second reference gate output enable signals; Generating a gate output enable signal for the even field by performing a logical multiplication on the first and third reference gate output enable signals; And selecting and outputting the odd field gate output enable signal and the even field gate output enable signal according to a field selection signal. 11. The method of claim 10, The liquid crystal panel has scan lines corresponding to the NTSC (National Television System Committee) method, and displays a PAL (Phrase Alternative by Line) image signal.

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