KR101103961B1 - Half rate burst mode clock and data recovery - Google Patents

Abstract

The present invention discloses a half rate burst mode clock data decompressor. A clock data decompressor according to the present invention includes a half-rate burst mode clock data decompressor including a reference phase locked loop, the clock data decompressor comprising: an open / close circuit separating an edge detection pulse generated through input data into a set signal and a reset signal; A first open / close oscillator (GVCO) for outputting a recovery clock using the set signal and the reset signal; A delay circuit for delaying the input data; And a data recovery unit for restoring the data delayed through the delay circuit to first and second data having different phases by using both an up edge and a down edge of the recovery clock. According to the present invention, while the half-rate operation of the switch circuit of the restorer has the advantage of ensuring the same performance as the full rate.

Description

Half rate burst mode clock and data recovery

The present invention relates to a half rate burst mode clock data decompressor, and more particularly, to a clock data decompressor capable of guaranteeing the same performance as a full rate operation even at a half rate.

With the recent Internet becoming an indispensable element in our lives, network providers are constantly striving to improve the quality of their networks.

In recent years, the method of connecting network subscribers with optical cables is generally adopted in that it can accommodate broadband services. The PON (Passive Optical Network) method using a repeater as a passive element in an optical cable network has high reliability and low cost. It is getting a spotlight because of its structure.

1 is a diagram illustrating a configuration of a general PON system.

As shown in FIG. 1, in an PON system, an optical cable is connected to an optical line terminal (OLT) 100 and a passive optical splitter 102 in a PON system, and each of the passive optical repeaters 102 is connected to one optical cable. Optical network units (ONUs) 104-1 to 104-3 are connected via individual optical cables.

Here, the transmission of data from the OLT 100 to the ONU 104 is called a downlink, and the transmission in the opposite direction is called an uplink.

In this case, the downlink and the uplink may be implemented as one optical cable using light having different wavelengths, and this method is called wavelength division multiplexing (WDN).

On the other hand, a time division scheme may be used, and in downlink, the OLT 100 transmits data to a plurality of ONUs 104-1 to 104-3 collectively, and each ONUs 104-1 to 104-3. ) Can only take data that arrives at its assigned time. In the uplink, time slots corresponding to each ONU 104-1 to 104-3 are allocated, and each ONU 104-1 to 104-3 is assigned to the OLT 100 side in the time slot assigned thereto. Can send data

In the downlink, the OLT 100 transmits data to a plurality of ONUs 104 at a time. In the uplink, one OLT 100 transmits data to each ONU 104-1 to 104-3 at an allocated time. Should be received. However, since the channels from the passive optical relay device 102 to each ONU 104 are different in the middle of the path, the size and timing information of the data received by the OLT 100 are different depending on time. Since one receiver has to follow the data characteristics that change every time, the uplink operates in burst mode (BM).

In the PON system as described above, due to the tree structure, an optical packet of a burst mode is used during uplink, and the OLT 100 includes a burst mode clock data decompressor to compensate for a phase difference between the packet and the packet. Burst Mode Clock and Data Recovery (BM-CDR) is required.

The conventional BM-CDR includes a structure using a matched gated oscillator as shown in FIG. 2 or a structure using a gating circuit as shown in FIG. 3 (M. Banu, “Clock Recovery Circuits with Instantaneous Locking, ”ELECTRONICS LETTERS 5th vol. 28 No. 23, Nov 2008).

Here, the structure using the switching circuit can reduce the number of the switching oscillator is a structure generally employed in the BM-CDR.

In general, a conventional BM-CDR has a full rate structure. In a full-rate CDR, an open / close circuit that must operate at the same frequency as the input data rate (N bps). Therefore, there is a problem that the data recovery unit and the output terminal must also have an operating speed of N Hz.

In order to solve the problems of the prior art as described above, it is an object of the present invention to propose a half rate burst mode clock data restorer capable of guaranteeing the same performance as a full rate even when operating at half rate.

According to a preferred embodiment of the present invention to achieve the above object, in the half-rate burst mode clock data restorer including a reference phase locked loop, the edge detection pulse generated through the input data as a set signal and a reset signal; Separate switching circuit; A first open / close oscillator (GVCO) for outputting a recovery clock using the set signal and the reset signal; A delay circuit for delaying the input data; And a data recovery unit for restoring the data delayed through the delay circuit to the first and second data having different phases using both the up edge and the down edge of the recovery clock.

The switching circuit may include: a half cycle delay cell that delays the input data by a half cycle; An edge detection pulse output unit configured to generate the edge detection pulse using the input data and the half cycle delayed data; And a signal separator configured to separate the edge detection pulse into the set signal and the reset signal using a GVCO clock input from the first open / close oscillator.

The edge detection pulse output unit may be at least one of an exclusive logic gate or an AND gate.

The signal separator may include: a set signal output unit configured to output the set signal by inputting the edge detection pulse and the GVCO clock; And a reset signal output unit configured to output the reset signal by inputting the edge detection pulse and the inverted signal of the GVCO clock.

Preferably, the first opening and closing oscillator, at least one delay cell; And a recovery clock output unit for outputting the recovery clock, wherein the recovery clock output unit may be a differential circuit including a set signal input terminal, a reset signal input terminal, and a clock input terminal to which a clock is input from the delay cell.

The recovery clock output unit outputs a recovery clock using one of the set signal input terminal and the reset signal input terminal according to the state of the clock input through the clock input terminal.

The GVCO clock is the output of one of the one or more delay cells.

The data recovery unit may include: a first D-flip-flop configured to output data input from an upper edge of the recovery clock among data delayed through the delay circuit; And a second D-flip-flop that outputs data input at a downward edge of the recovery clock among the data delayed through the delay circuit.

According to another aspect of the present invention, in the half-rate burst mode clock data restorer, an open / close circuit for separating an edge detection pulse generated through input data into a set signal and a reset signal, and a recovery clock using the set signal and the reset signal. A clock data recovery core having a first open / close oscillator for outputting the signal; And a reference phase locked loop allowing the first open / close oscillator to operate at a preset frequency.

According to the present invention, the concept of set / reset has an advantage of guaranteeing the same bit error rate (BER) and CID Consecutive Identical Digit (BER) performance as the full rate while operating at half rate for clock data recovery.

1 is a diagram illustrating a configuration of a general PON system.
2 to 3 show the structure of a conventional burst mode clock data decompressor.
4 illustrates the structure of a half rate burst mode clock data decompressor in accordance with a preferred embodiment of the present invention.
5 is a diagram showing the detailed configuration of the switching circuit 402 according to an embodiment of the present invention.
6 is a timing diagram of pulses output through input data and delay cells and edge detection pulse outputs, respectively;
Fig. 7 is a timing diagram shown when a conventional open / close circuit operating at full rate is operated at half rate.
8 is a timing diagram in the case of using an open / close circuit and a GVCO structure to which the set / reset switching concept according to the present invention is applied.
9 is a diagram illustrating a detailed configuration of a recovery clock output unit according to an embodiment of the present invention.
10 and 11 illustrate examples of recovering clock and data by the method according to the present invention.

As the present invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a structure of a half rate burst mode clock data recoverer according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the clock data restorer according to the present embodiment may include a clock data recovery core 400 (hereinafter, referred to as a 'CDR core') and a reference phase locked loop 420.

The CDR core 400 generates a recovered clock having a fixed frequency by the reference phase locked loop 420 and recovers input data using the generated recovered clock.

According to a preferred embodiment of the present invention, the clock data decompressor is operated at a half rate, i.e., a frequency (N / 2 Hz) corresponding to half of an input data rate (N bps). Restore the data.

According to the present exemplary embodiment, the CDR core 400 includes a switching circuit 402, a first voltage controlled oscillator 1: GVCO1 404, a delay circuit 406, and a data recovery unit 408. can do.

The open / close circuit 402 generates an edge detection pulse (ED pulse) using input data, and separates the edge detection pulse into a set signal and a reset signal.

5 is a diagram showing a detailed configuration of the switching circuit 402 according to an embodiment of the present invention.

As shown in FIG. 5, the switching circuit 402 according to the present exemplary embodiment may include a delay cell 500, an edge detection pulse output unit 502, and a signal separation unit 504.

Referring to the operation of the open / close circuit 402, the delay cell 500 first delays the input data by a predetermined time, and the delayed data is input to the edge detection pulse output unit 502.

6 is a timing diagram of input data and pulses output through the delay cell 500 and the edge detection pulse output unit 502, respectively.

As shown in FIG. 6, the delay cell 500 delays by half (T / 2) of the input data period, and the edge detection pulse output unit 502 uses the data and input data delayed by half a period of the input data. An edge detection pulse that is 1/2 of the period is generated and output. The delay cell 500 may be defined as a half cycle delay cell in that it outputs a half cycle delayed pulse.

As illustrated in FIG. 5, the edge detection pulse output unit 502 outputs an edge detection pulse through a logical operation of input data and half cycle delayed data. In this case, the edge detection pulse output unit 502 may be configured as an exclusive OR gate, but is not limited thereto. The edge detection pulse output unit 502 may include an AND gate and a gate capable of various logic operations.

Conventionally, an open / close circuit of a clock data restorer operating at full rate includes only a delay cell and an edge detection pulse output unit as shown in FIG. 3, and the edge detection pulse is input to the first open / close oscillator GVCO1 as it is. (See FIG. 3).

Fig. 7 is a timing diagram shown when a conventional open / close circuit operating at full rate is operated at half rate.

As shown in FIG. 7A, when the open / close circuit of the clock data restorer operating at full rate is applied to the half rate as it is, as shown in FIG. 7B, a recovery clock for restoring the input data cannot be generated. There is a problem.

That is, in order to restore the input data, a recovery clock that oscillates in synchronization with the downward edge or the rising edge of the edge detection pulse should be generated. When the conventional switching circuit is applied to the half rate as it is, the synchronization with the edge detection pulse is performed as described above. Generated recovery clock cannot be generated.

Thus, according to an exemplary embodiment of the present invention, the signal detection unit 504 is additionally provided to the edge detection pulse output unit 502.

As shown in FIG. 5, the signal separator 504 according to the present embodiment may include a set signal output unit 504-1 and a reset signal output unit 504-2.

As shown in FIG. 5, the set signal output unit 504-1 and the reset signal output unit 504-2 may be configured as an AND gate, but are not necessarily limited thereto.

Hereinafter, the set signal output unit 504-1 and the reset signal output unit 504-2 will be described based on a case of an AND gate.

8 is a timing diagram in the case of using an open / close circuit and a GVCO structure to which the set / reset switching concept according to the present invention is applied.

According to the present embodiment, the set signal output unit 504-1 receives an edge detection pulse T / 2 ED pulse and a clock (hereinafter, referred to as a GVCO clock) from the first switching oscillator 404, and outputs a reset signal. The unit 504-2 includes an edge detection pulse T / 2 ED pulse and the inverted signal GVCO Clock_b of the GVCO clock.

As shown in FIG. 8, the set signal output unit 504-1 outputs a high signal when both the edge detection pulse and the GVCO clock are high, and the reset signal output unit 504-2 inverts the edge detection pulse. Outputs a high signal when all the GVCO clocks are high.

As described above, when the set / reset structure is provided to the switching circuit 402, the edge detection pulse is divided into a set signal and a reset signal.

The first open / close oscillator 404 according to the present exemplary embodiment outputs a recovered clock using the set signal and the reset signal.

As shown in FIG. 8, the up edge of the recovery clock is synchronized with the down edge of the set signal, and the down edge of the recovery clock is synchronized with the down edge of the reset signal.

As shown in FIG. 5, the first open / close oscillator 404 according to the present embodiment may include one or more delay cells 510-1 to 510-n and a recovery clock output unit 512 for outputting a recovery clock. Can be.

According to the present embodiment, the output of one of the delay cells 510-n becomes the GVCO clock input to the set signal output unit 504-1 and the reset signal output unit 504-2. As described above, the GVCO clock is input directly to the set signal output unit 504-1, and the inverted GVCO clock is input to the reset signal output unit 504-2.

The recovery clock output unit 512 may be defined as a delay cell, and generates a recovery clock using one of a set signal and a reset signal.

9 is a diagram illustrating a detailed configuration of a recovery clock output unit according to an embodiment of the present invention.

As shown in FIG. 9, the reconstructed clock output unit 512 according to the present exemplary embodiment may include a clock input terminal 900, a set signal input terminal 902, and a reset signal input terminal 904. do.

The clock from the delay cell 510-n is input to the clock input terminal 900. According to the present exemplary embodiment, when the state of the input clock is low (L), the set signal input terminal 902 is operated to oscillate. When the state of the input clock is high (H), the reset signal input terminal 904 is Will start to oscillate

As described above, the recovery clock output unit 512 generates a recovery clock using the set signal and the reset signal.

Referring to FIG. 4, data delayed by the recovery clock and delay circuit 406 is input to the data recovery unit 408, and the data recovery unit 408 restores the input data using the recovery clock.

According to the present embodiment, the data recovery unit 408 may include at least two D-flip flops 408-1 to 408-2.

The D-flip-flop is a circuit that outputs a value corresponding to the data input at the up edge or the down edge of the clock, and is called a data flip-flop and generally includes an SR flip-flop and an NOT gate.

According to the present embodiment, the first D flip-flop 408-1 uses an up edge trigger method, and the second D flip-flop 408-2 uses a down edge trigger method.

As described above, the recovery clock output unit 512 outputs a half-rate recovery clock using the set and reset signals. In this case, two D-flip-flops are configured to output data at different edges as in the present embodiment so that even when using a half-rate recovery clock, the same performance as at full rate can be achieved.

10 and 11 illustrate examples of recovering clock and data by the method according to the present invention.

As shown in FIGS. 10 to 11, the input data is restored using both the up edge and the down edge of the recovery clock, and different edge trigger schemes are used. Recovered to Recovered Data Phase A and Recovered Data Phase B).

The operation of the CDR core 400 as described above is performed in conjunction with the reference phase locked loop 420.

The reference phase locked loop 420 includes a second open / close oscillator 422, a frequency divider 424, a phase frequency detector 426, a charge pump 428, and a loop filter 430. ).

The frequency divider 424 divides the output frequency f _VCO of the second open / close oscillator 422 by the division ratio N to output a signal having a frequency of f _V.

The phase frequency detector 426 and the charge pump 428 detect a difference between the reference frequencies f _R and f _V and output a charge pulse. The signal adjusts the output frequency via the low band filter 430.

According to the present exemplary embodiment, the reference phase locked loop 420 is fixed such that the output frequency of the second open / close oscillator 422 becomes a frequency corresponding to half of the data rate, so that the clock and data are restored based on the half rate. do.

The present invention can guarantee the same bit error rate (BER) and CID Consecutive Identical Digit (BER) performance as the full rate, where the bit error rate (BER), which is one of the main characteristics of the burst mode clock data restorer, Refers to the number of bits in which an error occurs in the process of being delivered with respect to the number of bits received. In addition, one of the main characteristics of the burst mode clock data restorer, CID (Consecutive Identical Digit), is the number of bits that can recover data without error when consecutive “HIGH” or “LOW” data is input.

Although described above with reference to embodiments of the present invention, those of ordinary skill in the art various modifications and variations of the present invention without departing from the spirit and scope of the invention described in the claims below It will be appreciated that it can be changed.

Claims (10)

A half rate burst mode clock data decompressor comprising a reference phase locked loop,
An open / close circuit separating the edge detection pulse generated through the input data into a set signal and a reset signal;
A first open / close oscillator (GVCO) for outputting a recovery clock using the set signal and the reset signal;
A delay circuit for delaying the input data; And
It includes a data recovery unit for restoring the data delayed through the delay circuit to the first and second data having a different phase by using both the up edge and the white edge of the recovery clock,
The opening and closing circuit,
Generating the edge detection pulse by using the input data and the half-cycle delayed data of the input data, and separating the edge detection pulse into the set signal and the reset signal by using a GVCO clock input from the first switching oscillator. Clock Data Restorer. The method of claim 1,
The opening and closing circuit,
A half cycle delay cell that delays the input data by a half cycle;
An edge detection pulse output unit generating the edge detection pulse; And
And a signal separator for separating the edge detection pulse into the set signal and the reset signal. The method of claim 2,
And the edge detection pulse output unit is at least one of an exclusive logic gate or an AND gate. The method of claim 2,
The signal separation unit,
A set signal output unit configured to output the set signal by inputting the edge detection pulse and the GVCO clock; And
And a reset signal output unit configured to output the reset signal by inputting the edge detection pulse and the inverted signal of the GVCO clock. The method of claim 4, wherein
The first opening and closing oscillator,
One or more delay cells; And
A recovery clock output unit configured to output the recovery clock,
And the recovery clock output unit is a differential circuit including a set signal input terminal, a reset signal input terminal, and a clock input terminal to which a clock is input from the delay cell. The method of claim 5,
And the recovery clock output unit outputs a recovery clock using one of the set signal input terminal and the reset signal input terminal according to the state of the clock input through the clock input terminal. The method of claim 5,
And the GVCO clock is an output of one of the one or more delay cells. The method of claim 1,
The data recovery unit,
A first D-flip-flop that outputs data input from an up edge of the recovery clock among the data delayed through the delay circuit; And
And a second D-flip-flop that outputs data input at a lower edge of the recovery clock among the data delayed through the delay circuit. In the half rate burst mode clock data decompressor,
A clock data recovery core having an open / close circuit for separating an edge detection pulse generated through input data into a set signal and a reset signal, and a first open / close oscillator for outputting a recovery clock using the set signal and the reset signal; And
A reference phase locked loop for operating the first open / close oscillator at a preset frequency,
The reference phase locked loop includes a second open / close oscillator for outputting a fixed reference signal at a frequency corresponding to one half of the input data rate.
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