KR101099562B1 - Method for manufacturing of semiconductor device - Google Patents

Abstract

The present invention discloses a method for manufacturing a semiconductor device. According to an aspect of the present invention, there is provided a substrate having an SOI structure in which an oxide film is formed therein by implanting and thermally treating impurities into a silicon substrate, forming a device isolation layer on the substrate, forming a gate on the substrate, and forming the gate. Forming a source / drain region in both sides of the substrate, forming a trench for etching the substrate and the oxide layer on one side of the gate to expose the substrate under the oxide layer, and forming a lower electrode through the dielectric layer in the trench Forming an interlayer insulating film on the entire surface including the gate; forming a plate node contact hole exposing the substrate under the oxide film by etching the interlayer insulating film, the substrate, and the oxide film; and the plate node contact hole. Forming a plate node contact by depositing a conductive film on the It is characterized by including.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

1A to 1C are cross-sectional views of processes for explaining a method of manufacturing a conventional semiconductor device.

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

21 silicon substrate 22 oxide film

23 device isolation film 24 gate oxide film

25: gate conductive film 26: hard mask film

27: gate 28: source / drain region

29 spacer 30 trench

31 dielectric film 32 lower electrode

33: trench type capacitor 34: interlayer insulating film

35: plate node contact hole 36: bit line contact hole

37: bitline

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of arbitrarily adjusting a plate voltage of a capacitor by forming a trench type capacitor.

In general, a capacitor stores electric charges and supplies electric charges necessary for the operation of the semiconductor device. As the semiconductor device becomes highly integrated, the capacitance of the device becomes smaller while the unit cell size becomes smaller. This is an increasing trend.

As described above, as the semiconductor device is highly integrated, the capacitor is also required to be miniaturized, but there is a limit in charge storage, which makes it difficult to be highly integrated as compared with the size of the cell. In view of this, the structure for storing the charge of the capacitor has been changed in various ways, and the method of increasing the charge of the capacitor includes a method of using a material having a high dielectric constant, a method of decreasing the thickness of the dielectric material, and an increase of the surface area of the capacitor. And the like. In recent years, a method of increasing the surface area of a capacitor has been mainly used.

That is, the structure of the charge storage electrode of the capacitor is a stacked structure to obtain a large capacitor area by stacking a plurality of layers on a narrow planar surface and a trench of a certain depth in the semiconductor substrate after forming a trench of a certain depth And a trench structure for storing charges.                         

1A to 1C are cross-sectional views of processes for explaining a method of manufacturing a conventional semiconductor device.

As shown in FIG. 1A, a device isolation layer 2 is formed by applying a shallow trench isolation (STI) process on a semiconductor substrate 1, and then impurity ion implantation is performed in the substrate 1 to form a well region ( Not shown). Subsequently, after the gate oxide film 3 and the gate conductive film 4 are sequentially formed on the substrate 1, the gate conductive film 4 and the gate oxide film 3 are etched to form the gate 5.

As shown in FIG. 1B, source and drain regions 6a and 6b are formed by implanting impurity ions into the substrate on both sides of the gate 5. Next, after the nitride film is formed on the substrate product including the gate 5, the nitride film is etched to form spacers 7 on both side walls of the gate 5.

As illustrated in FIG. 1C, the trench 8 is formed by etching the substrate under one side of the gate 5 to a predetermined depth. Subsequently, after forming the dielectric film 9 on the trench 8 surface, the polysilicon film 10 is formed on the dielectric film 9 to form the trench capacitor 11.

Thereafter, an interlayer insulating layer 12 is formed on the substrate including the gate 5, and then the interlayer insulating layer 12 is etched to form a bit line contact hole 13, and the bit line contact hole 13. ) Is deposited to form a bit line 14.

In general, the P-type well region is used as GND in the memory cell, and the P-type well region has a voltage of 0V. However, since the trench type capacitor uses a P type well region as a plate node, the voltage of the plate node is equal to the voltage of the P type well region to be 0V. Accordingly, since the plate voltage of the trench capacitor becomes 0V, the sensing sensitivity of the device is reduced during the write operation of the device, thereby reducing the operating speed of the device.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of arbitrarily adjusting a plate voltage of a capacitor by forming a trench type capacitor.

According to an aspect of the present invention, there is provided a substrate having an SOI structure in which an oxide film is formed therein by implanting and thermally treating impurities into a silicon substrate, forming a device isolation film on the substrate, and forming a gate on the substrate. Forming a source / drain region in the substrate on both sides of the gate; forming a trench to expose the substrate under the oxide layer by etching the substrate and the oxide layer on one side of the gate; and forming a trench in the trench. Forming a lower electrode through the substrate; forming an interlayer insulating layer on the entire surface including the gate; etching the interlayer insulating layer, the substrate, and the oxide layer to form a plate node contact hole exposing the substrate under the oxide layer; And depositing a conductive film in the plate node contact hole. A characterized in that it comprises forming.

Here, the ion implantation is characterized in that injecting O2 ions at a dose of 1.5E18 / ㎠ or more.

The heat treatment is characterized in that carried out for 12 hours at a temperature of 1200 ~ 1400 ℃.

The dielectric film is formed as an oxide film by performing an oxidation process at a temperature of 750 ~ 850 ℃.

The lower electrode may be formed of a doped polysilicon film.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views of respective processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2A, the silicon substrate 21 is ion-implanted with impurities having a high concentration per unit area, and then heat-treated to prepare a substrate having an SOI structure in which an oxide film 22 is formed therein. At this time, the ion implantation implants O 2 ions at a dose of 1.5E18 / cm 2 or more. Here, the heat treatment is performed for 12 hours at a temperature of 1200 ~ 1400 ℃.

As shown in FIG. 2B, the device isolation layer 23 is formed by applying an STI process to the substrate 21, and then a well region (not shown) is formed by implanting impurities into the substrate 21. Next, impurities are implanted to adjust the threshold voltage of the transistor, and a heat treatment process is performed to activate the implanted impurities.

Subsequently, a gate oxide film 24, a gate conductive film 25, and a hard mask film 26 are sequentially formed on the substrate 21. Next, the hard mask layer 26, the gate conductive layer 25, and the gate oxide layer 24 are selectively etched to form the gate 27.

As illustrated in FIG. 2C, source / drain regions 28a and 28b are formed by implanting N-type impurities into the substrate on both sides of the gate 27. Subsequently, after the nitride film is formed on the substrate including the gate 27, the nitride film is etched to form spacers 29 on both side walls of the gate. In this case, the spacer 29 is formed to secure the process margin due to the excessive etching in the subsequent process of etching the substrate to a predetermined depth to form a trench.

As illustrated in FIG. 2D, a trench 30 exposing the substrate 21 under the oxide layer 22 is formed by etching the substrate 21 and the oxide layer 22 on the gate 27 to a predetermined depth. Next, after forming the dielectric film 31 on the trench 30, the lower electrode 32 is formed on the dielectric film 31. At this time, the dielectric layer 31 is formed as an oxide film by performing an oxidation process at a temperature of 750 ~ 850 ℃. Here, the lower electrode 32 is formed of a doped polysilicon film. Subsequently, the lower electrode 32 is etched back to expose the substrate 21 to form a trench capacitor 33.

As shown in FIG. 2E, after forming the interlayer insulating film 34 on the substrate product including the gate 27, the interlayer insulating film 34, the substrate 21, and the oxide film 22 are etched to expose the substrate. As a result, a plate node contact hole 35 exposing the substrate under the oxide layer 22 is formed. Subsequently, the interlayer insulating layer 34 is etched to expose the substrate to form bit line contact holes 36 connected to the source / drain regions 28a and 28b.

As illustrated in FIG. 2F, a bit line contact 38 and a plate node contact 37 are formed by filling a conductive film in the bit line contact hole 36 and the plate node contact hole 35.

As described above, the present invention forms an SOI substrate by forming an oxide film between silicon and silicon by performing high temperature heat treatment after ion implantation of impurities into the silicon substrate. Next, after forming the trench capacitor, the plate node contact hole and the bit line contact hole are sequentially formed, and the plate voltage of the capacitor can be arbitrarily adjusted by filling the conductive film in the bit line contact hole and the plate node contact hole. In addition, it is possible to increase the capacity of the capacitor by deepening the trench depth of the capacitor.

In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto. Those skilled in the art may have many modifications and variations without departing from the spirit of the present invention. I will understand.

 As described above, according to the present invention, after the ion implantation of impurities into the silicon substrate, a high temperature heat treatment is performed to form an SOI substrate, a trench capacitor to form a plate node contact hole, and a plate node contact hole. The plate voltage of the capacitor can be arbitrarily adjusted by embedding the conductive film in the. As a result, the coupling ratio between the bit line and the bit line decreases, so that the voltage of the bit line increases as the capacitance of the bit line decreases, thereby improving the driving capability of the device.

Claims (5)

Implanting impurities into the silicon substrate and performing heat treatment to prepare a substrate having an SOI structure having an oxide film formed therein; Forming an isolation layer on the substrate; Forming a gate on the substrate; Forming source / drain regions in the substrate on both sides of the gate; Etching the substrate and the oxide layer on one side of the gate to form a trench for exposing the substrate under the oxide layer; Forming a lower electrode through the dielectric layer through the trench; Forming an interlayer insulating film on the entire surface including the gate; Etching the interlayer insulating film, the substrate and the oxide film to form a plate node contact hole exposing the substrate under the oxide film; and And depositing a conductive film in the plate node contact hole to form a plate node contact. The method of claim 1, wherein the ion implantation implants O 2 ions at a dose of 1.5E18 / cm 2 or more. The method of claim 1, wherein the heat treatment is performed at a temperature of 1200 to 1400 ° C. for 12 hours. The method of claim 1, wherein the dielectric film is formed into an oxide film by performing an oxidation process at a temperature of 750 to 850 ° C. 7. The method of claim 1, wherein the lower electrode is formed of a doped polysilicon film.

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