KR101068136B1 - method for forming a gate electrode of semiconductor device - Google Patents

Abstract

A method of forming a gate electrode of a semiconductor device is disclosed. After forming a gate insulating film made of pure oxide film and a first gate conductive film made of polysilicon film on the substrate, patterning is performed to form a preliminary gate pattern using the first gate conductive film pattern and the gate insulating film pattern. A thin film containing nitride is continuously formed on the surface of the substrate, the sidewalls and the top surface of the preliminary gate pattern, and a second gate conductive film formed of a polysilicon film is formed on the surface of the thin film including the nitride. Then, the entire surface is etched to form a gate pattern having a thin film pattern including nitride and a second gate conductive layer pattern on sidewalls of the preliminary gate pattern and the preliminary gate pattern. Therefore, it is possible to compensate for the deterioration in characteristics due to the hot carriers concentrated at the end portions where the substrate and the gate pattern come into contact with each other.

Description

Method for forming a gate electrode of semiconductor device

BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing for demonstrating the characteristic fall by the hot carrier in the gate electrode manufactured by the conventional method.

2A to 2F are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device according to example 1 of the present invention.

The present invention relates to a method for forming a gate electrode of a semiconductor device, and more particularly, to a method for forming a gate electrode of a MOS transistor.

Recently, deterioration of semiconductor devices due to hot carriers has been caused by shortening of channel lengths in MOS transistors. In particular, as shown in FIG. 1, in the region A where the end portion of the gate insulating film pattern of the gate electrode 14 is in contact with the substrate 10, the deterioration of characteristics of the semiconductor device due to the hot carrier is concentrated. Reference numeral 12 is a trench device isolation layer.                         

Therefore, in order to compensate for the deterioration of the characteristics of the semiconductor device caused by the hot carrier, the structure of the MOS transistor is changed to an LDD structure, or an oxynitride film is applied as the gate insulating film.

However, when the channel length is very short, deterioration due to hot carriers frequently occurs in the LED structure. In addition, the application of the oxynitride film can greatly reduce the deterioration due to the hot carrier, but the application of the oxynitride film is not easy because it causes deterioration of the current characteristic (for example, the GM characteristic).

As described above, in the recent manufacture of semiconductor devices in which the channel length becomes very short, there is a problem in that the degradation of the characteristics due to the hot carrier cannot be easily solved.

It is an object of the present invention to provide a method for forming a gate electrode of a semiconductor device for sufficiently reducing the deterioration of characteristics due to hot carriers.

The gate electrode forming method of the present invention for achieving the above object,

Forming a gate insulating film made of a pure oxide film on the substrate;

Forming a first gate conductive film made of a polysilicon film on the gate insulating film;

Patterning the first gate conductive layer and the gate insulating layer to form a preliminary gate pattern using the first gate conductive layer pattern and the gate insulating layer pattern;

Continuously forming a thin film including nitride on a surface of the substrate and on sidewalls and top surfaces of a preliminary gate pattern;

Forming a second gate conductive film made of a polysilicon film on a surface of the thin film including the nitride; And

A thin film pattern including nitride on the sidewalls of the preliminary gate pattern and the preliminary gate pattern by removing the thin film including a nitride formed on the surface of the substrate and the upper surface of the preliminary gate pattern by performing an entire surface etching process; Forming a gate pattern having a second gate conductive layer pattern.

Here, the thin film including the nitride is preferably an oxynitride film or a silicon nitride film.

In addition, when the thin film including the nitride is an oxynitride layer, etching the part of the oxynitride layer pattern formed on the sidewall of the gate pattern and forming a metal silicide layer on the surface of the substrate and the upper surface of the gate pattern. The method may include electrically connecting the first gate conductive layer pattern and the second gate conductive layer pattern partially exposed by etching. In this case, some etching of the oxynitride layer pattern uses a HF solution diluted to 20 to 100: 1.

In the case where the thin film including the nitride is a silicon nitride film, etching the part of the silicon nitride film pattern formed on the sidewall of the gate pattern and forming a metal silicide film on the surface of the substrate and the upper surface of the gate pattern And electrically connecting the first gate conductive layer pattern and the second gate conductive layer pattern partially exposed by etching. At this time, it is preferable to use a phosphoric acid solution of 100 to 175 ℃ for some etching of the silicon nitride film pattern.

As described above, according to the present invention, a thin film containing nitride is applied to an area where the end portion of the gate insulating film pattern is in contact with the substrate. That is, the thin film containing nitride is applied to the region where the characteristic degradation due to the hot carrier is concentrated. Therefore, the deterioration of the characteristics of the semiconductor device due to the hot carrier can be sufficiently reduced.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

Example 1

2A to 2F are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device according to example 1 of the present invention.

Referring to FIG. 2A, the device isolation layer 22 is formed on the substrate 20. In this case, the device isolation layer 22 selects a trench device isolation layer because it is suitable for a semiconductor device having a fine pattern structure. Accordingly, the substrate 20 is divided into an active region and an inactive region. Then, ion implantation is performed to form a well (not shown) for imparting desired electrical characteristics to the substrate 20. Subsequently, a pure oxide film is formed on the substrate 20 as a gate insulating film. Subsequently, a polysilicon film is formed as a gate conductive film on the pure oxide film.

Then, the polysilicon film and the pure oxide film are patterned. The patterning is accomplished by etching using a photoresist pattern. In this manner, by performing the patterning, the preliminary gate pattern 24 including the pure oxide film pattern 24a and the polysilicon film pattern 24b is obtained on the active region of the substrate 20. At this time, the preliminary gate pattern 24 is formed so that its width is about 0.04 占 퐉 narrower than the set width of the gate pattern.

Referring to FIG. 2B, an oxynitride layer 26 is continuously formed on the surface of the substrate 20, the sidewalls and the upper surface of the preliminary gate pattern 24. In this case, the oxynitride layer 26 is formed using NO gas and has a thickness similar to that of the pure oxide layer pattern of the preliminary gate pattern 24. Then, a polysilicon film 28 is formed on the surface of the oxynitride film 26.

Referring to FIG. 2C, the polysilicon layer 28 and the oxynitride layer 26 formed on the surface of the substrate 20 and the upper surface of the preliminary gate pattern 24 are sequentially removed by etching the entire surface. Accordingly, the surface of the substrate 20 and the upper surface of the preliminary gate pattern 24 are exposed, and the oxynitride layer pattern 26a and the poly oxynitride layer 26 and the polysilicon layer remain on only sidewalls of the preliminary gate pattern 24. The silicon film pattern 28a is formed. Thus, the gate pattern 30 including the preliminary gate pattern 24, the oxynitride layer pattern 24a and the polysilicon layer pattern 28a formed on sidewalls of the preliminary gate pattern 24 is obtained.

As described above, an oxynitride layer pattern 26a is formed at an end portion of the gate pattern 30 in contact with the gate pattern 30 and the substrate 20. Therefore, the oxynitride film pattern 26a sufficiently prevents the characteristic degradation due to the hot carrier. In addition, since the oxynitride film pattern 26a is formed only at the end portion, the electrical characteristics are hardly affected.                     

Referring to FIG. 2D, ion implantation using the gate pattern 30 as an ion mask is performed. As a result, a shallow junction region 32 is formed in the substrate 20 adjacent to the gate pattern 30. Subsequently, spacers 34 are formed on sidewalls of the gate pattern 30. The spacer 34 may be obtained by selecting a nitride film and stacking and etching the entire surface. In addition, a buffer oxide layer (not shown) may be formed on the sidewall of the gate pattern 30 before the spacer 34 is formed.

Referring to FIG. 2E, ion implantation using the gate pattern 30 and the spacer 34 as an ion mask is performed. As a result, a source / drain pattern 36 is obtained on the substrate 20 adjacent to the spacer 34. Subsequently, a portion of the oxynitride layer pattern 26a formed on the sidewall of the gate pattern 30 is etched. At this time, the etching is used HF solution diluted to 50: 1. As such, the etching is performed to form grooves as in the region B. FIG. In particular, since the etching target is set to about 100 mV, the depth of the groove also has about 100 mV.

Referring to FIG. 2F, a metal silicide material is formed on the substrate, the spacer, and the gate pattern, and heat treatment is performed. Accordingly, material movement occurs on the substrate and the gate pattern. Therefore, the metal silicide layer 38 is formed on the surface of the substrate and the upper surface of the gate pattern. In this case, the gate conductive layer patterns partially exposed by the etching contact each other. That is, the gate conductive layer patterns are electrically connected to each other by being in contact with each other.

Thus, a completed gate electrode is formed on the substrate, and a transistor including the gate electrode and a source / drain pattern is formed.

Example 2

Example 2 is the same as Example 1 except that the oxynitride film which is the gate insulating film of Example 1 is replaced with the silicon nitride film. Here, the silicon nitride film is formed about twice as thick as the thickness of the pure oxide film pattern of the preliminary gate pattern. In addition, the silicon nitride film is formed by a low pressure chemical vapor deposition method adjusted to a temperature atmosphere of about 700 ℃ and a pressure atmosphere of about 200mTorr. In addition, a phosphoric acid solution of about 150 ° C. is used in etching to form a groove in the sidewall of the gate pattern.

As described above, in Example 2, a silicon nitride film pattern is formed at an end portion where the gate pattern and the substrate contact each other. Therefore, the silicon nitride film pattern sufficiently prevents the characteristic degradation caused by the hot carrier.

Therefore, according to this invention, the fall of the characteristic of the semiconductor device by a hot carrier can fully be prevented. Therefore, there is an effect that the electrical reliability of the semiconductor device is improved.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (7)

Forming a gate insulating film made of a pure oxide film on the substrate; Forming a first gate conductive film made of a polysilicon film on the gate insulating film; Patterning the first gate conductive layer and the gate insulating layer to form a preliminary gate pattern using the first gate conductive layer pattern and the gate insulating layer pattern; Continuously forming a thin film including nitride on a surface of the substrate and on sidewalls and top surfaces of a preliminary gate pattern; Forming a second gate conductive film made of a polysilicon film on a surface of the thin film including the nitride; And A thin film pattern including nitride on the sidewalls of the preliminary gate pattern and the preliminary gate pattern by removing the thin film including a nitride formed on the surface of the substrate and the upper surface of the preliminary gate pattern by performing an entire surface etching process; A method of forming a gate electrode of a semiconductor device, comprising forming a gate pattern having a second gate conductive film pattern. The method of claim 1, wherein the thin film including nitride is an oxynitride film. The method of forming a gate electrode of a semiconductor device according to claim 1, wherein the thin film containing nitride is a silicon nitride film. The method of claim 1, after the forming of the gate pattern, Etching a portion of the thin film including nitride formed on sidewalls of the gate pattern; And Electrically connecting the first gate conductive layer pattern and the second gate conductive layer pattern partially exposed by the etching by forming a metal silicide layer on a surface of the substrate and an upper surface of the gate pattern; The method of forming a gate electrode of a semiconductor device further comprising. 5. The method of claim 4, wherein the etching of the thin film including nitride comprises using an HF solution diluted to 20 to 100: 1. 6. delete The method of claim 4, wherein the etching of the thin film including nitride uses a phosphoric acid solution at 100 to 175 ° C. 6.

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