KR101055568B1 - Sensing Circuit of Flash Memory Device and Sensing Method of Flash Memory Device - Google Patents

Abstract

Disclosed are a sensing circuit of a flash memory device and a sensing method of a flash memory device capable of reducing a sensing error. The sensing circuit of the flash memory device is activated when the selected cell belongs to the first bit group to provide the first read verify voltage to the selected cell and the plurality of FCG reference cells, and to generate a cell voltage corresponding to the first read verify voltage. An FCG sensing unit that compares a plurality of FCG reference voltages to provide a first comparison result signal, and is activated when the selected cell belongs to the second bit group, and sequentially supplies the plurality of second read verify voltages to the selected cell and the SG reference cell. And an SG sensing unit and a first comparison result signal and a second comparison result signal which provide a second comparison result signal by comparing the cell voltage and the SG reference voltage generated corresponding to each second read verify voltage. And a decoder configured to perform decoding in response to the comparison result signal of to determine state information of the selected cell. Therefore, the sensing margin can be secured by performing the sensing in the unsaturated region of the voltage-current characteristic curve, thereby reducing the sensing error.

Flash Memory, MLC, Sensing, SG, FCG

Description

Sensing Circuit Of Flash Memory Device And Method For Sensing Flash Cell Of Flash Memory Device

The present invention relates to a flash memory device, and more particularly, a sensing circuit of a flash memory device and a sensing of a flash memory device, which can be applied to a multi-level cell (MLC) flash memory in which multi-bit data is stored in one memory cell. It is about a method.

Non-volatile memory is a device that can preserve stored information even when power supply is interrupted. In particular, flash memory is a representative device of nonvolatile memory, and has high integration and excellent data retention.

Flash memory may be classified into NOR and NAND types according to a connection state between a cell and a bit line. A NOR flash memory has a structure in which two or more cell transistors are connected in parallel to one bit line, and a NAND flash memory has a structure in which two or more cell transistors are connected in series to one bit line. NOR-type flash memory is disadvantageous for high integration because of high current consumption, but is suitable for a memory that requires high-speed operation, and NAND-type flash memory is advantageous for high integration, so it is easy to implement a large-capacity memory.

In addition, the flash memory is a single-level cell (SLC: short-term "SLC") flash memory and a multi-level cell (MLC), depending on the number of bits that can be stored in the unit memory cell Abbreviated as 'MLC').

SLC flash memory is a flash memory that stores one bit of data in one memory cell, also called a single-bit cell (SBC) memory. MLC flash memory can store more than 2 bits of data in one memory cell, also called multi-bit cell (MBC) memory. MLC flash memory enables high integration of memory since one memory cell can store multiple bits.

An important factor in MLC flash memory is the ability to accurately detect the electrons stored in the floating gate. Since the electrons stored in the floating gate of the flash memory cell change with the current-voltage characteristics of the flash transistor, the ability to accurately detect charge is very important in MLC flash memory.

The cell sensing method of the flash memory can be classified into a fixed constant-gate variable-current method and a variable-gate constant-current method.

The Fixed Constant-Gate Variable-Current method is a method of determining the state of a cell by applying a fixed gate voltage to a flash memory cell and comparing the flowing cell current with a plurality of reference currents. A method of determining a state of a cell by applying a variable voltage to the gate of the cell and comparing the corresponding cell current with one reference current. An example of the Variable-Gate Constant-Current method is the Stepped Gate method.

1 is a circuit diagram illustrating a general fixed constant-gate variable-current sensing method, and illustrates a sensing circuit of a 2-bit MLC flash memory cell having four storage levels.

Referring to FIG. 1, when a fixed gate voltage is applied to a flash memory cell 10 connected to a common word line and three reference cells 20 having different resistance values, the flash memory cell 10 and three reference cells are applied. A current flows through the 20, and the current of the flash memory cell 10 and the current of each reference cell 20 are compared in the corresponding comparator 30 and then input to the decoder 40 to decode the flash memory cell ( A bit indicating the state of 10) is output.

In FIG. 1, a sensing circuit of a 2-bit MLC flash memory has been described as an example. However, when a fixed constant-gate variable-current sensing method is used in a 3-bit or larger MLC flash memory, a current margin becomes saturated and a sensing margin is obtained. ) Will decrease.

FIG. 2 is a characteristic graph illustrating a saturation state of current levels occurring in an MLC flash memory of 3 bits or more.

As shown in FIG. 2, in an MLC flash memory of 3 bits or more, the number of current levels for determining the state of a flash memory cell is increased, thereby decreasing a margin between each current level, thereby increasing a sensing error. There is this.

A first object of the present invention for solving the above problems is to provide a sensing circuit of a flash memory device that can reduce the sensing error by securing a sensing margin.

In addition, a second object of the present invention is to provide a sensing method of the flash memory device.

In the sensing circuit of a flash memory device according to an aspect of the present invention for achieving the first object of the present invention described above, in the cell sensing circuit of a multilevel cell (MLC) flash memory, the selected cell is assigned to the first bit group. Is activated to provide a first read verify voltage to the selected cell and a plurality of Fixed Constant-Gate Variable-Current (FCG) reference cells, and reference a cell voltage and a plurality of FCGs generated corresponding to the first read verify voltage. The FCG sensing unit which compares the voltages and provides a first comparison result signal, and is activated when the selected cell belongs to the second bit group, sequentially plural second read verification voltages to the selected cell and the stepped gate reference cell. SG sensing unit and the first comparison result signal to provide a second comparison result signal by comparing the cell voltage and the SG reference voltage generated corresponding to each second read verification voltage And corresponding to any one of the comparison result signals supplied from the second comparison result signal and a decoder for determining the state information of the selected cell lines to perform decoding. The FCG sensing unit is activated in response to an activation control signal provided when the selected cell belongs to a first bit group to provide the first read verify voltage to the selected cell and the plurality of FCG reference cells; A plurality of FCG reference cells for generating a reference current corresponding to the first read verify voltage provided, a first current voltage converter for converting a current provided from the selected cell into the cell voltage, and a plurality of FCG reference cells A plurality of second current voltage converters respectively converting the provided currents into the plurality of FCC reference voltages, and a plurality of agents configured to compare the cell voltages and the plurality of FCG reference voltages to provide a plurality of first comparison result signals. 1 may comprise a comparator. The first read verify voltage may have a voltage greater than the largest threshold voltage among the threshold voltages belonging to the first bit group. The SG sensing unit is activated in response to an activation control signal provided when the selected cell belongs to a second bit group, and sequentially provides the plurality of second read verification voltages to the selected cell and the SG reference cell. And a SG reference cell generating a reference current corresponding to the plurality of second read verification voltages sequentially provided, a first current voltage converter converting a current provided from the selected cell into the cell voltage, and the SC And a third comparator for converting the current provided from the reference cell into the SG reference voltage and a second comparator for comparing the cell voltage and the SG reference voltage to provide the second comparison result signal. The decoder unit may include an FCG decoder that decodes the provided first comparison result signal to determine state information of the selected cell, and an SG decoder that decodes the provided second comparison result signal to determine state information of the selected cell. Can be. The FCG decoder may decode the provided first comparison result signal and provide only a bit, except for the MSB, among the bits belonging to the first bit group to the decoding output. The SG decoder may decode the provided second comparison result signal and provide only the bits, except for the MSB, among the bits belonging to the second bit group to the decoding output.

In addition, the sensing method of a flash memory device according to an aspect of the present invention for achieving the above-described second object of the present invention, the first bit group and the first state information corresponding to the threshold voltage distribution of the multi-level cell flash memory; Dividing into two bit groups, providing a bit group determination voltage for determining a bit group to which the selected cell belongs, and if the selected cell is not turned on in response to the bit group determination voltage, a fixed constant -Performing a gate variable-current (SG) sensing, performing stepped gate (SG) sensing when the selected cell is turned on in response to the bit group determination voltage, and any one of the FCG sensing or the SG sensing. And determining the state information of the selected cell by decoding the comparison result signal obtained through sensing of. The step of dividing the state information corresponding to the threshold voltage distribution of the multilevel cell flash memory into a first bit group and a second bit group may be classified according to a most significant bit of the state information. Providing a bit group determination voltage for determining a bit group to which the selected cell belongs, determining the bit group to a voltage that is smaller than a threshold voltage belonging to the first bit group and larger than a threshold voltage belonging to the second bit group. Can be provided as a voltage. When the selected cell is not turned on according to the bit group determination voltage, performing FCG sensing may include: setting a most significant bit to a first logic value, and setting a first read verify voltage to the selected cell and a plurality of cells. Providing a FCG reference cell, and a cell current generated from the selected cell corresponding to the first read verify voltage and a reference current generated from the plurality of FCG reference cells, respectively, as a cell voltage and a plurality of FCG reference voltages, respectively. And converting the cell voltage and the plurality of FCG reference voltages to generate a plurality of first comparison result signals and decoding the plurality of first comparison result signals. When the selected cell is turned on in response to the bit group determination voltage, performing a stepped gate (SG) sensing may include setting a most significant bit to a second logic value and setting a second read verify voltage to the selected cell. And providing an SG reference cell, and converting a cell current generated from the selected cell and a reference current generated from the SG reference cell to cell voltage and SG reference voltage, respectively, in correspondence with the second read verify voltage. And when the cell voltage is smaller than the SG reference voltage, increasing the second read verify voltage by a predetermined magnitude and adding a second read voltage increased by the preset magnitude to the selected cell and the SG reference cell. Providing a step may include. The sensing method of the multilevel cell flash memory may further include decoding a comparison result signal when the cell voltage is greater than the SG reference voltage.

According to the sensing circuit of the flash memory device and the sensing method of the flash memory device as described above, the bits corresponding to the plurality of threshold voltages are divided into a lower bit group and a higher bit group. By providing the bit group determination voltage to the cell, if the bit group to which the selected cell belongs belongs to the lower bit group, SG sensing detects state information of the selected cell, and if the selected cell belongs to the upper bit group, FCG sensing is performed. Detect state information of the selected cell.

Therefore, the sensing margin can be secured by performing the sensing in the unsaturated region of the voltage-current characteristic curve, thereby reducing the sensing error.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any of a plurality of related items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. Hereinafter, the same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted.

Example

3 is a conceptual diagram illustrating a sensing method of a flash memory device according to an exemplary embodiment of the present invention, and illustrates a NAND type 3 bit MLC flash memory in which 3 bits of data are stored in one memory cell.

As shown in FIG. 3A, a flash memory device according to an embodiment of the present invention has eight threshold voltage distributions because one cell can store three bits of data.

In the present invention, the bits corresponding to the eight threshold voltages are divided into a lower bit group and a higher bit group, and different sensing methods are applied to each bit group.

Specifically, after setting '111, 110, 101, and 100' as a lower bit group, and setting '011, 010, 001, and 000' as an upper bit group, a cell selected to read data belongs to. If it is determined that the selected cell belongs to the lower bit group by determining the bit group, data is read by applying a stepped gate (hereinafter, abbreviated as 'SG') sensing method, and the selected memory cell belongs to the upper bit group. When it is determined, data is read by using a fixed constant-gate variable-current (hereinafter, abbreviated as 'FCG') sensing method.

That is, in the sensing method of the flash memory device according to an embodiment of the present invention, the bits corresponding to each threshold voltage are divided into two bit groups, a lower bit group and an upper bit group, and then an SG sensing method is applied to the lower bit group. By applying the FCG sensing scheme to the upper bit group, sensing can be performed in an unsaturated region of the voltage-current characteristic curve as shown in FIG. 3 (b), thereby reducing data sensing errors. Can be.

4 illustrates a sensing circuit of a flash memory device according to an embodiment of the present invention.

Referring to FIG. 4, a data sensing circuit according to an embodiment of the present invention may be configured with an FCG sensing unit 100, an SG sensing unit 200, and a decoder unit 300, and is controlled by a controller (not shown). Based on either of the FCG sensing unit 100 or the SG sensing unit 200 is activated to sense the selected cell and then provide the sensed voltage to the decoder 300 and selected according to the output of the decoder 300 Determine the state of the cell (i.e. read the data).

In detail, the FCG sensing unit 100 may include an FCG voltage generator 110, three FCG reference cells 120, a current voltage converter 130, and three comparators 140.

The FCG voltage generator 110 is activated in response to a control signal of a controller (not shown), and generates an FCG voltage V _FCG having a predetermined size to generate three FCG reference cells 120 and selected cells 150. To the gate. The FCG voltage V _FCG may be the read verify voltage Vr8 illustrated in FIG. 3A.

In this case, the three FCG reference cells 120 and the selected cells 150 have currents corresponding to the FCG voltages V _FCG provided, respectively, and the three FCG reference cells 120 and the selected cells 150. The current voltage converters 130 and 160 respectively connected to the current voltage converters 130 and 160 generate voltages corresponding to the currents I _cell , I _ref1 , I _ref2, and I _ref3 , respectively, and provide them to the comparators 140.

The three comparators 140 compare the cell voltages V _cell provided by the current voltage converter 160 with the reference voltages V _ref1 , V _ref2, and V _ref3 provided by the three current voltage converters 130, respectively. The comparison result signals V _out1 , V _out2 and V _out3 are then provided to the FCG decoder 310 of the decoder 300.

The SG sensing unit 200 may be composed of an SG voltage generator 210, an SG reference cell 220, a current voltage converter 230, and a comparator 240.

The SG voltage generator 210 is activated in response to a control signal of a controller (not shown), and generates an SG voltage V _SG and provides it to the gates of the SG reference cell 220 and the selected cell 150. The SG voltage V _SG may be three read verify voltages Vr1, Vr2, and Vr3 illustrated in FIG. 3A, and the SG voltage generator 210 may set the 3 according to a preset time synchronization. Read verify voltages Vr1, Vr2, and Vr3 are sequentially provided to the gates of the SG reference cell 220 and the selected cell 150.

In this case, the SG reference cell 220 and the selected cell 150 have a current flowing corresponding to the read verify voltages Vr1, Vr2, and Vr3 sequentially provided, and the SG reference cell 220 and the selected cell 150 are provided. The current voltage converters 230 and 160 respectively connected to the currents I _ref4 and A voltage corresponding to I _cell ) is generated and provided to the comparator 240.

The comparator 240 compares the voltage V _cell provided by the current voltage converter 160 with the voltage V _ref4 provided by the current voltage converter 230, and then compares the comparison result signal V _out4 with the decoder 300. SG decoder 320).

The current voltage converter 140, the current voltage converter 160, and the current voltage converter 230 may all have the same configuration. A detailed configuration of the current voltage converters 140, 160, and 230 is illustrated in FIG. 5. It demonstrates in detail.

The decoder unit 300 may include an FCG decoder 310 and an SG decoder 320. The FCG decoder 310 performs decoding corresponding to the comparison result signals V _out1 , V _out2, and V _out3 provided from the comparator 140, and outputs decoded signals DH2, DH1, and DH0. Here, the decoded signals DH2, DH1, and DH0 represent cell state information of any one of cell state information belonging to an upper bit group 011, 010, 001, and 000, and all bits belonging to an upper bit group are all MSBs. Since the Most Significant Bit is '0', the FCG decoder 310 outputs only two bits (ie, DH1 and DH0) to the decoding channel corresponding to the input comparison result signals V _out1 , V _out2 and V _out3 . .

In addition, the SG decoder 320 performs decoding corresponding to the comparison result signal V _out4 provided from the comparator 240 and outputs the decoded signals DL2, DL1, and DL0. Here, the decoding signals DL2, DL1, and DL0 indicate any one cell state information among cell state information belonging to the lower bit groups 111, 110, 101, and 100, and all bits belonging to the lower bit group are all MSBs. Since SG decoder 320 outputs only two bits (ie, DL1 and DL0) as a decoded signal corresponding to the input comparison result signal V _out4 .

In the data sensing circuit shown in FIG. 4, the FCG voltage generator 110 and the SG voltage generator 210 are activated in response to a control signal (eg, an enable signal) in a controller (not shown). After applying the read verify voltage Vr4 shown in (a) of FIG. 3 as a bit group determination voltage for determining the bit group to which the selected cell belongs, the FCG voltage generation unit 110 and according to whether the selected cell is turned on; Any one of the SG voltage generators 210 may be activated.

5 is a circuit diagram illustrating a detailed configuration of the current voltage converter shown in FIG. 4. Since the current voltage converters 130, 160, and 230 shown in FIG. 4 all have the same configuration, the current voltage converter 130 will be described with reference to FIG.

Referring to FIG. 5, the current voltage converter 130 according to an embodiment of the present invention may include a power supply unit 131, a voltage stabilizer 133, a pull up unit 135, and a pull down unit. The unit 137, a load transistor TN4, and a resistor R may be included.

The power supply unit 131 may include an inverter and a PMOS transistor TP1, and the transistor TP1 is turned on in response to the sense amplifier enable signal SAE to provide the power VDD.

The voltage stabilizer 133 may include a PMOS transistor TP2 and an NMOS transistor TN1, and performs a function of stabilizing the voltage VDD supplied to the power supply 131.

The pull-up unit 135 may be composed of two PMOS transistors TP3 and TP4. The transistor TP3 is turned on in response to the sense amplifier disable signal / SAE, and the transistor TP4 is turned on in response to the voltage V _R formed in proportion to the incoming cell current I _cell . by driving the current and controls the current (I _s) the driving of the load transistor (TN4).

The pull-down unit 137 may be composed of NMOS transistors TN2 and TN3. The transistor TN2 is turned on or off in response to the sense amplifier disable signal / SAE to control the on-off operation of the load transistor TN4. For example, when the sense amplifier disable signal / SAE is logic high, the transistor TN2 is turned on so that the load transistor TN4 is turned off regardless of the operations of the transistors TP4 and TN3. The transistor TN3 is turned on corresponding to the voltage V _R formed in proportion to the incoming cell current I _cell to drive the current to control the driving of the current I _s of the load transistor TN4.

The load transistor TN4 controls the output voltage V _out by driving the current I _s in proportion to the voltage V _GS formed corresponding to the operation of the pull-up unit 145 and the pull-down unit 147.

The resistor R distributes the voltage V _R according to the magnitude of the current I _cell .

Referring to FIG. 5, the overall operation of the current voltage converter 130 will be described. First, when the cell current I _cell is inputted to the current voltage converter 130, the size of the input cell current I _cell . In proportion, a voltage V _R is formed.

The formed voltage V _R is commonly provided to the gates of the transistor TP4 of the pull-up unit 145 and the transistor TN3 of the pull-down unit 147, and the current driving of the transistors TP4 and TN3 is performed. The ability is determined according to the voltage V _R provided above.

The voltage V _GS between the gate and the source of the load transistor TN4 is determined according to the current driving capability of the transistors TP4 and TN3 and corresponds to the determined voltage V _GS . The magnitude of the current I _S flowing through the source of the load transistor TN4 is determined.

In addition, the magnitude of the output current I _out is determined according to the magnitude of the current I _S flowing through the source of the load transistor TN4, and is output in proportion to the magnitude of the determined output current I _out . The magnitude of the voltage V _out is determined.

For example, when the size of the input cell current I _cell is large, the voltage V _R increases accordingly, and the current driving capability of the transistor TN3 corresponds to the increased voltage V _R. As a result, the current driving capability of the transistor TP4 is reduced, so that the voltage V _GS between the gate and the source of the load transistor TN4 is reduced. In addition, the current driving capability of the load transistor TN4 decreases corresponding to the reduced voltage V _GS , so that the current I _S decreases and the output current I _out increases so that the output voltage V _out increases. do.

6 shows a detailed circuit and a truth table of the FCG decoder shown in FIG.

4 to 6, each comparator 140 includes a cell voltage V _cell provided by the current voltage converter 160 and reference voltages V _ref1 , V _ref2 , which are provided by the corresponding current voltage converter 130. After comparing V _ref3 ), the comparison signal V _out1 , V _out2, and V _out3 are output.

For example, when the state of the selected cell is '001', each comparator 140 outputs '0, 1, 1' as the comparison result signals V _out1 , V _out2, and V _out3 , and the FCG decoder 310. ) Outputs '10' to the output values DH1 and DH0 decoded corresponding to the _input comparison result signals V _out1 , V _out2 and V _out3 .

Here, the FCG sensing unit 100 performs data sensing on an upper bit group (that is, 011, 010, 001, and 000) in the threshold voltage distribution diagram shown in FIG. Since the status bits are all MSBs ('0'), the FCG decoder 310 corresponds to the input comparison result signals V _out1 , V _out2, and V _out3 to the other two bits except for MSB (ie, DH1 and DH0). Decode only.

7 is a flowchart illustrating a sensing method of a flash memory device according to an embodiment of the present invention, FIG. 8 is a flowchart illustrating details of an FCG sensing step illustrated in FIG. 7, and FIG. 9 is a SG illustrated in FIG. 7. This is a flowchart showing the details of the sensing step.

7 to 9, first, a target cell to be read is selected from a cell array of a flash memory (step 710), and a bit group determination voltage is provided to the selected cell to determine a bit group to which the selected cell belongs (step 710). Step 720). Here, the bit group determination voltage may be determined as a voltage (eg, Vr4) that is larger than a threshold voltage belonging to the lower bit group and smaller than a threshold voltage belonging to the upper bit group, as shown in FIG. 3A.

Thereafter, it is determined whether the selected cell is turned on in accordance with the bit group determination voltage provided as described above (step 730), and the cell sensing method is applied based on this.

That is, when the cell current I _cell does not flow because the selected cell is not turned on, it is determined that the selected cell belongs to an upper bit group (ie, 011, 010, 001, 000), and the selected cell is selected through FCG sensing. In operation 740, when the selected cell is turned on and a cell current I _cell flows, the selected cell is determined to belong to a lower bit group (that is, 111, 110, 101, and 100). The selected cell is sensed (step 760).

In detail, when FCG sensing is performed on the selected cell, DH2 is set to '0' because MSBs of bits belonging to an upper bit group are all '0' (step 741).

The preset read verify voltage is then provided to the selected cell and three FCG reference cells (step 742). The preset read verify voltage may be set to a voltage (eg, Vr8) having a voltage larger than a threshold voltage distribution belonging to an upper bit group, as shown in FIG. 3A.

Thereafter, in the selected cell and the three FCG reference cells, a cell current I _cell and a reference cell current I _ref1 , I _ref2 , and I _ref3 corresponding to the read verification voltages respectively flow, and the current-voltage voltage converting unit flows through the cell. The current I _cell and the reference cell currents I _ref1 , I _ref2 , and I _ref3 are _converted into the cell voltage V _cell and the reference voltages V _ref1 , V _ref2 , and V _ref3 (step 743).

Thereafter, the comparator compares the cell voltage V _cell and the reference voltages V _ref1 , V _ref2 , and V _ref3 to provide comparison result signals V _out1 , V _out2, and V _out3 (step 744), and the FCG decoder. Decodes the comparison result signal (V _out1 , V _out2 and V _out3 ) (step 745) to determine two bits DH1 and DH0 excluding the MSB (step 780).

Alternatively, when performing SG sensing on the selected cell, DL2 is set to '1' because the MSBs of the bits belonging to the higher bit group are all '1' (step 761).

The preset read verify voltage is then provided to the selected cell and the SG reference cell (step 762). Here, the voltage first provided to the selected cell and the SG reference cell is the lowest read verify voltage (ie, Vr1) among the read verify voltages Vr1, Vr2, and Vr3 belonging to the lower bit group illustrated in FIG. 3A. Can be provided.

Thereafter, in the selected cell and the SG reference cell, a cell current I _cell and a reference cell current I _ref4 corresponding to the read verification voltage are respectively supplied, and the current-voltage voltage converter is connected to the cell current I _cell and the reference. The cell current I _ref4 is _converted into the cell voltage V _cell and the reference voltage V _ref4 (step 763).

Thereafter, the comparator compares the cell voltage V _cell and the reference voltage V _ref4 (step 764), and if the cell voltage V _cell is greater than the reference voltage V _ref4 , decodes the comparison result signal ( In step 766, two bits excluding the MSB (ie, DL1 and DL0) are determined (step 780), and when the cell voltage V _cell is smaller than the reference voltage V _ref4 , the read verify voltage is increased by a predetermined magnitude. After increasing (step 765), the process returns to step 762. Here, the voltage increased by performing step 765 may be Vr2 shown in FIG. 3A, and even when Vr2 is applied as a result of performing steps 762 to 764, the cell voltage V _cell is referred to above. If it is smaller than the voltage V _ref4 , the read verification voltage is increased to Vr3 by performing step 765, and then steps 762 to 764 are performed again.

  That is, in the SG sensing method, a read verify voltage Vr1 shown in FIG. 3A is provided to the selected cell and the SG reference cell to determine the state of the selected cell as '111' when current flows in the selected cell. When a current flows in the selected cell when the voltage Vr2 is provided, the state of the selected cell is determined as '110'. When the current flows in the selected cell when the read verify voltage Vr3 is provided, the state of the selected cell is determined as '101'. do. When no current flows in the selected cell when the read verify voltage Vr3 is provided, the state of the selected cell is determined as '100'.

Also, in the SG sensing method, since the time for which the read verification voltages having different sizes are provided to the selected cells is different, the corresponding SG decoder must be implemented. For example, in the SG sensing method, when the read verification voltages Vr1, Vr2, and Vr3 are applied to 1usec, 3usec, and 5usec, respectively, when the current flows in the cell selected in 1usec, the output of the SG decoder should be '111', and in 3usec, If the current flows in the selected cell, the output of the SG decoder should be '110'. If the current flows in the cell selected in 5usec, the output of the SG decoder should be '101'. Alternatively, if no current flows in the selected cell after 5usec, the output of the SG decoder should be '100'.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

1 is a circuit diagram illustrating a general fixed constant-gate variable-current sensing method.

FIG. 2 is a characteristic graph illustrating a saturation state of current levels occurring in an MLC flash memory of 3 bits or more.

3 is a conceptual diagram illustrating a sensing method of a flash memory device according to an embodiment of the present invention.

4 illustrates a sensing circuit of a flash memory device according to an embodiment of the present invention.

5 is a circuit diagram illustrating a detailed configuration of the current voltage converter shown in FIG. 4.

6 shows a detailed circuit and a truth table of the FCG decoder shown in FIG.

7 to 9 are flowcharts illustrating a sensing method of a flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: FCG sensing unit 110: FCG voltage generation unit

120: FCG reference cell 130: current voltage converter

140: comparator 200: SG sensing unit

210: SG voltage generator 220: SG voltage generator

230: current voltage converter 240: comparator

300: decoder 310: FCG decoder

320: SG decoder

Claims (13)

In the cell sensing circuit of a multilevel cell (MLC) flash memory, When the selected cell belongs to the first bit group, the selected cell is activated to provide a first read verify voltage to the selected cell and a plurality of Fixed Constant-Gate Variable-Current (FCG) reference cells, and generate the first read verify voltage corresponding to the first read verify voltage. An FCG sensing unit configured to compare the cell voltages and the plurality of FCG reference voltages to provide a first comparison result signal; When the selected cell belongs to the second bit group, the selected cell is activated to sequentially provide the plurality of second read verify voltages to the selected cell and the stepped gate reference cell, and generate a cell voltage corresponding to each of the second read verify voltages. And an SG sensing unit configured to compare the SG reference voltages and provide a second comparison result signal. And And a decoder configured to determine decoding state information of the selected cell by decoding corresponding to any one of the first comparison result signal and the second comparison result signal. The method of claim 1, wherein the FCG sensing unit An FCG voltage generator configured to be activated in response to an activation control signal provided when the selected cell belongs to a first bit group to provide the first read verify voltage to the selected cell and the plurality of FCG reference cells; A plurality of FCG reference cells for generating a reference current corresponding to the first read verify voltage provided; A first current voltage converter converting a current provided from the selected cell into the cell voltage; A plurality of second current voltage converters respectively converting currents respectively provided from the plurality of FCG reference cells into the plurality of FCC reference voltages; And And a plurality of first comparators configured to compare the cell voltage and the plurality of FCG reference voltages to provide a plurality of the first comparison result signals. The method of claim 2, wherein the first read verify voltage is And a voltage greater than the largest threshold voltage among the threshold voltages belonging to the first bit group. The method of claim 1, wherein the SG sensing unit An SG voltage generator configured to be activated in response to an activation control signal provided when the selected cell belongs to a second bit group to sequentially provide the plurality of second read verification voltages to the selected cell and the SG reference cell; An SG reference cell generating a reference current corresponding to the plurality of second read verify voltages sequentially provided; A first current voltage converter converting a current provided from the selected cell into the cell voltage; A third current voltage converter converting a current provided from the SG reference cell into the SG reference voltage; And And a second comparator for comparing the cell voltage and the SG reference voltage to provide the second comparison result signal. The method of claim 1, wherein the decoder An FCG decoder to decode the provided first comparison result signal to determine state information of the selected cell; And And an SG decoder which decodes the provided second comparison result signal to determine state information of the selected cell. The method of claim 5, wherein the FCG decoder And decoding the provided first comparison result signal to provide only a bit, except for MSB, as a decoding output among the bits belonging to the first bit group. The method of claim 5, wherein the SG decoder And decoding the provided second comparison result signal and providing only bits except for MSB among the bits belonging to the second bit group as a decoding output. In the sensing method of a multilevel cell flash memory, Dividing state information corresponding to a threshold voltage distribution of the multilevel cell flash memory into a first bit group and a second bit group; Providing a bit group determination voltage for determining a bit group to which the selected cell belongs; Performing Fixed Constant-Gate Variable-Current (FCG) sensing when the selected cell is not turned on in response to the bit group determination voltage; Performing stepped gate (SG) sensing when the selected cell is turned on in response to the bit group determination voltage; And And determining the state information of the selected cell by decoding a comparison result signal obtained through the sensing of either the FCG sensing or the SG sensing. The method of claim 8, wherein the classifying the state information corresponding to the threshold voltage distribution of the multilevel cell flash memory into a first bit group and a second bit group includes: And classifying according to the most significant bit of the state information. The method of claim 8, wherein providing a bit group determination voltage for determining a bit group to which the selected cell belongs, And providing a voltage smaller than a threshold voltage belonging to the first bit group and greater than a threshold voltage belonging to the second bit group as the bit group determination voltage. The method of claim 8, wherein if the selected cell is not turned on according to the bit group determination voltage, performing FCG sensing may include: Setting the most significant bit to a first logic value; Providing a first read verify voltage to the selected cell and a plurality of FCG reference cells; Converting a cell current generated from the selected cell and a reference current generated from the plurality of FCG reference cells, respectively, into a cell voltage and a plurality of FCG reference voltages corresponding to the first read verify voltage; Generating a plurality of first comparison result signals by comparing the cell voltage and the plurality of FCG reference voltages; And And decoding the plurality of first comparison result signals. The method of claim 8, wherein when the selected cell is turned on in response to the bit group determination voltage, performing a stepped gate (SG) sensing may include: Setting the most significant bit to a second logic value; Providing a second read verify voltage to the selected cell and an SG reference cell; Converting a cell current generated from the selected cell and a reference current generated from the SG reference cell, respectively, into a cell voltage and an SG reference voltage corresponding to the second read verify voltage; If the cell voltage is less than the SG reference voltage, increasing the second read verify voltage by a predetermined magnitude; And And providing a second read voltage increased by the predetermined magnitude to the selected cell and the SG reference cell. The method of claim 12, wherein the sensing method of the multilevel cell flash memory comprises: And if the cell voltage is greater than the SG reference voltage, decoding the comparison result signal.

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