KR101048692B1 - Cluster type deposition equipment and method of manufacturing thin film transistor using same - Google Patents

Abstract

The present invention relates to a cluster type deposition apparatus capable of performing a deposition process without vacuum break by performing heat treatment before and after deposition in one cluster, and a method of manufacturing a thin film transistor using the same. Among them, the cluster deposition apparatus of the present invention includes a loader in which a plurality of substrates are inserted and waiting, a preheating chamber for preheating the substrate transferred from the preloader, and a plurality of films for depositing a predetermined film on the substrate transferred from the preheating chamber. It comprises a PECVD chamber, an annealing chamber for annealing the substrate transferred from the one PECVD chamber, and an unloader that receives the substrate exiting from the annealing chamber and outflows it to the outside.

Cluster type, Plasma Enhanced Chemical Vapor Deposition (PECVD), Annealing, Preheating, Hydrogenation, Vacuum break

Description

Cluster Type Deposition Equipment and Manufacturing Method of Thin Film Transistor Using the Same {Cluster Type of Apparatus for Deposition and Method for Manufacturing Thin Film Transistors Using the same}

1 is a cross-sectional view showing a typical top gate thin film transistor

Figure 2a is a schematic diagram showing a conventional clustered deposition equipment

FIG. 2B is a schematic diagram of each PECVD chamber in FIG. 2A

3 is a view showing a conventional hydrogenation process

4 is a view showing a conventional cleaning process

5 is a schematic diagram showing a clustered deposition apparatus of the present invention and a driving sequence thereof

Description of the Related Art [0002]

50: controller 51, 52, CVD chamber

53, 54, 55: sputter chamber 56: central chamber

57: robot arm 60: cassette

70: substrate 81, 82, 92, 93: plate

83, 84, 96: valve 91: magnetic

94: bonding material 95: target

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a cluster type deposition apparatus capable of performing a deposition process without vacuum break by performing heat treatment before and after deposition in a cluster, and a method of manufacturing a thin film transistor using the same.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELD), and vacuum fluorescent (VFD) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as the substitute for CRT (Cathode Ray Tube) for the use of mobile image display device because of the excellent image quality, light weight, thinness, and low power consumption. In addition to the use of the present invention has been developed in various ways such as a television and a computer monitor for receiving and displaying broadcast signals.

In order to use such a liquid crystal display as a general screen display device in various parts, it is a matter of how high quality images such as high definition, high brightness and large area can be realized while maintaining the characteristics of light weight, thinness and low power consumption. Can be.                         

A general liquid crystal display device may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel has a predetermined space and is bonded to the lower substrate, the upper substrate, and the upper and lower parts. It consists of the liquid crystal layer injected between the board | substrates.

Here, the lower substrate (TFT array substrate) has a plurality of gate lines arranged in one direction at regular intervals, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, and the gate lines A plurality of pixel electrodes formed in a matrix form and a plurality of thin film transistors configured to transfer signals of the data line to each pixel electrode are formed in a plurality of pixel electrodes formed in a matrix form in each of the pixel regions defined by intersections with the data lines. .

The upper substrate (color filter array substrate) includes a black matrix layer for blocking light in portions other than the pixel region, a color filter layer representing color colors of R, G, and B, and a front surface including the color filter layer. The formed common electrode is formed.

The driving principle of the general liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the arrangement of molecules can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal by optical anisotropy, thereby representing image information.                         

Recently, the development of the active matrix type thin film transistor (TFT) liquid crystal display device among the various forms of the liquid crystal display device has been remarkable.

In the active matrix thin film transistor liquid crystal display device (TFT LCD), an electrode of an individual pixel forming a screen of a display device is controlled using a transistor, wherein the thin film transistor is formed on a lower substrate including a semiconductor layer. .

On the other hand, depending on where the gate electrode is located with respect to the semiconductor layer is divided into a top gate (bottom gate) method and a bottom gate (bottom gate) method. That is, when the gate electrode is located above the semiconductor layer, it is called a top gate, and when the gate electrode is located below the semiconductor layer, it is called a bottom gate.

Hereinafter, a conventional cluster deposition apparatus and a method of manufacturing a thin film transistor using the same will be described with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a typical top gate thin film transistor.

As shown in FIG. 1, a general top gate thin film transistor includes a semiconductor layer 11 formed in a predetermined pattern on a substrate 10, and a gate insulating layer 12 formed on an entire surface of the substrate 10 including the semiconductor layer 11. And a gate electrode 13 formed on a portion of the gate insulating layer 12 corresponding to a predetermined region on the semiconductor layer 11, an insulating film 14 formed on the entire surface including the gate electrode 13, and the A contact hole is formed in the insulating layer 14 and the gate insulating layer 12 to form source / drain electrodes 15a and 15b connected to both sides of the semiconductor layer 11.                         

Hereinafter, a method of manufacturing a general top gate thin film transistor will be described with reference to the drawings.

First, a silicon oxide film (SiO ₂ ) is formed over the substrate 10 as a buffer layer (omitted), and a semiconductor layer 11 is formed on a predetermined region on the buffer layer.

The semiconductor layer 11 is formed by depositing amorphous silicon, dehydrogenation, polysilicon by laser recrystallization, and then patterning.

Subsequently, the gate insulating layer 12 is deposited on the buffer layer including the semiconductor layer 11.

Subsequently, metals for gate electrodes such as aluminum (Al), aluminum alloy, chromium (Cr), tungsten (W), molybdenum (Mo), antimony (Sb), and tantalum (Ta) are deposited on the gate insulating layer 12. After that, it is selectively removed to form the gate electrode 13. In general, the gate electrode 13 may have a two-layer structure of an aluminum-containing metal and a molybdenum-containing metal, and a two-layer structure of an aluminum-containing metal and, in some cases, chromium. For the etching process, a metal should be used without any form of undercut or problem in annealing after ion doping.

Subsequently, by injecting hydrogen onto the entire surface and introducing the hydrogen into the semiconductor layer 11, hydrogen holds a dangling bond of silicon (Si) that remains uncrystallized after crystallization of the semiconductor layer 11. In order to increase the mobility of the semiconductor layer 11.

In the hydrogenation annealing process, the substrate 10 including the gate insulating layer 12 is heat-treated at about 400 ° C. in an oven for about 4 hours.

Subsequently, an ion implantation process for forming a p-type device or an n-type device on the gate insulating film 12 including the gate electrode 13 is performed.

At this time, the gate electrode 13 serves as a mask to form high concentration impurity regions 11a and 11b according to each type in portions of the semiconductor layer 11 corresponding to both sides of the gate electrode 13.

Subsequently, an interlayer insulating layer 14 is deposited on the entire surface including the gate electrode 13.

The interlayer insulating film 14 is usually formed by depositing a silicon oxide film or a silicon nitride film. In some cases, the interlayer insulating film 14 may be formed by applying a photosensitive organic film. In this case, since the etching process for patterning does not need to be performed separately, the process can be simplified.

Subsequently, the interlayer insulating layer 14 is selectively removed to form contact holes exposing the high concentration impurity regions 11a and 11b of the semiconductor layer.

Subsequently, a source / drain electrode metal is entirely deposited on the entire surface by filling the contact hole, and then selectively removed to form the source / drain electrodes 15a and 15b. The source / drain electrode metal is formed of aluminum (Al), aluminum alloy, chromium (Cr), tungsten (W), molybdenum (Mo), antimony (Sb), tantalum (Ta), or the like.                         

Subsequently, a transparent conductive film of a front ITO material is deposited on the interlayer insulating layer 14 including the source / drain electrodes 15a and 15b, and selectively removed to remove the pixel electrode connected to the drain electrode 15b. To form.

Hereinafter, a method of depositing a gate insulating film on the substrate 10 including the semiconductor layer 11, a hydrogenation annealing process, and the like will be described with reference to the accompanying drawings.

Figure 2a is a schematic diagram showing a conventional clustered deposition equipment, Figure 2b is a schematic diagram of the interior of each PECVD chamber of Figure 2a.

As shown in FIG. 2A, the conventional clustered deposition apparatus has a transfer chamber 38 in the center thereof, and a plurality of plasma enhanced chemical vapor deposition (PECVD) chambers 31, 32, 33, and 34 are disposed around the substrate. It includes a preheating chamber 37 which preheats the incoming / outgoing loader 35, the unloader 36 and the introduced substrate 10 before the PECVD process.

In the conventional cluster type deposition apparatus, the substrate (see 10 in FIG. 1) drawn into the transfer chamber 38 from the loader 34 (see 10 in FIG. 1) enters the preheating chamber 37 (②) before the deposition process. The substrate 10 is preheated to a constant temperature, and then enters one of the plurality of CVD chambers 31, 32, 33, 34 (③) to complete the PECVD process, and then passes through the transfer chamber 38 again. (④) It is made in such a way that the unloader 35 exits (⑤).

Here, the movement of the substrate 10 is controlled by the movement of the robot arm (39) located in the center, the substrate (cassette) 60 in the loader 35 and the unloader 36, respectively ) And then one by one exit, or come in one by one to fill the cassette 60 and then to the next process line.

The movement of the substrate 10 using the robot arm 39 in the cluster deposition apparatus described above is controlled by the controller 40.

The buffer chamber 50 is a chamber in which the PECVD chambers 101, 102, 103, 104 which perform the next process, or the substrate 10 which is waiting before entering the transfer chamber 112 remain.

In the conventional clustered deposition equipment, a plurality of PECVD chambers 31, 32, 33, and 34 are configured, and each of the PECVD chambers 31, 32, 33, and 34 is configured as follows.

As shown in FIG. 2B, the PECVD chamber includes first and second plates 21 and 22 spaced apart from each other by a predetermined interval, and the substrate 10 is mounted on the second plate 22. Then, RF (Radio Frequency) power is applied to the first plate 21, the second plate 22 is grounded, and a plasma region is formed in a space between the first and second plates 21 and 22. Form. That is, the reaction gas of the vapor deposition film to be deposited in the chamber and the atmosphere gas are introduced into the plasma state in the space between the first and second plates 21 and 22, and then on the substrate 10. Allow to be deposited.

3 is a view showing a conventional hydroprocessing process.

As shown in FIG. 3, the conventional hydroprocessing process is performed in units of lots 75 in which 10 to 25 substrates 10 are mounted in an oven 80. At this time, the temperature is about 400 ℃, the running time proceeds for about 4 hours, the atmosphere gas is H ₂ , N ₂ .

As such, it takes a long time for the hydrogenation process to be carried out in the oven for several hours. After the deposition process is performed, the substrate 10 exits the cluster-type deposition equipment, and thus the substrate is cleaned at least once. (10) This is because, after cooling, the heat treatment time for the actual hydrogen annealing takes longer as well as the time for preheating the substrate 10 again.

4 is a view showing a conventional cleaning process.

As shown in FIG. 4, the conventional cleaning process transfers the substrate 10, and sprays the DI solution onto the substrate 10 through the upper spray nozzle 24 to perform the cleaning. Such a cleaning process may be performed by, for example, performing a process of hydrogen annealing through an oven after a deposition process of an insulating layer using a cluster deposition apparatus, and when a vacuum break occurs between the two processes, Since the atmosphere meets impurities and accumulates on the substrate, the process proceeds at the time of removing the impurities.

The conventional clustered deposition apparatus as described above and a method of manufacturing a thin film transistor using the same have the following problems.

First, the cluster type deposition equipment for the deposition process and the oven for the hydrogen annealing (heat treatment) are provided separately, the cost burden for the equipment was large.

Secondly, the deposition process and the hydrogenation annealing process were performed separately, which took a long time to manufacture the liquid crystal display.

Third, since the deposition process and the hydrogenation annealing process is performed in separate equipment, a vacuum break is generated between the processes. The vacuum break occurs to expose the substrate to the atmosphere, which requires a cleaning process before the hydrogen annealing process, and it takes a long time to wait outside the vacuum chamber no matter how precise the cleaning process (consisting of about 20 minutes) is performed. Inevitably, deterioration of properties between the film deposited by the deposition equipment and the film formed after the hydrogenation heat treatment is inevitable.

This eventually causes a problem of deteriorating the characteristics of the polysilicon thin film transistor that requires hydrogenation heat treatment.

The present invention has been made to solve the above problems to provide a cluster-type deposition equipment and a method of manufacturing a thin film transistor using the same process to proceed the deposition process without vacuum break by performing a pre-deposition heat treatment in one cluster, The purpose is.

The cluster type deposition apparatus of the present invention for achieving the above object is a predetermined number of loaders to which a plurality of substrates are inserted and waiting, a preheating chamber for preheating the substrate transferred from the loader, and a substrate transferred from the preheating chamber. And a plurality of PECVD chambers for depositing a film, an annealing chamber for annealing the substrate transferred from the one PECVD chamber, and an unloader for receiving the substrate exiting from the annealing chamber and outflowing it to the outside. have.                     

The predetermined film is an inorganic insulating film.

The insulating film is SiNx or SiO ₂ .

In addition, the method of manufacturing a thin film transistor using the cluster type deposition apparatus of the present invention includes the steps of introducing a substrate with a semiconductor layer formed from the outside to the loader, and transmitting the substrate in a preheating chamber to preheat the substrate; Transferring the substrate to any one of a plurality of deposition chambers to deposit an interlayer insulating film on the substrate; transferring the substrate to an annealing chamber to anneal the substrate to hydrogenate the semiconductor layer; It is characterized by including the step of outflowing through the unloader.

The semiconductor layer is crystallized and patterned.

The annealing takes place within 15 minutes.

The annealing is performed at a temperature of 380 ~ 450 ℃.

The annealing is performed in an atmosphere of N ₂ and H ₂ .

Hereinafter, a cluster type deposition apparatus and a method of manufacturing a thin film transistor using the same according to the present invention will be described with reference to the accompanying drawings.

5 is a schematic diagram showing a cluster type deposition apparatus of the present invention and a driving sequence thereof.

As shown in FIG. 5, the cluster deposition apparatus 100 of the present invention is characterized in that the preheating chamber 105 and the annealing chamber 106 are formed in one cluster.

That is, the cluster deposition apparatus 100 of the present invention includes a transfer chamber 112 located at the center, a plurality of PECVD chambers 101, 102, 103, 104 formed around the transfer chamber 112, and a plurality of transfer chambers 112. The loader 107 to which the substrate 130 is drawn in and waiting, the unloader 108 to which the substrate 130 exiting from one PECVD chamber 101, 102, 103, 104 is transferred, and the transfer chamber 112 A robot arm 115 positioned within the robot arm 115 to move the substrate 130 between the loader / unloader 107, 108, the transfer chamber 112 and the plurality of PECVD 101, 102, 103, 104, and the substrate ( It comprises a controller (not shown) for controlling the movement of the 130.

Here, the buffer chamber 110 is a chamber waiting when the substrate 130 moves between the transfer chamber 112 and the other process chambers.

The cluster type deposition apparatus is driven as follows.

First, the substrate 130 is drawn into the loader 107. The substrate 130 is in a state in which a semiconductor layer (not shown) is patterned and formed.

Subsequently, the substrate 130 is discharged from the cassette 120 one by one through the robot arm 115 in the loader 107 and transferred to the transfer chamber 112 (①), in the transfer chamber 112 The substrate 130 is transferred to the preheating chamber 105 to be preheated.

In this case, the temperature preheated shall be 350 degrees C or less.

Subsequently, the preheated substrate 130 is transferred to any one of the first, second, third, and fourth PECVD chambers 101, 102, 103, and 104 in the order in which the preheated substrate 130 is introduced. Each PECVD chamber 101, 102, 103, 104 generates a gas in a plasma state and deposits it on the substrate 130.

At this time, the deposition flows into the reaction gas and the atmosphere gas of the film to be deposited, the preheated substrate 130 to maintain the temperature, that is, the condition that takes about 2 minutes per substrate at a temperature of about 350 ℃ Is done.

The film deposited on the substrate 130 is an inorganic insulating film such as SiO ₂ or SiNx.

Subsequently, when the PECVD process is completed on each substrate 130 in any one of the first, second, third, and fourth PECVD chambers 101, 102, 103, 104, the process returns to the annealing chamber 106. The substrate 130 is transferred (④).

In the annealing chamber 106 using a heat transfer atmospheric gas of N _2, H ₂ etc. of the gas and the reaction gas to H ₂ at a temperature of 380 ~ 450 ℃ under a pressure of 1 ~ 100Torr and annealing the substrate (130) . At this time, the hydrogen (H) flowing through the heat treatment process the dangling bond remaining after the ion injection into the semiconductor layer through the insulating film deposited on the substrate 130 is captured.

Subsequently, the annealing chamber 106 again passes out of the transmission chamber 112 (⑤) and out through the unloader 108 (⑥).

The first to fourth PECVD chambers 101, 102, 103, 104, the preheating chamber 105, and the annealing chamber 106 are all vacuum chambers.

As described above, the cluster deposition apparatus according to the present invention includes both the preheating chamber 105 and the annealing chamber 106 in one cluster to pattern the semiconductor layer, and then proceeds with the formation of a gate insulating film and a hydrogenation process. By all proceeding to the same cluster, a vacuum break is not applied between the (gate) insulating film formation process and the hydrogenation process, and the thin film transistor is formed so that the cleaning process that is required when the vacuum break occurs is omitted. In addition, it is possible to omit the use of the oven equipped in the annealing process.

The manufacturing method of the thin film transistor using the cluster type deposition apparatus of the present invention described above is as follows.

The cluster deposition apparatus of the present invention is an apparatus that may be used in forming a top gate thin film transistor as an example.

That is, after the semiconductor layer is formed on the substrate, the substrate may be introduced into the cluster deposition apparatus of the present invention to deposit the entire gate insulating film, and then perform a heat treatment for hydrogenating the gate insulating film.

In addition, the cluster deposition apparatus of the present invention may be used when forming a bottom gate thin film transistor.

In this case, first, the gate electrode is formed on the substrate, and then the gate insulating film is deposited on the entire surface. Subsequently, after forming a semiconductor layer on the gate insulating film to correspond to the upper portion of the gate electrode, the substrate is introduced into the cluster deposition equipment of the present invention. Subsequently, after depositing the interlayer insulating film using the cluster type deposition apparatus of the present invention, the step of subsequently performing a heat treatment for hydrogenating the interlayer insulating film may be continuously performed.                     

As described above, the cluster deposition apparatus of the present invention can use both a top gate type or a bottom gate type thin film transistor, and all of them can perform a heat treatment process for depositing an insulating layer and hydrogenation thereof using one cluster.

Through such a process, using the cluster deposition apparatus of the present invention, a vacuum break time does not occur between the insulating film deposition process and the heat treatment process for hydrogenation, and thus, the deposition process and the heat treatment process for hydrogenation are performed. Since no cleaning process is required in the intervening phase, impurities are not contaminated at the interface between the deposited film and the film formed thereafter, thereby improving the interface characteristics and improving the efficiency of the process.

The deposition equipment of the present invention as described above has the following effects.

First, by integrating the insulation film deposition equipment and the heat treatment equipment for hydrogenation in one cluster, it is possible to avoid the use of a separate oven for the hydrogenation heat treatment process. Thus, the cost for using the equipment is reduced.

Second, the vacuum break between the two processes can be omitted by continuously performing an insulating film deposition process and a heat treatment process for hydrogenation in one cluster. Omission of the vacuum brake means omission of the cleaning process between the two processes, thus shortening the process time.

Third, the omission of the vacuum brake also means that the substrate is not exposed to the atmosphere between the two processes, whereby more stable interfacial properties of the deposited insulating film are expected.

Fourth, the above and vacuum break omission can be expected to ultimately improve the yield and characteristics of the thin film transistor.

Claims (8)

A loader in which a substrate on which a plurality of semiconductor layers are formed is drawn and waiting; A preheating chamber for preheating the substrate transferred from the loader; A plurality of PECVD chambers for depositing an insulating film on the substrate transferred from the preheating chamber; A substrate on which the insulating film is deposited feed on the semiconductor layer from one of said plurality of PECVD chamber, a reaction gas H ₂ and the atmosphere gas N _2, to a hydrogenation annealing by H ₂ H ₂ The residual dangling bonds and An annealing chamber for coupling; And an unloader which receives the substrate exiting from the annealing chamber and flows it out to the outside. delete The method of claim 1, The insulating film is a cluster-type deposition equipment, characterized in that SiNx or SiO ₂ . In the manufacturing method of a thin film transistor using a cluster deposition apparatus equipped with a loader / unloader, a plurality of deposition chambers, a preheating chamber and an annealing chamber, Introducing a substrate on which the semiconductor layer is formed from the outside into the loader; Transferring the substrate in a preheating chamber to preheat the substrate; Transferring the substrate to any one of a plurality of deposition chambers to deposit an interlayer insulating film of SiNx or SiO ₂ component on the substrate; The substrate is transferred to an annealing chamber and the substrate on which the interlayer insulating film is deposited on the semiconductor layer is hydrogenated and annealed by reaction gas H ₂ and atmospheric gases N ₂ and H ₂ to capture the remaining dangling bonds of the semiconductor layer. Giving step; And discharging the substrate to the outside through the unloader. The method of claim 4, wherein The semiconductor layer is a method of manufacturing a thin film transistor using a cluster deposition equipment characterized in that the crystallization and patterning is made. The method of claim 4, wherein The annealing is a thin film transistor manufacturing method using a cluster type deposition equipment, characterized in that made within 15 minutes. The method of claim 4, wherein The annealing is a method of manufacturing a thin film transistor using a cluster type deposition equipment, characterized in that at a temperature of 380 ~ 450 ℃. delete

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