KR101045036B1 - Ic tester - Google Patents

Ic tester Download PDF

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KR101045036B1
KR101045036B1 KR1020070055950A KR20070055950A KR101045036B1 KR 101045036 B1 KR101045036 B1 KR 101045036B1 KR 1020070055950 A KR1020070055950 A KR 1020070055950A KR 20070055950 A KR20070055950 A KR 20070055950A KR 101045036 B1 KR101045036 B1 KR 101045036B1
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pin
pins
semiconductor integrated
integrated circuit
tester
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KR20080091693A (en
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히데키 나가누마
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요코가와 덴키 가부시키가이샤
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 핀 사이가 완전히 단락(short)되어 있지 않더라도, 핀간의 단락을 검출할 수 있는 반도체 집적 회로의 시험 방법 및 IC 테스터를 실현하는 것을 목적으로 한다.An object of the present invention is to realize a test method and an IC tester for a semiconductor integrated circuit capable of detecting a short circuit between pins even if the pins are not completely shorted.

본 발명에 따르면, 복수개의 핀을 구비하는 반도체 집적 회로의 핀간의 단락을 검출하는 반도체 집적 회로의 시험 방법에 있어서, IC 테스터 또는 반도체 집적 회로가, 반도체 집적 회로의 소정의 핀에 펄스 신호 또는 스텝 신호를 발생시키고, IC 테스터가, 소정의 핀에 인접하는 반도체 집적 회로의 핀으로부터의 파형에 의해 핀간 단락의 판정을 행하는 것을 특징으로 한다.According to the present invention, in a method for testing a semiconductor integrated circuit for detecting short circuits between pins of a semiconductor integrated circuit having a plurality of pins, the IC tester or the semiconductor integrated circuit includes a pulse signal or a step at a predetermined pin of the semiconductor integrated circuit. A signal is generated, and the IC tester determines the short circuit between pins by the waveform from the pin of the semiconductor integrated circuit adjacent to the predetermined pin.

반도체 집적 회로, IC 테스터, 단락, 펄스 신호, 스텝 신호 Semiconductor Integrated Circuits, IC Testers, Short Circuit, Pulse Signal, Step Signal

Description

ＩＣ 테스터{IC TESTER}IC tester {IC TESTER}

도 1은 본 발명의 일실시예를 나타낸 구성도이다.1 is a block diagram showing an embodiment of the present invention.

도 2는 DUT(10)의 인접 핀의 파형 예를 나타낸 도면이다.2 is a diagram illustrating an example of waveforms of adjacent pins of the DUT 10.

도 3은 종래의 IC 테스터의 구성을 나타낸 도면이다.3 is a view showing the configuration of a conventional IC tester.

도 4는 DUT(10)의 구체적 구성을 나타낸 도면이다.4 is a diagram illustrating a specific configuration of the DUT 10.

도 5는 DUT(10)의 주요부 확대 단면도이다.5 is an enlarged cross-sectional view of an essential part of the DUT 10.

[부호의 설명][Description of the code]

10: DUT 12: 반도체 집적 회로10: DUT 12: semiconductor integrated circuit

13: 핀 40: 시험부13: pin 40: test part

41: 펄스 발생부 42: 측정부41: pulse generator 42: measurement unit

[특허 문헌 1] 일본국 특개평 5(1993)-190637호 공보[Patent Document 1] Japanese Unexamined Patent Publication No. 5 (1993) -190637

본 발명은, 반도체 집적 회로, 예를 들면, 액정 구동 드라이버의 핀간의 단 락을 검출하는 반도체 집적 회로의 시험 방법 및 IC 테스터에 관한 것이다.The present invention relates to a test method and an IC tester of a semiconductor integrated circuit for detecting a short circuit between pins of a semiconductor integrated circuit, for example, a liquid crystal drive driver.

IC 테스터는, 반도체 집적 회로에 신호를 출력하고, 반도체 집적 회로의 출력에 의해 불량 여부의 판정을 행하고 있다. 또한, IC 테스터는, 예를 들면, 상기 특허 문헌 1에 나타나 있는 바와 같이, 반도체 집적 회로의 핀간 단락의 판정을 행하고 있다.The IC tester outputs a signal to the semiconductor integrated circuit, and determines whether or not it is defective by the output of the semiconductor integrated circuit. In addition, the IC tester determines the short circuit between pins of the semiconductor integrated circuit, for example, as described in Patent Document 1.

이와 같은 장치를 도 3에 나타내 설명한다.Such an apparatus is shown and described in FIG.

도 3에 있어서, 피시험 대상(이하 DUT로 약칭)(10)은, 예를 들면, 액정 구동 드라이버이며, 도 4에 나타낸 바와 같이, TAB 테이프(11)에 반도체 집적 회로(12)가 탑재되고, 반도체 집적 회로(12)가 복수개의 핀(13)에 배선(도시하지 않음)을 통하여 접속되어 있다. DC 측정부(20)는 IC 테스터에 설치되고, DUT(10)의 핀마다 접속하고, 직류 전압 출력 또는 직류 전류 측정을 행한다. 제어부(30)는, DC 측정부(20)의 제어와 핀간 단락의 판정을 행한다. 핀간 저항 R은, DUT(10)의 핀 사이의 저항 성분을 나타낸다. 그리고, 핀간 단락 이외의 시험을 위한 구성은 생략하고 있다.In FIG. 3, the test target (hereinafter abbreviated as DUT) 10 is, for example, a liquid crystal drive driver. As shown in FIG. 4, the semiconductor integrated circuit 12 is mounted on the TAB tape 11. The semiconductor integrated circuit 12 is connected to the plurality of pins 13 through a wiring (not shown). The DC measuring unit 20 is installed in an IC tester, connected to each pin of the DUT 10, and performs DC voltage output or DC current measurement. The control part 30 performs control of the DC measuring part 20, and determines the short circuit between pins. The pin resistance R represents a resistance component between the pins of the DUT 10. In addition, the structure for tests other than an inter-pin short circuit is abbreviate | omitted.

이와 같은 장치의 핀간 단락 시험 동작을 설명한다. DC 측정부(20)가, 제어부(30)의 제어에 의해, DUT(10)의 소정의 핀에 전압 출력하고, 상기 소정의 핀에 인접하는 DUT(10)의 핀을 DC 측정부(20)가 측정한다. 핀간 단락일 경우 핀간 저항 R이 낮으며, 핀간 단락이 아닐 경우 핀간 단락 저항 R이 높아지므로, 제어부(30)는, DC 측정부(20)가 측정하는 전류가 소정값보다 클 때, 핀간 단락이라고 판정한다.The pin-to-pin short test operation of such a device will be described. The DC measuring unit 20 outputs a voltage to a predetermined pin of the DUT 10 by the control of the control unit 30, and the DC measuring unit 20 applies a pin of the DUT 10 adjacent to the predetermined pin. To measure. The pin-to-pin resistance R is low when the pin is shorted and the pin-to-pin short-circuit R is high when the pin is not shorted. Determine.

최근, 액정 디스플레이의 대형화, 화소수의 증가에 의해, 액정 구동 드라이버가 약 700핀으로 다핀화되고, 핀간 피치가 약 30㎛로, 핀 사이의 간극은 약 10㎛로 좁아지고 있다. 그러므로, 도 5의 (a)에 나타낸 바와 같이, 먼지나 티끌 등의 이물질(14)이 핀 사이에 부착되어, 완전 단락 상태를 만들 뿐만 아니라, 도 5의 (b)에 나타낸 바와 같이, 이물질(14)과 다른 쪽의 핀 사이에 근소한 간극이 형성되지만 접촉하지 않는 상태가 되어, 시험 시에는 핀간 단락이 발생하지 않으므로, DUT(10)이 우량품으로 판정되어도, 나중에, 상기 근소한 간극이 단락되어, 불량이 되는 문제점이 있었다.In recent years, due to the increase in the size of the liquid crystal display and the increase in the number of pixels, the liquid crystal drive driver has been multi-pinned to about 700 pins, the pitch between pins is about 30 mu m, and the gap between the pins is narrowed to about 10 mu m. Therefore, as shown in Fig. 5A, foreign matters 14, such as dust and dust, are attached between the pins to create a completely shorted state, and as shown in Fig. 5B, the foreign matter ( 14) and the other pin are formed, but the state is not in contact with each other, and since the short circuit between pins does not occur during the test, even if the DUT 10 is judged as a good product, the small gap is shorted later. There was a problem of becoming defective.

따라서, 본 발명의 목적은, 완전히 단락되어 있지 않더라도, 핀간 단락의 검출을 행할 수 있는 반도체 집적 회로의 시험 방법 및 IC 테스터를 실현하는 것이다.Accordingly, it is an object of the present invention to realize a test method and an IC tester for a semiconductor integrated circuit capable of detecting an inter-pin short circuit even if not completely shorted.

전술한 바와 같은 과제를 달성하기 위하여, 제1 발명은,In order to achieve the above object, the first invention,

복수개의 핀을 구비하는 반도체 집적 회로의 핀간 단락을 검출하는 반도체 집적 회로의 시험 방법에 있어서,In the test method of a semiconductor integrated circuit for detecting an inter-pin short circuit of a semiconductor integrated circuit having a plurality of pins,

IC 테스터 또는 상기 반도체 집적 회로가, 상기 반도체 집적 회로의 소정의 핀에 펄스 신호 또는 스텝 신호를 발생시키고,An IC tester or the semiconductor integrated circuit generates a pulse signal or a step signal at a predetermined pin of the semiconductor integrated circuit,

상기 IC 테스터가, 상기 소정의 핀에 인접하는 상기 반도체 집적 회로의 핀으로부터의 파형에 의해 핀간 단락의 판정을 행하는 것을 특징으로 한다.The IC tester performs the determination of an inter-pin short circuit by a waveform from a pin of the semiconductor integrated circuit adjacent to the predetermined pin.

제2 발명은, 제1 발명에 있어서,2nd invention is 1st invention,

판정 타이밍에서 파형이 판정값보다 클 때, IC 테스터가 핀간 단락이라고 판정하는 것을 특징으로 한다.When the waveform at the determination timing is larger than the determination value, the IC tester determines that it is an inter-pin short.

제3 발명은,3rd invention,

복수개의 핀을 구비하는 반도체 집적 회로를 시험하는 IC 테스터에 있어서,An IC tester for testing a semiconductor integrated circuit having a plurality of pins,

상기 반도체 집적 회로의 소정의 핀에 펄스 또는 스텝 신호를 발생시키고, 상기 소정의 핀에 인접하는 인접 핀의 파형에 의해 핀간 단락을 판정하는 시험부가 설치된 것을 특징으로 한다.And a test section for generating a pulse or a step signal to a predetermined pin of the semiconductor integrated circuit and determining a short circuit between pins based on a waveform of an adjacent pin adjacent to the predetermined pin.

제4 발명은, 제3 발명에 있어서,4th invention is a 3rd invention,

판정 타이밍에서 파형이 판정값보다 클 때, 시험부가 핀간 단락이라고 판정하는 것을 특징으로 한다.When the waveform at the determination timing is larger than the determination value, the test section determines that it is an inter-pin short circuit.

제5 발명은, 제3 발명 또는 제4 발명에 있어서,In 5th invention, in 3rd invention or 4th invention,

시험부는,The test part,

소정의 핀에 펄스 또는 스텝 신호를 발생시키는 펄스 발생부와,A pulse generator for generating a pulse or step signal to a predetermined pin;

인접 핀을 측정하는 측정부Measuring part measuring adjacent pins

를 구비한다.It is provided.

[실시예][Example]

이하 본 발명을, 도면을 사용하여 상세하게 설명한다. 도 1은 본 발명의 일실시예를 나타낸 구성도이다.EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated in detail using drawing. 1 is a block diagram showing an embodiment of the present invention.

도 1에 있어서, DUT(10)는, 예를 들면, 액정 구동 드라이버이며, 도 4에 나 타낸 바와 같이, TAB 테이프(11)에 반도체 집적 회로(12)가 탑재되고, 반도체 집적 회로(12)가 복수개의 핀(13)에 배선(도시하지 않음)을 통하여 접속되어 있다. 시험부(40)는, IC 테스터에 설치되고, DUT(10)의 복수개의 핀에 전기적으로 접속되고, DUT(10)의 소정의 핀에 펄스를 발생시키고, 상기 소정의 핀에 인접하는 인접 핀의 파형에 의해 핀간 단락을 판정한다. 시험부(40)에는, DUT(10)의 핀마다 펄스 발생부(41) 및 측정부(42)가 설치되고, 또한 제어부(43)가 설치된다. 펄스 발생부(41)는, 예를 들면 액티브 로드 회로이며, 소정의 핀에 펄스를 발생시킨다. 측정부(42)는, 예를 들면 A/D 변환부이며, 인접 핀을 측정한다. 제어부(43)는, 펄스 발생부(41) 및 측정부(42)를 제어하고, 측정부(42)의 측정 결과에 따라, 핀간 단락의 판정을 행한다. 핀간 용량 C는, DUT(10)의 핀 사이의 용량 성분을 나타낸다. 그리고, 핀간 단락 이외의 시험을 위한 구성은 생략되어 있다.In FIG. 1, the DUT 10 is, for example, a liquid crystal drive driver. As shown in FIG. 4, the semiconductor integrated circuit 12 is mounted on the TAB tape 11, and the semiconductor integrated circuit 12 is provided. Is connected to the plurality of pins 13 via a wiring (not shown). The test unit 40 is installed in an IC tester, electrically connected to a plurality of pins of the DUT 10, generates a pulse at a predetermined pin of the DUT 10, and is adjacent to the predetermined pin. The pin-to-pin short circuit is determined by the waveform of. The test unit 40 is provided with a pulse generator 41 and a measurement unit 42 for each pin of the DUT 10, and a control unit 43 is provided. The pulse generator 41 is an active load circuit, for example, and generates a pulse to a predetermined pin. The measurement part 42 is an A / D conversion part, for example, and measures an adjacent pin. The control part 43 controls the pulse generator 41 and the measurement part 42, and determines the short circuit between pins according to the measurement result of the measurement part 42. FIG. The pin-to-pin capacitance C represents the capacitance component between the pins of the DUT 10. In addition, the structure for tests other than an inter-pin short circuit is abbreviate | omitted.

이와 같은 장치의 동작을 설명한다. 도 2는, DUT(10)의 인접 핀의 파형예를 나타낸 도면이다.The operation of such a device will be described. 2 is a diagram illustrating an example of waveforms of adjacent pins of the DUT 10.

펄스 발생부(41)가, 제어부(43)의 제어에 의해, DUT(10)의 소정의 핀에 펄스를 출력하고, 상기 소정의 핀의 인접하는 DUT(10)의 핀을 측정부(42)가 측정한다. 핀간 단락이 아닌 경우, 도 2의 파형 a와 같이 되고, 도 5의 (b)에 나타낸 바와 같이, 이물질(14)과 다른 쪽의 핀 사이에 근소한 간극은 형성되지만 접촉하지 않을 경우, 도 2의 파형 b와 같이 되므로, 제어부(43)는, 스트로브(판정 타이밍)에서, 측정부(42)의 측정 결과가 판정값보다 클 때, 핀간 단락이라고 판정한다. 제어부(43)는, 스트로브로에서, 측정부(42)의 측정 결과가 판정값보다 작으면, 핀간 단 락이라고 판정하지 않는다. 여기서, 측정 결과가 판정값과 동일한 경우에 핀간 단락 판정은 핀간 단락 혹은 핀간 비단락 중 어느쪽으로 판정되어도 된다. 그리고, 핀간 단락이 완전하게 이루어질 경우, 파형 b와 같이 변화하지 않지만, 펄스가 그대로 측정부(42)에 입력되므로, 판정값보다 크게 되는 것은 말할 나위도 없다. 즉, 핀간 단락으로 판정된다.The pulse generating unit 41 outputs a pulse to a predetermined pin of the DUT 10 under the control of the control unit 43, and measures the pin of the adjacent DUT 10 of the predetermined pin. To measure. In the case of no short-circuit between the pins, it becomes the same as the waveform a of FIG. 2, and as shown in FIG. 5B, a small gap is formed between the foreign material 14 and the other pin, but the contact of FIG. Since it becomes like waveform b, the control part 43 determines with a strobe (judgment timing) that it is a short circuit between pins, when the measurement result of the measuring part 42 is larger than a determination value. The control part 43 does not determine that it is a short circuit between pins, when the measurement result of the measuring part 42 is smaller than a determination value by the strobe. Here, in the case where the measurement result is the same as the determination value, the pin-to-pin short circuit determination may be determined by either pin-to-pin short circuit or pin-to-pin short circuit. When the pin-to-pin short circuit is completed, it does not change as in the waveform b, but it goes without saying that the pulse is directly input to the measuring section 42, so that it becomes larger than the determination value. That is, it is determined as a short circuit between the pins.

이와 같이, 펄스 발생부(41)가 DUT(10)의 소정의 핀에 펄스를 부여하고, 측정부(42)가 소정의 핀에 인접하는 DUT(10)의 인접 핀을 측정하고, 이 측정 결과에 따라, 제어부(43)가 핀간 단락의 판정을 행하므로, 완전히 단락되어 있지 않더라도, 핀간 단락을 검출할 수 있다.In this way, the pulse generator 41 applies a pulse to a predetermined pin of the DUT 10, and the measuring unit 42 measures an adjacent pin of the DUT 10 adjacent to the predetermined pin. Accordingly, since the control section 43 determines the inter-pin short circuit, it is possible to detect the inter-pin short circuit even if it is not completely shorted.

그리고, 본 발명은 이에 한정되지 않고, 측정부(42)는 A/D 변환부인 것을 나타냈으나, 컴퍼레이터나, A/D 변환부와 상기 A/D 변환부의 출력을 입력하는 디지털 컴퍼레이터의 조합으로 이루어질 수도 있다. 이 경우, 제어부(43)에서, 핀간 단락의 판정은 불필요하게 된다. 또한, 측정부(43) 내에, 핀간 단락을 판정하는 구성이 포함될 수도 있다.Incidentally, the present invention is not limited thereto, but the measurement unit 42 is an A / D conversion unit, but the comparator or the digital comparator for inputting the output of the A / D conversion unit and the A / D conversion unit is used. It may be made in combination. In this case, in the control section 43, determination of the short circuit between pins becomes unnecessary. In addition, the measurement unit 43 may include a configuration for determining an inter-pin short circuit.

또한, 펄스 발생부(41)가 펄스를 발생하는 구성을 나타냈으나, 스텝 신호를 발생할 수도 있다.In addition, although the pulse generation part 41 showed the structure which generate | occur | produces a pulse, you may generate a step signal.

또한, 펄스 발생부(41)가 설치된 구성을 나타냈으나, DUT(10) 자체에 소정의 핀에 펄스 또는 스텝 신호를 출력시키고, 인접 핀을 측정부(43)로 측정하도록 구성될 수도 있다.In addition, although the configuration in which the pulse generator 41 is provided is shown, it may be configured to output a pulse or a step signal to a predetermined pin to the DUT 10 itself, and measure adjacent pins by the measuring unit 43.

본 발명에 따르면 이하와 같은 효과가 있다.According to the present invention has the following effects.

청구항 1 및 청구항 2에 의하면, IC 테스터 또는 반도체 집적 회로가 반도체 집적 회로의 소정의 핀에 펄스 또는 스텝 신호를 부여하고, IC 테스터가 소정의 핀에 인접하는 반도체 집적 회로의 핀의 파형에 의해 핀간 단락의 판정을 행하므로, 완전히 단락되어 있지 않더라도, 핀간 단락을 검출할 수 있다.According to claims 1 and 2, an IC tester or a semiconductor integrated circuit imparts a pulse or step signal to a predetermined pin of the semiconductor integrated circuit, and the IC tester is pin-to-pin by the waveform of the pin of the semiconductor integrated circuit adjacent to the predetermined pin. Since the short circuit is judged, an inter-pin short circuit can be detected even if it is not completely shorted.

청구항 3 내지 청구항 5에 의하면, 시험부가 반도체 집적 회로의 소정의 핀에 펄스 또는 스텝 신호를 부여하고, 시험부가 소정의 핀에 인접하는 반도체 집적 회로의 인접 핀의 파형에 의해 핀간 단락을 판정하므로, 완전히 단락되어 있지 않더라도, 핀간 단락을 검출할 수 있다.According to Claims 3 to 5, since the test section applies a pulse or a step signal to a predetermined pin of the semiconductor integrated circuit, and the test section determines the inter-pin short circuit by the waveform of the adjacent pin of the semiconductor integrated circuit adjacent to the predetermined pin, Even if it is not completely shorted, an inter-pin short can be detected.

Claims (5)

삭제delete 복수개의 핀을 구비하는 액정 구동 드라이버를 시험하는 IC 테스터에 있어서,In the IC tester for testing a liquid crystal drive driver having a plurality of pins, 상기 액정 구동 드라이버의 소정의 핀에 펄스 신호 또는 스텝 신호를 발생시키고, 판정 타이밍에서, 상기 소정의 핀에 인접하는 인접 핀의 파형이 판정값보다 클 때, 핀간 단락을 판정하는 시험부가 설치된, A test section for generating a pulse signal or a step signal to a predetermined pin of the liquid crystal drive driver and determining a short circuit between pins when a waveform of an adjacent pin adjacent to the predetermined pin is larger than a determination value at a determination timing; IC 테스터.IC tester. 제2항에 있어서,The method of claim 2, 상기 시험부는,The test unit, 상기 소정의 핀에 펄스 신호 또는 스텝 신호를 발생시키는 펄스 발생부와,A pulse generator for generating a pulse signal or a step signal to the predetermined pin; 상기 인접 핀을 측정하는 측정부Measuring unit for measuring the adjacent pin 를 구비하는 IC 테스터.IC tester having a. 삭제delete 삭제delete
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5003955B2 (en) * 2007-11-21 2012-08-22 横河電機株式会社 IC tester
CN101697003B (en) * 2009-11-06 2011-08-03 烽火通信科技股份有限公司 Short circuit detecting method and short circuit detecting device
CN102244378B (en) * 2010-05-11 2015-06-10 立锜科技股份有限公司 Device and method for protecting IC (integrated circuit)
CN103544911A (en) * 2012-07-17 2014-01-29 东莞万士达液晶显示器有限公司 Electronic device
TWI461715B (en) * 2012-12-06 2014-11-21 Wistron Corp Testing apparatus and testing method of electronic device
TWI618937B (en) * 2016-12-27 2018-03-21 瑞昱半導體股份有限公司 Integrated circuit test method
CN106771832B (en) 2017-02-23 2019-08-16 京东方科技集团股份有限公司 Its display device of a kind of circuit checker, circuit detecting method and application
US20210041488A1 (en) * 2019-08-11 2021-02-11 Nuvoton Technology Corporation Measuring Input Capacitance with Automatic Test Equipment (ATE)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06186302A (en) * 1992-12-18 1994-07-08 Nippon Steel Corp Semiconductor device
JP2002122623A (en) 2000-10-12 2002-04-26 Yoshikazu Ichiyama Short circuit detecting device for circuit board
KR20040063576A (en) * 2003-01-08 2004-07-14 삼성전자주식회사 Pin to pin short/open test method for output pins of the semiconductor device by leakage current measurement
JP2007019329A (en) 2005-07-08 2007-01-25 Toyota Motor Corp Semiconductor device and method for detecting short circuit across terminal

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04128665A (en) * 1990-09-19 1992-04-30 Nec Yamagata Ltd Open/contact detecting device for semiconductor device
JP2919147B2 (en) * 1992-01-13 1999-07-12 九州日本電気株式会社 Test method for semiconductor integrated circuit
JP3246543B2 (en) * 1996-05-28 2002-01-15 日本電気株式会社 Test method for semiconductor device
JPH10339756A (en) * 1997-06-10 1998-12-22 Yokogawa Electric Corp Method for inspecting short-circuiting between pins and lsi-testing device using it
JP2001004968A (en) * 1999-06-18 2001-01-12 Sharp Corp Liquid crystal display device and its inspection device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06186302A (en) * 1992-12-18 1994-07-08 Nippon Steel Corp Semiconductor device
JP2002122623A (en) 2000-10-12 2002-04-26 Yoshikazu Ichiyama Short circuit detecting device for circuit board
KR20040063576A (en) * 2003-01-08 2004-07-14 삼성전자주식회사 Pin to pin short/open test method for output pins of the semiconductor device by leakage current measurement
JP2007019329A (en) 2005-07-08 2007-01-25 Toyota Motor Corp Semiconductor device and method for detecting short circuit across terminal

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