KR101030974B1 - 4-bit memory cell having vertical gate, nor flash memory array using the same and fabrication method thereof - Google Patents

Abstract

The present invention relates to a memory cell, a Noah flash memory array using the same, and a method of manufacturing the same. More specifically, a rectangular pillar-shaped silicon fin is disposed on both sides of a gate fin formed of a conductive material, with charge storage spaces interposed therebetween. By having a structure in which a first source / drain and a second source / drain are formed across silicon fins, a 4-bit memory cell having a vertical gate capable of 4-bit cell operation with one gate, a noah flash memory array using the same, and fabrication thereof It is about a method.

Vertical Gate, 4-Bit, Noah Flash, Memory

Description

4-bit memory cell with vertical gate and Noah flash memory array using same and manufacturing method therefor {4-BIT MEMORY CELL HAVING VERTICAL GATE, NOR FLASH MEMORY ARRAY USING THE SAME AND FABRICATION METHOD THEREOF}

The present invention relates to a memory cell, a Noah flash memory array using the same, and a method of manufacturing the same. More specifically, a rectangular pillar-shaped silicon fin is disposed on both sides of a gate fin formed of a conductive material, with charge storage spaces interposed therebetween. By having a structure in which a first source / drain and a second source / drain are formed across silicon fins, a 4-bit memory cell having a vertical gate capable of 4-bit cell operation with one gate, a noah flash memory array using the same, and fabrication thereof It is about a method.

Flash memory can be classified into code flash and data flash according to its application. The former uses NOR type structure with fast and random access, and the latter uses NAND type structure with page access and high density. Is used.

Until now, the floating gate type has been mass-produced mainly with such flash memory. However, the floating gate type memory has a limitation that the floating node must have a certain thickness or more as the memory cell (element) becomes smaller. In operation, there is a problem that a high voltage of 15V or more is required, cell-to-cell coupling problems, drain interference problems, and the like, and eventually, scaling down of devices has been limited.

Charge trapping memory (CTF) has been proposed to solve the problem of the floating gate type memory, which, unlike the floating gate type memory, uses a non-conductive material nitride as a charge storage space. And TANOS and the like.

Since the charge trapping memory (CTF) uses a non-conductive material as the charge storage space, as shown in FIG. 1, two independent storage nodes can be implemented in one channel, thereby allowing two bits (one bit on the source side and one drain). One bit per page: this operation is called mirror-bit), and it is possible to implement Channel Hot Electron Injection (CHEI) during write operation, Hot Hole Injection (HHI) during erase operation, In the read operation, reverse reading is mainly used to distinguish each bit independently.

If the charge trapping memory (CTF) is applied to a double gate structure, as shown in FIG. 2, four bits are possible in one cell, but such multi-storage cell (MSNC) Scaling down Node Cells has the following fundamental limitations.

The first is the short channel effect (SCE). When a punch-through occurs in the short channel structure, the channel is formed deep in the bulk side rather than the gate surface. The high temperature electron injection (CHEI) efficiency is lowered, and the read storage operation is not influenced by the charge storage node and the gate, thereby making it difficult to obtain a sufficient threshold voltage window.

The second is the redistribution of stored charges. When electrons are injected by high temperature electron injection (CHEI), the electrons are spread around and stored in a distribution of about 40 nm. There is a problem that the electrons to be stored in the mix are mixed up (ITRS road map shows that a channel length of at least 140 nm is required for stable operation beyond the charge redistribution problem).

Third is the second-bit effect, as the shorter channel lengths bring the source and drain bits closer together, causing electrical charges to cause electrical coupling, which is sufficient to distinguish each bit during a read operation. There is a problem that it is difficult to obtain voltage fluctuations.

In addition, since the channel length of a conventional multi-bit device having a planar structure has a size of 2F based on the current exposure technology, as shown in FIG. 3, when reducing the size from 2F to 1F, the multi storage node cell (MSNC) is used. ) Is difficult to implement multi-bit, and only multi-bit implementation by multi-level cell (MLC) is possible. Therefore, there is a fundamental limitation in reducing a cell size by implementing 4-bit in one cell.

The present invention is proposed to fundamentally solve a problem (limitation point) of a multi-bit device having a planar structure, and forms a silicon pillar having a rectangular pillar shape with charge storage spaces interposed on both sides of a gate fin formed of a conductive material. A 4-bit memory cell having a vertical gate capable of 4-bit cell operation with one gate by having a structure in which a first source / drain and a second source / drain are formed across each of the silicon fins, and a Noah flash memory array using the same; Its purpose is to provide its manufacturing method.

In order to achieve the above object, a 4-bit memory cell having a vertical gate according to the present invention comprises a silicon substrate having a trench; A gate pin having a vertical shape surrounded by an insulating film in the trench; Two silicon trench walls formed on the left and right tunneling insulating films on both sides of the insulating film, with the charge storage space portion and the blocking insulating film interposed between the gate pins; A first source / drain and a second source / drain formed on the silicon trench walls spaced apart from each other, the second source / drain being formed under the silicon trench walls, And electrically insulated from each other by an underlying trench insulating layer, wherein the first source / drain is formed on each of the silicon trench walls and electrically connected to each other by a conductive material layer.

In the NOR flash memory array using the cell, a plurality of gate pins are formed perpendicularly to a length direction to form each gate pin as a word line, and one side or both sides of each gate pin and a length direction of each gate pin. A plurality of square pillar-shaped silicon fins spaced apart from each other along the source line and a source or a drain formed under each of the square pillar-shaped silicon fins arranged in parallel with the word line are connected to each other to form a lower bit line. The conductive material layer formed on each of the rectangular pillar-shaped silicon fins arranged perpendicular to the word line is an upper bit line.

The method for manufacturing a Noah flash memory array includes: a first step of forming a plurality of silicon fins by depositing and patterning a nitride film on a silicon substrate; Depositing a first insulating material on the entire surface of the substrate and etching anisotropically to form insulating film sidewalls on each of the silicon fins; A third step of forming an impurity doping layer in the bottom of the trench between the silicon fins by implanting ions into the entire surface of the substrate; A fourth step of forming a lower bit line doping layer by diffusing the impurity doping layer to the lower portion of each silicon fin through an annealing process; A fifth step of separating the lower bit line doped layer into each lower bit line through a silicon etching process; Depositing and planarizing a second insulating material over the entire surface of the substrate to fill the trench with the second insulating material; A seventh step of selectively recessing and etching the non-silicon material filled in the trench to form a trench insulating film to electrically isolate each of the lower bit lines; An eighth step of forming charge storage spaces on both sides of each of the silicon fins exposed by the recess etch; A ninth step of depositing and etching a first conductive material on the entire surface of the substrate to form a word line; A tenth step of depositing and planarizing an interlayer insulating material over the substrate; An eleventh step of selectively etching the nitride film to expose an upper portion of each of the silicon fins; A twelfth step of forming an upper bit line doping layer on each of the exposed silicon fins through an ion implantation process; And depositing a second conductive material on the entire surface of the substrate, and sequentially etching the second conductive material, the upper bit line doping layer, and each of the silicon fins to form an upper bit line. do.

Since a 4-bit memory cell having a vertical gate according to the present invention has a vertical channel structure, the channel can be sufficiently long even within the size of 1F, and thus, such as a short channel effect, a charge redistribution problem, a second-bit effect, and the like, which are conventionally pointed out, It fundamentally solves the problem and has the effect of symmetrical 4-bit memory cell operation with a single gate.

In addition, in the NOR flash memory array using a cell according to the present invention, since one word line shares both rectangular pillar-shaped silicon pins, it is possible to reduce the number of word lines compared to the prior art, resulting in a reduced word line width and words. Since the width of the isolation space between lines can be reduced, the integration is improved, the number of contacts is reduced, and peripheral circuits (eg, word line decoders) connected to the word lines are simplified.

In addition, the bit line is divided into two types, one is formed on the upper side of the silicon fin perpendicular to the word line, and the other is formed parallel to the word line in the form buried under the silicon pin, a separate for forming each bit line By eliminating the need for a horizontal space, there is an effect of significantly improving the degree of integration.

Furthermore, the method of manufacturing a Noah flash memory array according to the present invention has an advantage of using an existing CMOS process as it is.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

[About structure of cell Example ]

First, a memory cell according to the present invention basically includes a silicon substrate 10a having a trench, as shown in FIG. A gate pin 70 having a vertical shape surrounded by an insulating film 52, 54, 62 in the trench; Two silicon trench walls 44a1 formed on the left and right tunneling insulating layers 62 of the insulating layers, with the charge storage space 64 and the blocking insulating layer 66 interposed therebetween with the gate pin at the center; 12b1, 42c1, 44a2, 12b2, 42c2); Each of the silicon trench walls may include a first source / drain 44a1 and 44a2 and a second source / drain 42c1 and 42c2 spaced apart from each other.

In this case, the charge storage space 64 may be formed as an nitride layer to form an ONO structure 60 together with the tunneling insulating layer 62 and the blocking insulating layer 66. However, the doping layer instead of the nitride layer is doped. The conductive material layer such as the silicon-based material layer may be used to form a floating gate structure.

The second source / drain 42c1 and 42c2 are formed under each silicon trench wall as shown in FIG. 24, and are adjacent to the second source by the trench insulating layer STI under the gate pin 70. Electrically insulated from the drain and each other.

The trench insulating layer STI is an insulating layer filled in the trench under the gate pin 70, and reference numerals 62, 52, and 32a of FIG. 24 correspond to the trench insulating layer STI.

By doing so, even if a sufficiently high voltage is applied to the gate pin 70, it is possible to fundamentally block channel formation on the substrate under the trench to effectively achieve electrical isolation between neighboring second sources / drains.

Meanwhile, the first sources / drains 44a1 and 44a2 are formed on the silicon trench walls as shown in FIG. 24 and electrically connected to each other by the conductive material layer 80a.

In this way, a high voltage is applied to the gate pin 70, and a voltage is applied to the left and right second source / drain 42c1 and 42c2 while the same voltage is applied to the first source / drain 44a1 and 44a2. By applying alternately, it can be effectively programmed above or below each of the charge storage spaces 64. The same is true for read and erase operations, allowing full drive to 4-bit cells.

And, each of the silicon trench wall, as shown in Figure 24, it is preferable to implement a rectangular pillar-shaped silicon fin having a predetermined width, thickness and height.

At this time, the width of the silicon trench wall can prevent the paired cell interference (PCI) by the gate pin of the neighboring cell, and the thickness of the silicon trench wall is read current (resistance at read) and integration degree. And the height of the silicon trench walls can be sized to account for the read current (resistance at read), but to overcome the problems of the prior art (short channel effect, charge redistribution problem, secind-bit effect, etc.). .

By doing so, the same gate pin 70 may be shared and the plurality of memory cells may be effectively spaced apart from each other at regular intervals.

[Regarding Memory Array Example ]

The memory array according to the present invention uses a 4-bit memory cell according to an embodiment of the cell structure. Basically, as illustrated in FIG. 23, a plurality of gate pins 70 are formed to be perpendicular to the longitudinal direction, respectively. The gate fin is a word line (WL1, WL2, etc.), and a plurality of square pillar-shaped silicon fins (silicon trench walls) are spaced apart at a predetermined distance along one or both sides of the gate fins and the longitudinal direction of each gate fin. And a source or a drain (second source / drain) formed under each of the rectangular pillar-shaped silicon fins arranged in parallel with the word line and connected to each other to form a lower bit line (BBL1, BBL2, BBL3, etc.). The conductive material layer 80a formed on each of the rectangular pillar-shaped silicon fins arranged perpendicularly to the word line is an upper bit line (TBL1, TBL2, etc.). The features.

Here, a connection of a source or a drain (second source / drain) formed under each of the rectangular pillar-shaped silicon fins arranged in parallel with the word line for forming the lower bit lines BBL1, BBL2, BBL3, etc., As shown in FIG. 22, the impurity doped layer 46 may be formed, but the array process conditions may be adjusted, and as shown in FIG. 18, the lower side of the second source / drain arranged in parallel with the word line may be connected to each other (42b). It can also be.

In addition, since the structure of each cell used in the memory array is as described above in the embodiment of the structure of the cell, description thereof will be omitted.

Next, a brief description of the operation method of the memory array according to the present embodiment.

First, in the read (read) or write (program) operation, 0 V is not applied to an unwanted bit line, but is floated.

In FIG. 23, 0 V is applied to BBL1 and 3 V is applied to TBL1 to store (program) charge in Bit 1 (①). Then, a voltage of 5 V is applied to WL2. In this case, since the undesired bit line BBL2 is floating in Bit 2 (2), even if the same voltage is applied to TBL1 and WL2, no charge is stored.

In order to confirm this, simulation results were obtained as shown in FIGS. 25 to 27.

FIG. 25 illustrates a voltage application method for simulation, and FIGS. 36 and 27 are simulation results showing potentials and current densities when voltages are applied as shown in FIG. 25.

Through the simulation, when BBL2 is floated, the channel of the silicon portion of Fin 2 is also electrically floated, so that the channel potential of Fin 2 due to the high voltage of WL2 is increased by the self-boosting effect. As a result, even though a high voltage was applied to WL2, the program due to tunneling did not occur in Bit 2 (②) and Bit 4 (④). Also, as shown in FIG. 27, a high current density appeared only between BBL1 and TBL1. Only (①) was able to confirm that the program by high temperature electron injection (CHEI) occurred.

In this manner, by selecting the bit lines that are not selected, random write, read, and erase operations may be performed on each bit.

Examples of the respective operating voltages for each bit are as shown in FIGS. 28 to 31.

28 shows the operating voltage of Bit 1 (①), FIG. 29 shows the operating voltage of Bit 2 (②), FIG. 30 shows the operating voltage of Bit 3 (③), and FIG. 31 shows the operating voltage of Bit 4 (④), respectively. .

[Method of Manufacturing Memory Array Example ]

The manufacturing method of the memory array according to the above embodiment basically goes through a manufacturing process as shown in FIGS. 4 to 18. Looking at this in detail.

First, as shown in FIG. 4, the nitride film 20 is deposited and patterned on the silicon substrate 10 to form a plurality of silicon fins 12 (first step).

Of course, before depositing the nitride layer 20, an oxide layer may be deposited on the substrate to reduce p + channel implantation and stress between the silicon substrate and the nitride layer. In this case, the nitride film 20 serves as an etch stopper during the CMP process, which is performed in a subsequent planarization process.

Subsequently, as shown in FIG. 5, a first insulating material is deposited on the entire surface of the substrate, and anisotropically etched to form insulating film sidewalls 30 on the silicon fins (second step).

The first insulating material may be a conventional oxide film, and the formation of the insulating film sidewall 30 may use a conventional sidewall process of anisotropically etching the oxide film by LPCVD. The insulating layer sidewall 30 serves as a barrier to prevent ions from being doped into the silicon trench walls during the subsequent ion implantation.

Next, as shown in FIG. 6, an impurity doping layer 40 is formed on the bottom of the trench between the silicon fins 12 by implanting n + ions onto the entire surface of the substrate (third step).

In this case, n + ion implantation causes the wafer inclination direction to be 0 degrees (ie, to implant ion perpendicularly to the silicon fin) to penetrate the insulating film sidewall 30 and prevent the n + ion from being doped into the silicon trench wall. In addition, by implanting the ion at a sufficiently high dose to allow the diffusion to the lower portion of the silicon fin 12 in the subsequent annealing process and to reduce the resistance of the bottom bit line (BBL).

Subsequently, as shown in FIG. 7, the impurity doping layer 40 is diffused to the lower portions of the silicon fins 12 through an annealing process such as a high temperature heat treatment to form a lower bit line doping layer 42 (fourth step).

In this case, the impurity doping layer 40 may be sufficiently diffused to the lower portions of the silicon fins 12 by adjusting the heat treatment time and the like.

Next, as shown in FIG. 8, the lower bit line doping layer 42 is separated into each lower bit line 42a through a silicon etching process (a fifth step).

Next, as shown in FIG. 9, the insulating film sidewall 30 is removed, and a thermal oxide film 32 is formed on the entire surface of the trench 14 exposed by the thermal oxidation process. As shown in FIG. 10, a second insulating material is formed on the entire surface of the substrate. Is deposited and planarized to fill the trench 14 with the second insulating material 50 (sixth step).

The thermal oxide film 32 is formed to clean the interface before the second insulating material 50 is filled, but the second insulating material is immediately removed without removing the insulating film sidewall 30 and forming the thermal oxide film 32. (50) can also be filled.

The deposition of the second insulating material 50 may be performed using LPCVD or HDP oxide to fill the trench 14 with an oxide film, and the planarization process may also use a conventional CMP process.

Next, as shown in FIG. 11, the trench insulating layer STI is formed by selectively recessing the non-silicon material filled in the trench 14 to form the respective lower bit lines 42a. Electrical isolation (step 7).

Here, if the non-silicon material is directly filled with the second insulating material 50 in the trench 14 without removing the insulating film sidewall 30 in the sixth step, the insulating film sidewall 30 and the second insulating material 50 ), Otherwise it refers to the thermal oxide film 32 and the second insulating material (50).

Subsequently, as shown in FIG. 12, charge storage spaces 64 are formed on both sides of each of the silicon fins exposed by the recess etch (eighth step).

The charge storage space 64 may be formed through a conventional ONO 60 forming process or a floating gate forming process.

Next, as shown in FIG. 13, the first conductive material is deposited and etched on the entire surface of the substrate to form a word line 70 (ninth step).

The first conductive material may be a doped silicon-based material.

Thereafter, as shown in FIG. 14, an interlayer insulating material (ILD) 54 is deposited on the entire surface of the substrate and planarized by using a CMP process or the like (step 10).

Next, as shown in FIG. 15, the nitride film 20 is selectively etched to expose the upper portion of each of the silicon fins 12 (an eleventh step).

Next, as shown in FIG. 16, an upper bit line doping layer 44 is formed on the exposed silicon fin 12 through an n + ion implantation process (12th step).

Next, as shown in FIG. 17, a second conductive material 80 is deposited on the entire surface of the substrate, and as shown in FIG. 18, the second conductive material 80, the upper bit line doping layer 44, and the respective silicon fins ( 12) is sequentially etched to form the upper bit line 80a (Thirteenth step).

The second conductive material may also be a doped silicon-based material, and is connected only to the upper portion 44a of each of the silicon fins 12 exposed through the second conductive material. 80a) can be formed.

In the process, the second conductive material 80, the upper bit line doping layer 44, and the silicon fins 12 are sequentially formed in order to form the upper bit line 80a in the thirteenth step. When etching, as shown in FIG. 19, when the lower bit lines 42c are also etched and cut, the insulating film 92 is formed in the exposed groove 90a as shown in FIG. Further, the n + ion implantation process and the annealing process are further performed to connect the cut respective lower bit lines 42c to the impurity doping layer 46.

The insulating film may be a thermal oxide film (refer to reference numeral 92 in Fig. 22), but the latter is more preferable because the sidewall oxide film (not shown) by LPCVD is effective in preventing ion implantation into silicon fins or the like.

In the n + ion implantation, the wafer slope is 0 degrees to allow ion implantation only at the bottom of the trench, and the annealing process is performed only for a short time through the RTA.

In addition, before the insulating film forming process for further proceeding with the ion implantation process, as shown in FIG. 20, the charge storage space portion 64 may be removed first, which causes the charge storage space portion 64 to be removed from the conductive material layer. In the case of using a non-conductive material layer such as a nitride film, it is essentially required.

FIG. 1 is a conceptual diagram illustrating a prior art showing that two independent storage nodes may be implemented in a single channel to enable 2-bit operation.

2 is a structural cross-sectional photograph of a conventional double gate showing that 4 bits are possible in one cell.

FIG. 3 is a cross-sectional view illustrating a difficulty in implementing multi-bits by a multi storage node cell (MSNC) when the structure of FIG. 2 is reduced to 1F.

4 to 22 are process perspective views showing a method of manufacturing a quinoa array according to the present invention.

FIG. 23 is a diagram showing the arrangement of the present invention in FIG.

FIG. 24 is a structural perspective view of a cell showing only the memory cell of the present invention in FIG. 23.

25 to 27 are simulation results of the operation of the cell and the array according to the present invention.

FIG. 28 is a table showing the operating voltages of bit 1 (①) in FIG.

FIG. 29 is a table showing the operating voltages of bit 2 (2) in FIG.

FIG. 30 is a table showing the operating voltages of bit 3 (③) in FIG.

FIG. 31 is a table showing the operating voltages of bit 4 (④) in FIG.

<Description of the symbols for the main parts of the drawings>

10, 10a: silicon substrate 12: silicon fin

20 nitride film 30 insulating film sidewall

42c1, 42c2: second source / drain 44a1, 44a2: first source / drain

52, 54 insulating film 62 tunneling oxide film

64: charge storage space 66: blocking oxide film

70 gate pin (word line) 80a: conductive material layer (upper bit line)

Claims (10)

delete delete A silicon substrate having a trench; A gate pin having a vertical shape surrounded by an insulating film in the trench; Two silicon trench walls formed on the left and right tunneling insulating films on both sides of the insulating film, with the charge storage space portion and the blocking insulating film interposed between the gate pins; A first source / drain and a second source / drain formed on the silicon trench walls spaced apart from each other; The second source / drain is formed under each of the silicon trench walls, and is electrically insulated from each other by a trench insulating film under the gate fin, And the first source / drain is formed over each of the silicon trench walls and electrically connected to each other by a layer of conductive material. The method of claim 3, wherein Each silicon trench wall is a rectangular pillar-shaped silicon fin having a predetermined width, thickness and height, And the charge storage space portion is formed of a nitride film or a conductive material layer. A Noah flash memory array using 4-bit memory cells having a vertical gate according to claim 4, comprising: A plurality of gate fins are formed perpendicularly to the longitudinal direction, and each gate fin is a word line. The rectangular pillar-shaped silicon arrayed in parallel with the word line by forming a plurality of rectangular pillar-shaped silicon fins spaced apart by a predetermined distance along one side or both sides of the gate fins and the longitudinal direction of each gate fin. The source or drain formed below the fin is connected to each other as a lower bit line, and the conductive material layer formed on each of the rectangular pillar-shaped silicon fins arranged perpendicular to the word line is an upper bit line. Noah flash memory array using 4-bit memory cells with vertical gates. The method of claim 5, The lower bit line is formed by connecting a source or a drain formed under each of the rectangular pillar-shaped silicon fins arranged in parallel with the word line by an impurity doping layer. Noah flash memory array. A method of manufacturing a Noah flash memory array using a 4-bit memory cell according to claim 6, Depositing and patterning a nitride film on the silicon substrate to form a plurality of silicon fins; Depositing a first insulating material on the entire surface of the substrate and etching anisotropically to form insulating film sidewalls on each of the silicon fins; A third step of forming an impurity doping layer in the bottom of the trench between the silicon fins by implanting ions into the entire surface of the substrate; A fourth step of diffusing the impurity doped layer to the lower portions of the silicon fins through an annealing process to form a lower bit line doped layer; A fifth step of separating the lower bit line doped layer into each lower bit line through a silicon etching process; Depositing and planarizing a second insulating material over the entire surface of the substrate to fill the trench with the second insulating material; A seventh step of selectively recessing and etching the non-silicon material filled in the trench to form a trench insulating film to electrically isolate each of the lower bit lines; An eighth step of forming charge storage spaces on both sides of each of the silicon fins exposed by the recess etch; A ninth step of depositing and etching a first conductive material on the entire surface of the substrate to form a word line; A tenth step of depositing and planarizing an interlayer insulating material over the substrate; An eleventh step of selectively etching the nitride film to expose an upper portion of each of the silicon fins; A twelfth step of forming an upper bit line doping layer on each of the exposed silicon fins through an ion implantation process; And depositing a second conductive material on the entire surface of the substrate, and sequentially etching the second conductive material, the upper bit line doping layer, and each of the silicon fins to form an upper bit line. A method of manufacturing a Noah flash memory array. The method of claim 7, wherein When sequentially etching the second conductive material, the upper bit line doping layer, and the respective silicon fins of the thirteenth step, when the lower bit lines are etched and cut, ion implantation is performed after forming an insulating film in the exposed groove. And further performing the annealing process to connect each of the cut lower bit lines to an impurity doping layer. The method of claim 8, And removing the sidewalls of the insulating layer between the fifth step and the sixth step, and further forming a thermal oxide film on the entire surface of the trench exposed by the thermal oxidation process. The method of claim 9, And first removing the charge storage space before the insulating film formation process to further proceed with the ion implantation process.

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