KR101024252B1 - Method for fabrication of semiconductor device - Google Patents

Abstract

The present invention overcomes the problem of insuring stable control of the SAC etching process due to the film non-uniformity of the insulating film, and prevents side diffusion by the subsequent thermal process of the ion implantation region of the substrate formed for ohmic contact. To provide a, for the present invention, forming a plurality of conductive film patterns on the substrate; Forming an etch stop layer in which a nitride layer is stacked on an oxide layer along a profile in which the plurality of conductive layer patterns are formed; Forming an insulating film on the etch stop film; Selectively etching the insulating layer to form a contact hole exposing the etch stop layer; Etching the etch stop layer to expose the substrate, wherein the nitride layer is vertically etched and the oxide layer is isotropically etched so that a portion of the oxide layer remains on the lower side of the contact hole; Performing ion implantation on the exposed substrate to form an ion implantation region for an ohmic contact; And removing the oxide film remaining on the side surface of the lower portion of the contact hole.

Contact Pads, Contact Plugs, Self Align Contact (SAC), Isolation, Etch Stopping Film, Ion Implantation Area, Side Diffusion.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE}             

1A to 1D are cross-sectional views showing a contact hole forming process of a semiconductor device according to the prior art.

FIG. 2 is a cross-sectional SEM photograph showing lateral diffusion of an impurity ion implantation region during deposition of a plug conductive film. FIG.

3A to 3D are cross-sectional views illustrating a process of forming a contact plug of a semiconductor device according to an embodiment of the present invention.

Figure 4a is a cross-sectional SEM photograph showing the two-layer jaw phenomenon generated when removing the etch stop film.

4B is a cross-sectional SEM photograph of the two-layer jaw of the oxide film removed by a pre-clean process.

5A to 5C are cross-sectional SEM photographs when the EOP detection method is applied to the SAC etching process and a graph showing changes in the EOP signal, respectively.

Explanation of symbols on the main parts of the drawings

300: substrate 301: field insulating film

302 active region 303 gate insulating film

304: gate conductive film 305: gate hard mask                 

306: oxide film 307: nitride film

308 Insulation layer 310 Contact hole

311 ion implantation region

306a: An oxide film etched to remain with a slight chin compared to the nitride film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device.

With the recent development of semiconductor device manufacturing technology, in the manufacturing process of semiconductor devices, especially in the cell manufacturing process, there is a shortage of overlap margin, which leads to a contact using a self alignment contact (SAC) etching process. The hole manufacturing process is used during the manufacturing process step of the DRAM (Dynamic Random Access Memory) element of 0.2 mu m or less. For example, a technique using a heterogeneous insulating film structure composed of an oxide film and a nitride film as an etch stop film on the gate electrode pattern is used.

1A to 1D are cross-sectional views illustrating a process for forming a contact hole in a semiconductor device according to the prior art.

FIG. 1A illustrates a state in which a plurality of gate electrode patterns G1 to G4 are formed in a cell region and a peripheral circuit region. The manufacturing process of FIG. 1A will be briefly described.                         

Field oxide film 101 is formed on a substrate 100 including a cell region and a peripheral circuit region and formed with various elements for forming a semiconductor device through a LOCOS (LOCal Oxidation Of Silicon) process or a shallow trench isolation (STI) process. The area and the active area 102 are distinguished.

A plurality of adjacent conductive film patterns, for example, gate electrode patterns, are formed in the active region, and an oxide-based gate insulating film 103 is deposited, and a metal film such as tungsten, a metal nitride film such as tungsten nitride film, tungsten silicide, and the like are deposited thereon. The metal silicide, polysilicon, or the like is deposited alone or in combination to deposit the gate conductive film 104, and then a nitride film-based hard mask insulating film is deposited.

Subsequently, a photoresist pattern (not shown) for forming a gate electrode pattern is formed, and then the gate electrode pattern is selectively etched using the hard mask insulating film, the gate electrode material, and the gate oxide film as an etching mask, thereby forming the gate insulating film 103 / Gate electrode patterns G1 to G4 forming a stack structure of the gate conductive film 104 / gate hard mask 105 are formed.

Subsequently, an etch stop film is formed in a double structure of the oxide film 106 and the nitride film 107 along the entire profile in which the gate electrode patterns G1 to G4 are formed. In general, although the nitride film 107 is used as an etch stop film, the nitride film 107 has a high dielectric constant, and in particular, when directly contacted with the substrate 100, it causes stress between the substrate 100 and deteriorates electrical characteristics. An oxide film 106 is used as a kind of buffer layer between the 100 and the nitride film 107.                         

Here, the nitride film 107 is used as an etch stop film, and as is well known, an etching selectivity with an oxide film used as an interlayer insulating film in the SAC etching process for forming a subsequent contact hole for a plug can be obtained. This is to prevent etching loss of the gate electrode patterns G1 to G4.

Subsequently, an insulating film 108 for interlayer insulation is formed while sufficiently covering the gate electrode pattern and the upper portion of the substrate. As the insulating film 108, a BPSG (Boro Phospho Silicate Glass) film, a BSG (Boro Phospho Silicate Glass) film, a PSG (Phospho Silicate Glass) film, a TEOS (Tetra Ethyl Ortho Silicate) film, an HDP (High Density Plasma) oxide film, or the like It can be used individually or in combination. As the insulating film 108, a BPSG film is mainly used.

Next, as shown in FIG. 1B, the substrate 100 between the gate electrode patterns G1 to G4, specifically, the electrical region between the active region 102 in the substrate 100 and the element to be formed thereon by a subsequent process. The cell contact open mask 109 is formed to form a contact plug or contact pad for connection, and then the insulating layer 108 is selectively etched using the cell contact open mask 109 as an etch mask to form gate electrode patterns G1 to G4. The contact hole 110 is formed by stopping the SAC etching on the nitride film 107, which is an etch stop layer between the layers.

In the SAC etching, a plasma using a mixed gas of CxFy (x, y is 1 to 10) / CaHbFc (a, b, c is 1 to 10) / Ar / O ₂ is used.

Subsequently, the cell contact open mask 109 is removed using Ar / O ₂ , and the nitride film 107 and the oxide film 106 between the gate electrode patterns G1 to G4 are etched to etch the active region of the substrate 100. Expose 102.

On the other hand, in order to improve the electrical characteristics of the exposed substrate 100 for ohmic contact upon contact between the subsequent contact plug and the substrate 100, specifically, the active region 102 of the substrate 100. P or B, etc. are implanted into 100). Reference numeral 111 denotes a region in which impurities are injected for ohmic contact.

FIG. 1C illustrates a process cross section in which impurities are injected into the substrate 100 at the bottom of the contact hole 110 for ohmic contact.

Subsequently, as shown in FIG. 1D, a pre-cleaning process is performed prior to the deposition of the plug conductive film to remove residues such as the oxide film 106 at the bottom of the contact hole 110.

On the other hand, the conventional contact hole forming process as described above causes the following problems.

First, when the mixed gas of CxFy / CaHbFc / Ar / O ₂ is used in the process of SAC etching the insulating film 108, the etching process should be stopped at the upper end of the nitride film 107 constituting the etch stop film. The uniform thickness of 108 must be preceded.

As described above, the BPSG film is mainly used as the insulating film 108, and the deposition rate of the BPSG film is slower at the edges than at the center of the wafer. Because of this, it is very difficult to ensure the film uniformity of the BPSG film during CMP process for planarization, and the characteristics of CMP equipment also have faster removal rate at the edge than the center of the wafer. Stable process control that leaves the thickness of 107) constant is difficult.

Second, impurities are implanted into the substrate 100 for ohmic contact with the substrate 100 of the subsequent contact plug. The impurity regions thus formed are later diffused later in the thermal process to increase leakage current. As a result, deterioration of the electrical characteristics of the device, such as a decrease in the refresh time of the DRAM device, is inevitable.

The thermal process is a process such as Rapid Thermal Annealing (hereinafter referred to as RTA) and Furnace Annealing. In case of using RTA, a method of growing a plug conductive film through an ESL (Elevated Silicon Layer) or SEG (Selective Epitaxial Growth) method is applicable.In the case of furnace heat treatment, the plug conductive film uses a general deposition method. This is how you do it.

FIG. 2 is a cross-sectional SEM (Scanning Electron Microscopy) photograph showing lateral diffusion of an impurity ion implantation region during deposition of a plug conductive film.

Referring to FIG. 2, the plug P is formed between the two gate electrode patterns G21 and G22, and the side diffusion is shown as 'X' in which the impurity ion implantation region is shown by the thermal process accompanying the plug formation process. It can be confirmed that this leads to deterioration of device characteristics such as reduction of short channel margin of the semiconductor device.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and overcomes the inability to secure stable control of the SAC etching process due to the film non-uniformity of the insulating film, and subsequently heats the ion implantation region of the substrate formed for the ohmic contact. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent side diffusion by a process.

The present invention to achieve the above object, forming a plurality of conductive film patterns on the substrate; Forming an etch stop layer in which a nitride layer is stacked on an oxide layer along a profile in which the plurality of conductive layer patterns are formed; Forming an insulating film on the etch stop film; Selectively etching the insulating layer to form a contact hole exposing the etch stop layer; Etching the etch stop layer to expose the substrate, wherein the nitride layer is vertically etched and the oxide layer is isotropically etched so that a portion of the oxide layer remains on the lower side of the contact hole; Performing ion implantation on the exposed substrate to form an ion implantation region for an ohmic contact; And removing the oxide film remaining on the side surface of the lower portion of the contact hole.

The present invention overcomes the problem of unstable control of the SAC etching process due to the film non-uniformity of the insulating film by applying the endpoint detection method without applying the conventional time control method in the SAC etching process performed before the primary etching stop.

In addition, the nitride film is vertically removed in the process of exposing the contact portion, and an isotropic etching is performed such that the lower oxide film is left to the inside of the contact hole more than the nitride film (eg, having a jaw), and then ohmic. By performing the ion implantation process for the contact, the ion implantation region is limited only to the vicinity of the center of the bottom of the contact hole. Therefore, a subsequent thermal process is applied so that the ion implantation region does not leave the contact hole region even when the ion implantation region is diffused. Accordingly, the side diffusion of the ion implantation region for the ohmic contact may be extended to the lower portion of the gate electrode pattern or the like, thereby increasing the leakage current.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3A to 3D are cross-sectional views illustrating a process of forming a contact plug of a semiconductor device according to an embodiment of the present invention.

In the embodiment of the present invention described below, the process of forming the contact hole pattern and the plug of the semiconductor device will be described as an example, and the contact hole pattern to which the present invention is applied is a metal node and a storage node of a bit line or a capacitor. The present invention can be applied to a process for forming a contact pad and contact with an impurity bonding layer in a substrate such as a source / drain junction for contact.

FIG. 3A illustrates a state in which a plurality of gate electrode patterns G31 to G34 are formed in the cell region and the peripheral circuit region. The manufacturing process of FIG. 3A will be briefly described.                     

A field oxide layer 301 is formed on a substrate 300 including a cell region and a peripheral circuit region and formed with various elements for forming a semiconductor device through a LOCOS or STI process to define a field region and an active region 302.

In the active region 302, a plurality of neighboring conductive film patterns, for example, gate electrode patterns are formed, and an oxide-based gate insulating film 303 is deposited, a metal film such as tungsten, a metal nitride film such as tungsten nitride film, The gate conductive film 304 is deposited by using a single or a combination of metal silicide such as tungsten silicide, polysilicon and the like, and then an insulating film for hard mask based on a nitride film is deposited.

Subsequently, a photoresist pattern (not shown) for forming a gate electrode pattern is formed, and then the gate electrode pattern is selectively etched using the hard mask insulating film, the gate electrode material, and the gate oxide film as an etching mask, thereby forming the gate insulating film 303 / Gate electrode patterns G31 to G34 forming a stack structure of the gate conductive film 304 / gate hard mask 305 are formed.

The gate hard mask 43 is to prevent the gate conductive layer 42 from being attacked in the process of forming the contact hole by etching the interlayer insulating layer during the etching process for subsequent contact formation, and the interlayer insulating layer and the etching speed are remarkably increased. Different materials are used. For example, when an oxide-based layer is used as an interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used, and an oxide-based material is used when a polymer-based low dielectric film is used as the interlayer insulating film. do.

An impurity diffusion region (not shown) such as a source / drain junction is formed in the substrate 30 between the gate electrode patterns G31 to G34.

When source / drain junction regions are formed between the gate electrode patterns G31 to G34 through ion implantation, impurities are implanted into the substrate 30 through ion implantation so as to be aligned with the gate electrode patterns G31 to G34. Next, spacers are formed on the sidewalls of the gate electrode patterns G31 to G34 and ion implantation is performed again to form an LDD structure. Here, the LDD structure, the impurity diffusion region, and the spacer forming process are omitted.

Subsequently, an etch stop film is formed in a double structure of the oxide film 306 and the nitride film 307 along the entire profile in which the gate electrode patterns G31 to G34 are formed. In general, although the nitride film 307 is used as an etch stop film, the nitride film 307 has a high dielectric constant, and in particular, when directly contacted with the substrate 300, it causes stress between the substrate 300 and deteriorates electrical characteristics. An oxide film 306 is used as a kind of buffer layer between the 300 and the nitride film 307.

Here, the nitride film 307 is used as an etch stop film, and as is well known, an etching selectivity with an oxide film used as an interlayer insulating film during the SAC etching process for forming a subsequent contact hole for a plug can be obtained. This is to prevent etching loss of the gate electrode patterns G31 to G34.

Subsequently, an insulating film 308 for interlayer insulation is formed while sufficiently covering the gate electrode pattern and the upper portion of the substrate. As the insulating film 308, a BPSG film, a BSG film, a PSG film, a TEOS film, an HDP oxide film, or the like can be used alone or in combination. The insulating film 308 is mainly a BPSG film.                     

Next, as shown in FIG. 3B, a photoresist is applied on the insulating film 308 to a suitable thickness through a spin coating method, and then the width of the contact source and the contact hole such as KrF, ArF or F ₂ are defined. A predetermined portion of the photoresist is selectively exposed using a predetermined reticle (not shown), and the portion exposed or not exposed by the exposure process is left through a developing process, and then a post-cleaning process is performed. By removing the etching residues, the photoresist pattern 309 which is a cell contact open mask for forming the LPC is formed.

Here, the cell contact open mask may use a hole type, a bar type, a tee type, or the like.

When the exposure to form the pattern, that is, the lower the light reflectivity of the insulating film 308 is increased to prevent the unwanted pattern is formed by forming a photoresist pattern (for the purpose of improving the adhesion between the insulating film 308 and the photoresist ( An anti-reflection film (not shown) is formed between the 309 and the insulating film 308. The anti-reflection film mainly uses an organic material similar to the photoresist and its etching characteristics, and may be omitted depending on the process. .

In addition, a hard mask may be formed between the insulating film 308 and the photoresist or between the insulating film 308 and the antireflection film. In this case, as the hard mask material, a nitride-based insulating material or a conductive material such as tungsten or polysilicon may be used.                     

An SAC etching process is performed to etch the interlayer insulating layer 45 as an etched layer using the photoresist pattern 46 as an etch mask to expose the etch stop layer 44 between the adjacent gate electrode patterns G41 to G44. Form 47.

At this time, the etching of the interlayer insulating film 45 is applied to the recipe of the conventional SAC etching process, fluorine-based plasma, for example, C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₅ F CxFy (x, y is 1 to 10), such as ₈ or C ₅ F ₁₀ , is used as a stock angle gas, and a gas for generating a polymer in the SAC process, that is, CH ₂ F ₂ , C ₃ HF ₅ or CHF ₃ CaHbFc (a, b, c is 1 to 10) gas and O ₂ gas are added, and an inert gas such as He, Ne, Ar, or Xe is used as a carrier gas.

On the other hand, in the present invention, by applying the EOP detection method without applying the time control method used in the conventional SAC etching process, it is possible to overcome the problem of the stable control of the SAC etching process due to the film non-uniformity of the insulating film.

5A to 5C show cross-sectional SEM photographs and graphs showing changes in the EOP signal when the EOP detection method is applied to the SAC etching process. Here, the wavelength used for EOP detection is 382.7 nm.

FIG. 5A is a cross-sectional view illustrating a process cross section after performing a first etching process to a lower portion of the gate hard mask 305 during the SAC etching process. The nitride film 307 used as an etch stop film as shown in FIG. 5C is illustrated in FIG. 5C. It can be seen that the peak value of the EOP signal was detected when the shoulder of the person was exposed.

Therefore, even through the EOP system, even if the film uniformity of the insulating film 208 is poor in part, a uniform etching profile can be obtained.

In addition, FIG. 5B is a cross-sectional view of the process after forming the contact hole 310 during the SAC etching process and performing the second etching process of exposing the nitride film 307 on the bottom surface of the contact hole 310. It can be seen that the peak value of the EOP signal is detected when the nitride film 307 at the bottom of the contact hole 310 is exposed, such as 'B'.

Therefore, it can be seen that the etching stop is possible in the nitride film 307 during the SAC etching process.

Subsequently, as shown in FIG. 3C, the photoresist pattern 309 is removed using an inert gas of He, N ₂ , Ar, or a mixed gas containing Xe and O ₂ . On the other hand, if the photoresist pattern 309 remains, it may cause a pattern defect in a subsequent etch stop film removal process, so it should be removed.

The nitride film 307 and the oxide film 306 between the gate electrode patterns G31 to G34 are etched to expose the active region 302 of the substrate 300. At this time, the nitride film 307 positioned on the upper portion of the etch stop layer is vertically etched in the usual manner, while the oxide film 306 located on the lower portion is slightly smaller than the nitride film 307 as indicated by reference numeral 306a. Isotropic etching is performed so as to remain with the jaw, that is, the etching process is performed to have a shape such that the width of the contact hole 310 is narrowed.

When the nitride film 307 is etched, a conventional recipe is used. As a gas, CF ₄ / CHF ₃ / O ₂ is used, and the pressure of the chamber is maintained at 10 mTorr to 100 mTorr, and the temperature is maintained at 0 ° C. to 60 ° C., The flow rate of each gas is used from 10SCCM to 100SCCM.

When etching the oxide film 306, a mixed gas of CF ₄ / CHF ₃ / Ar is used, the pressure in the chamber is maintained at 100 mTorr to 500 mTorr, and the temperature in the chamber is maintained at 0 ° C to 60 ° C. This is done at 10% to 50% lower power levels. At this time, the gas uses 10SCCM-100SCCM, respectively.

Figure 4a is a cross-sectional SEM photograph showing the two-layer jaw phenomenon that occurs when removing the etch stop film.

Referring to FIG. 4A, when the oxide film is etched, the etch stop layer is removed under the above-described process conditions, thereby confirming that the oxide film has a two-layer jaw phenomenon as shown in “306a”.

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Subsequently, the P 300 may be formed on the substrate 300 to improve electrical characteristics of the exposed substrate 300 for ohmic contact upon contact between the subsequent contact plug and the substrate 300, specifically the active region 302 of the substrate 300. Or B or the like. Reference numeral '311' denotes a region in which impurities are injected for ohmic contact.

On the other hand, since the oxide film 306 has a two-layer jaw structure, the ion implantation region 311 is not formed in the portion where the oxide film 306 remains, and the ion implantation region 311 is formed only near the center of the contact hole 310. It can be seen that formed.

At this time, ion implantation is also performed under normal conditions. For example, PH31 impurities having a concentration of 1E21 to 1E14 are implanted using ion implantation energy of 10 eV to 40 eV.

FIG. 3C illustrates a process cross section in which impurities are injected into the substrate 300 at the bottom of the contact hole 310 for ohmic contact.

Subsequently, as shown in FIG. 3D, a pre-cleaning process is performed before the deposition of the plug conductive film to remove the oxide film 306 having the two-layer jaw structure from the bottom of the contact hole 310. It is preferable to use a mixed gas of NF ₃ / He / O _{2 in} the pre-cleaning process.

4B is a cross-sectional SEM photograph of the two-layer jaw of the oxide film removed by a preclean process.

Referring to FIG. 4B, it can be confirmed that the two-layer jaw phenomenon of the oxide film 306 is removed by the pre-cleaning process as shown in '306'.

Subsequently, although not shown in the drawings, the conductive film for plug formation is deposited on the entire surface of the substrate 300 on which the contact hole 310 is formed to sufficiently fill the contact hole 310.

Here, the most commonly used material for forming a conductive film for plug formation is polysilicon, and may be formed by laminating with barrier metal layers such as Ti and TiN, and metal such as tungsten may be used instead of polysilicon.

Subsequently, a CMP process is performed on the target to which the gate hard mask 305 is exposed, and is electrically connected to the impurity diffusion region of the substrate 300, for example, the substrate 300 through the contact hole 310. And the top is flattened to form a plug with isolation.

The ion implantation region 311 formed by ion implanting impurities into the substrate 300 for ohmic contact with the substrate 300 of the contact plug is formed by forming a conductive film, for example, the plug conductive film through an ESL or SEG method. Diffusion is inevitable when RTA is grown or furnace heat treatment is used, which uses a general deposition method.

Meanwhile, in the above-described embodiment of the present invention, the ion implantation region 311 is formed only near the center of the contact hole 311, so that the range of diffusion of the ion implantation region 311 to the side during the thermal process can be minimized. do.

According to the present invention made as described above, the SAC etching process performed before the primary etching stop is applied to the end point detection method without applying the time control method as in the prior art, thereby achieving stable control of the SAC etching process due to the film non-uniformity of the insulating film. In the process of exposing the contact area, the nitride film is vertically removed as in the process of exposing the contact portion, and the oxide of the lower portion is etched to remain inside the contact hole more than the nitride film (for example, to have a jaw), and then the ohmic contact By performing the ion implantation process for the above, the ion implantation region is limited only to the vicinity of the center of the bottom of the contact hole. Therefore, a subsequent thermal process is applied so that the ion implantation region does not leave the contact hole region even when the ion implantation region is diffused. Accordingly, the embodiment has been found that the side diffusion of the ion implantation region for the ohmic contact may be extended to the lower portion of the gate electrode pattern and the like to increase the leakage current.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment of the present invention, only the T type SAC process is used as an example. In addition, the SAC process may be applied to a line type or hole type SAC process, and not only between the gate electrode patterns but also the bit line. The semiconductor device may be applied to various semiconductor manufacturing processes such as opening a gap (ie, a storage node contact hole forming step) or a via contact forming step.

As described above, the present invention has an effect of stopping the self-aligned contact etching at the upper end of the nitride film having a stable thickness by using an endpoint detection system during the insulating film etching process for the self-aligned contact.

In the present invention, the nitride film and the oxide film are etched to conduct electricity to the underlying substrate so that a portion of the oxide film remains at the bottom edge of the contact opening, and an etching section is formed, followed by ion implantation to carry out ion implantation to the contact center. By limiting, side ion diffusion of the ion implantation region is minimized by subsequent thermal processes, thereby preventing deterioration of electrical characteristics of the semiconductor device due to side diffusion.

Claims (12)

Forming a plurality of conductive film patterns on the substrate; Forming an etch stop layer in which a nitride layer is stacked on an oxide layer along a profile in which the plurality of conductive layer patterns are formed; Forming an insulating film on the etch stop film; Selectively etching the insulating layer to form a contact hole exposing the etch stop layer; Etching the etch stop layer to expose the substrate, wherein the nitride layer is vertically etched and the oxide layer is isotropically etched so that a portion of the oxide layer remains on the lower side of the contact hole; Performing ion implantation on the exposed substrate to form an ion implantation region for an ohmic contact; And Removing the oxide film remaining on the side surface of the lower portion of the contact hole. Semiconductor device manufacturing method comprising a. The method of claim 1, Etching the etch stop layer, Etching the nitride film using CF ₄ / CHF ₃ / O ₂ , and etching the oxide film using a CF ₄ / CHF ₃ / Ar gas so that the oxide film partially remains on the side surface of the contact hole. A semiconductor device manufacturing method comprising a. The method of claim 2, In the etching of the nitride film, maintaining a pressure in the chamber at 10 mTorr to 100 mTorr, a chamber temperature at 0 ° C. to 60 ° C., and using each gas at 10 SCCM to 100 SCCM. The method of claim 3, wherein In the etching of the oxide film, the pressure in the chamber is maintained at 100 mTorr to 500 mTorr, and the temperature in the chamber is maintained at 0 ° C. to 60 ° C., and the power is 10% to 50% lower than that of the nitride film. Method of manufacturing a semiconductor device, characterized in that using 10SCCM to 100SCCM. The method of claim 1, In the step of removing the oxide film, a semiconductor device manufacturing method characterized in that using NF ₃ / He / O ₂ gas. The method of claim 1, The insulating film is an oxide film-based material film, And forming a contact hole, using a self-aligned contact etching process. The method of claim 1, And removing the oxide film to form a plug in contact with the substrate through the contact hole. The method of claim 7, wherein Forming the plug, Forming a plug forming material to be conductive with the exposed substrate; And Forming an isolated plug by polishing the plug forming material with a target to which the conductive layer pattern is exposed. Semiconductor device manufacturing method comprising a. The method of claim 8, Forming the plug forming material, And depositing the plug-forming material on the entire surface of the substrate or growing from the exposed substrate through selective epitaxial growth. The method of claim 1, Forming the contact hole, A method of fabricating a semiconductor device, comprising using a photoresist pattern having a hole type, bar type, or tee type as an etching mask. The method of claim 1, The conductive film pattern is a semiconductor device manufacturing method comprising a gate electrode pattern, a bit line or any one of a metal wiring. The method of claim 8, The plug forming material includes polysilicon or tungsten.

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