KR101022569B1 - Thin Film Transistor and fabrication method thereof - Google Patents

Abstract

The thin film transistor manufacturing method according to the present invention comprises the steps of forming a gate electrode on the substrate; Forming a gate insulating film on the entire surface of the substrate on which the gate electrode is formed, and sequentially forming a microcrystalline silicon (uc-Si) layer and an amorphous silicon (n + a-Si) layer to which impurities are added on the gate insulating film; ; And depositing a predetermined metal layer obliquely on a substrate including the microcrystalline silicon (uc-Si) layer and the amorphous silicon ((n + a-Si) layer to which impurities are added.

Description

Thin film transistor and its manufacturing method {Thin Film Transistor and fabrication method

1a to 1e is a manufacturing process diagram of a thin film transistor according to the prior art.

2a to 2c is a manufacturing process diagram of a thin film transistor according to an embodiment of the present invention.

3a to 3e is a manufacturing process diagram of a thin film transistor according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

200 gate electrode 300 gate insulating film

400: microcrystalline silicon layer 500: silicon layer to which impurities are added

600: source electrode 650: drain electrode

The present invention relates to a thin film transistor, and more particularly, to a thin film transistor used as a switching element of a liquid crystal display device and a manufacturing method thereof.

Recently, with the rapid development of the information society, there is a need for a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption, among which a liquid crystal display has a resolution, It is excellent in color display and image quality, and is actively applied to notebooks and desktop monitors.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and image information may be expressed by changing the polarization state of light by optical anisotropy.

A conventional liquid crystal display device arranges two substrates on which the field generating electrodes are formed so that the surfaces on which the field generating electrodes are formed face each other, injects liquid crystal between the two substrates, and then applies a voltage to the field forming electrodes. By moving the liquid crystal molecules by the electric field generated by the application, the image is expressed by the transmittance of light that varies accordingly.

A thin film transistor, which is a switching element, is formed on a lower substrate of the liquid crystal display. In general, an active layer used in the thin film transistor is made of amorphous silicon (a-Si).

This is because amorphous silicon can be formed on a large substrate such as a low cost glass substrate at low temperature.

Hereinafter, a conventional thin film transistor and a method of manufacturing the same will be described with reference to the accompanying drawings.

1A to 1E are manufacturing process diagrams of a thin film transistor according to the prior art.

Referring to FIG. 1A, first, a metal layer is formed by depositing one selected from a group of conductive metals including aluminum (Al) and aluminum alloy (AlNd) by sputtering or the like on a substrate 10. The film is patterned by a photolithography process to form the gate electrode 20. At this time, the thickness of the metal film is about 2000 kPa to 2500 kPa.

Next, referring to FIG. 1B, the gate insulating layer 30 is formed on the entire surface of the substrate 10 on which the gate electrode 20 is formed to cover the gate electrode 20. In this case, the gate insulating layer 30 is made of an insulating material such as silicon nitride (SiNx) and has a thickness of about 2000 μs.

Next, amorphous silicon (a-Si) is deposited on the gate insulating layer 30 by chemical vapor deposition (hereinafter, referred to as CVD). In this case, the thickness of the amorphous silicon (a-Si) layer is about 2000Å, and the amorphous silicon (n + a-Si) layer to which the impurities are added by doping the impurities on the amorphous silicon (a-Si) layer 40. To form (50). At this time, the thickness of the amorphous silicon (n + a-Si) layer 50 to which the impurity is added is about 300 GPa, and the silicon (n + a-Si) layer 50 to which the impurity is added is bonded to the metal. When made, it has ohmic contact characteristics. The gate insulating layer 30 through a photolithography process using anisotropic etching so that the amorphous silicon layer 40 and the doped silicon (n + a-Si) layer 50 remain only in portions corresponding to the gate electrode 20. It is patterned to be exposed.                         

Referring to FIG. 1C, chromium (Cr) or molybdenum (Mo) is formed on the entire surface of the substrate 10 by a sputtering method so as to cover the silicon (n + a-Si) layer 50 to which impurities are added on the gate insulating layer 30. ) Or a selected one of aluminum (Al) is deposited to a thickness of 1500Å to form a metal film. The silicon (n + a-Si) layer 50 to which the impurity is added is in direct contact with the metal film to have ohmic contact characteristics. Therefore, this is referred to as an ohmic contact layer 50.

Then, a photoresist is applied on the metal film, and the photoresist is exposed and developed to form photoresist patterns on portions corresponding to both sides of the gate electrode.

The photoresist material may be divided into a positive type in which the exposed part is developed and a negative type in which the exposed part remains. In general, a positive photoresist material is used in an array process.

Using the photoresist pattern as a mask, the metal thin film is etched to expose the ohmic contact layer 50, and the exposed ohmic contact layer 50 is exposed to expose the amorphous silicon layer 40 under the ohmic contact layer. Etch it.

In this case, the amorphous silicon layer 40 is referred to as an active layer, and portions of the amorphous silicon layer remaining without etching are the source electrode 60 and the drain electrode 65, and the amorphous silicon region exposed between the two electrodes is a channel (Ch). )

Referring to FIG. 1D, an inorganic insulating material such as silicon nitride (SiNx) is entirely deposited on the gate insulating layer 30 to cover the source electrode 60 and the drain electrode 65 to form a passivation layer 70. At this time, the protective film 70 is formed to a thickness of 2000Å.

The passivation layer 70 is patterned through a photolithography process to form a contact hole 77 exposing the drain electrode 65.

Referring to FIG. 1E, for example, indium tin oxide (hereinafter referred to as ITO) among the transparent conductive metal groups is deposited on the passivation layer 70 to form a pixel electrode 80 having a thickness of 2000 Å. .

When the gate voltage is applied in the thin film transistor, electrons formed in the source electrode 60, which is a metal, pass through the ohmic contact layer 50 formed under the source electrode 60 and the active layer 40 formed of pure amorphous silicon; Pass the channel Ch formed in the active layer 40. Then, the electrons passing through the channel Ch tunnel through the ohmic contact layer 50 to move to the drain electrode 65.

However, the thin film transistor to which the amorphous silicon is applied has a very low carrier mobility due to the amorphous structure, which reduces the switching speed of the liquid crystal display.

In addition, the amorphous silicon thin film transistor has a problem in that it is relatively unstable and the duty cycle is relatively low.

In the thin film transistor to which the microcrystalline silicon is applied, the thin film transistor exhibiting more stable and high mobility characteristics by forming the channel portion of the thin film transistor on the side of the gate electrode by depositing the source / drain metal inclinedly, and the manufacturing method thereof. The purpose is to provide.

In order to achieve the above object, a thin film transistor manufacturing method according to the present invention comprises the steps of forming a gate electrode on a substrate; Forming a gate insulating film on the entire surface of the substrate on which the gate electrode is formed, and sequentially forming a microcrystalline silicon (uc-Si) layer and an amorphous silicon (n + a-Si) layer to which impurities are added on the gate insulating film; ; And depositing a predetermined metal layer obliquely on a substrate including the microcrystalline silicon (uc-Si) layer and the amorphous silicon ((n + a-Si) layer to which impurities are added.

In this case, the metal layer is deposited obliquely, so that source and drain electrodes are formed without a separate etching process, and a channel between the source and drain electrodes is formed at one side step of the gate electrode on which the metal layer is not deposited.

In addition, the gate electrode has a thickness of about 4000 kPa to 6000 kPa, and the microcrystalline silicon (uc-Si) layer is formed by chemical vapor deposition (CVD), and the thickness thereof is about 300 kPa. It is done.

In addition, the predetermined metal layer is one selected from chromium (Cr), molybdenum (Mo), or aluminum (Al), and the silicon (n + a-Si) layer to which the impurity is added is in direct contact with the metal film and has ohmic contact characteristics. It acts as an ohmic contact layer.

The method may further include forming a passivation layer by depositing an inorganic insulating material covering the source electrode and the drain electrode, and forming a contact hole exposing the drain electrode by patterning the passivation layer; The method may further include forming one of the transparent conductive metal groups on the passivation layer to form a pixel electrode electrically connected to the drain electrode.

In addition, the thin film transistor according to the present invention comprises a gate electrode formed on a substrate; A gate insulating film, a microcrystalline silicon (uc-Si) layer, and an amorphous silicon (n + a-Si) layer to which impurities are added, sequentially formed on the entire surface of the substrate on which the gate electrode is formed; Source and drain electrodes formed obliquely on a substrate including the microcrystalline silicon (uc-Si) layer and an amorphous silicon ((n + a-Si) layer to which impurities are added; and a gate electrode on which the metal layer is not deposited. And a channel between the source and drain electrodes formed at one step portion.

As described above, the conventional amorphous silicon thin film transistor is inferior to the crystalline silicon semiconductor in terms of physical properties such as conductivity and mobility. Therefore, in order to obtain high-speed characteristics, the method of manufacturing a thin film transistor of crystalline silicon semiconductor is strongly established. It is required.

Here, as the crystalline silicon semiconductor, polycrystalline silicon, microcrystalline silicon, amorphous silicon containing crystalline components, semi-amorphous silicon having an intermediate state between crystalline and amorphous Etc. are known.

In this case, in order to obtain the above polycrystalline silicon semiconductor, an amorphous semiconductor film is generally formed and crystallized by laser beam energy or the like. However, since the irradiation area of the laser beam is small, there is a problem that its throughput (throughput) is low. In addition, there is a problem that a next generation technology in which the stability of the laser is not sufficient to uniformly treat the entire surface of a large area substrate.

Therefore, a thin film transistor to which microcrystalline silicon is formed by the same method as that of conventional amorphous silicon formation, that is, by chemical vapor deposition may be overcome. However, in the case of the microcrystalline silicon thin film transistor, there is a problem in that the (linear) mobility is somewhat low.

Therefore, in the thin film transistor to which microcrystalline silicon is applied, a thin film transistor having a more stable and high mobility characteristic is formed by inclining the source / drain metal to form a channel portion of the thin film transistor on the side of the gate electrode. The purpose is to provide a method.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

2A to 2C are manufacturing process diagrams of a thin film transistor according to an embodiment of the present invention.

Referring to FIG. 2A, first, a metal film is formed by depositing one selected from a group of conductive metals including aluminum (Al) and aluminum alloy (AlNd) by sputtering or the like on a substrate 100. The film is patterned by a photolithography process to form the gate electrode 200. At this time, the metal film, that is, the thickness of the gate electrode 200 is preferably formed to about 4000 ~ 6000Å.

In the related art, the thickness of the gate electrode is generally about 2000 kPa, but the present invention is characterized in that the thickness of the gate electrode is about 2 to 3 times thicker than the conventional.

Next, referring to FIG. 2B, a gate insulating layer 300 is formed on the entire surface of the substrate 100 on which the gate electrode 200 is formed to cover the gate electrode 200. In this case, the gate insulating layer 300 is made of an insulating material such as silicon nitride (SiNx).

Next, a microcrystalline silicon (uc-Si) layer 400 is deposited on the gate insulating layer 300 using chemical vapor deposition (hereinafter, referred to as CVD).

In this case, the thickness of the microcrystalline silicon (uc-Si) layer 400 is preferably about 300Å, and doped with impurities on the microcrystalline silicon (uc-Si) layer 400 to add the amorphous silicon ( n + a-Si) layer 500 is formed. Here, the silicon (n + a-Si) layer 500 to which the impurity is added has ohmic contact property when the metal is bonded with the metal.

Finally, as shown in FIG. 2C, a predetermined metal layer is deposited obliquely on the microcrystalline silicon (uc-Si) layer 400 and the amorphous silicon (n + a-Si) layer 500 to which impurities are added. Here, the predetermined metal layer may be one selected from chromium (Cr), molybdenum (Mo), or aluminum (Al), and it is characterized by depositing the metal layer at an angle without depositing in the vertical direction as in the conventional case. have.

As such, by depositing the metal layer at an angle, the source 600 and the drain electrode 650 are formed without a separate etching process, and one side step portion of the gate electrode 200 on which the metal layer is not deposited is the source 600 and It becomes a channel ch between the drain electrodes 650.

At this time, since the thickness of the gate electrode 200 is two to three times thicker than the conventional one, the source 600 and the drain electrode 650 can be separated more reliably in the deposition of the metal layer at an angle. A portion where the source 600 and the drain electrode 650 are separated, that is, one side of the gate electrode 200 on which the metal layer is not deposited serves as a channel ch between the source 600 and the drain electrode 650. Will be done.

The length of the channel (ch) can be adjusted by the thickness of the gate electrode 200, and by using the side portion of the gate electrode 200 as a channel (ch), it is shorter than the conventional microcrystalline silicon thin film transistor By forming the channel portion, high mobility characteristics can be obtained.

In this case, the silicon (n + a-Si) layer 500 to which the impurity is added is in direct contact with the metal film to serve as an ohmic contact layer having ohmic contact characteristics.

The thin film transistor may be employed in an active matrix type liquid crystal display device or an active matrix type organic light emitting display device. In this case, the drain electrode of the thin film transistor is electrically connected to a pixel electrode provided in each pixel of the liquid crystal display device. The structure is connected to.

Hereinafter, a manufacturing process of a thin film transistor according to the present invention employed in a liquid crystal display device or an organic light emitting display device will be described with reference to FIG. 3. 3A to 3E are diagrams illustrating a manufacturing process of a thin film transistor according to another exemplary embodiment of the present invention.                     

However, the same reference numerals are used for the same components as in FIG. 2.

Referring to FIG. 3A, first, a metal film is formed by depositing one selected from a group of conductive metals including aluminum (Al) and aluminum alloy (AlNd) by sputtering or the like on a substrate 100. The film is patterned by a photolithography process to form the gate electrode 200.

At this time, the metal film, that is, the thickness of the gate electrode 200 is preferably formed to about 4000 ~ 6000Å.

In the related art, the thickness of the gate electrode 200 is generally about 2000 μs, but the present invention is characterized in that the thickness of the gate electrode 200 is formed to be about 2 to 3 times thicker than the conventional one.

Next, referring to FIG. 3B, the gate insulating layer 300 is formed on the entire surface of the substrate 100 on which the gate electrode 200 is formed to cover the gate electrode 200. In this case, the gate insulating layer 300 is made of an insulating material such as silicon nitride (SiNx).

Next, a microcrystalline silicon (uc-Si) layer 400 is deposited on the gate insulating layer 300 using chemical vapor deposition (hereinafter, referred to as CVD).

In this case, the thickness of the microcrystalline silicon (uc-Si) layer 400 is preferably about 300Å, and doped with impurities on the microcrystalline silicon (uc-Si) layer 400 to add the amorphous silicon ( n + a-Si) layer 500 is formed.                     

Here, the silicon (n + a-Si) layer 500 to which the impurity is added has ohmic contact property when the metal is bonded with the metal.

The gate insulating layer 300 through a photolithography process using anisotropic etching so that the microcrystalline silicon layer 400 and the impurity-added silicon (n + a-Si) layer 500 remain only in portions corresponding to the gate electrode 200. It is patterned to be exposed.

Next, as shown in FIG. 3C, a predetermined metal layer is deposited obliquely on the microcrystalline silicon (uc-Si) layer 400 and the amorphous silicon (n + a-Si) layer 500 to which impurities are added. .

Here, the predetermined metal layer may be one selected from chromium (Cr), molybdenum (Mo), or aluminum (Al), and has a feature of depositing the metal layer obliquely without depositing the metal layer in a vertical direction as in the conventional case. .

As such, by depositing the metal layer at an angle, the source 600 and the drain electrode 650 are formed without a separate etching process, and one side step portion of the gate electrode 200 on which the metal layer is not deposited is the source 600 and It becomes a channel ch between the drain electrodes 650.

At this time, since the thickness of the gate electrode 200 is two to three times thicker than the conventional one, the source 600 and the drain electrode 650 can be separated more reliably in the deposition of the metal layer at an angle. A portion where the source 600 and the drain electrode 650 are separated, that is, one side of the gate electrode 200 on which the metal layer is not deposited serves as a channel ch between the source 600 and the drain electrode 650. Will be performed.

The length of the channel (ch) can be adjusted by the thickness of the gate electrode 200, by using the side portion of the gate electrode 200 as a channel, thereby forming a channel portion shorter than the conventional microcrystalline silicon thin film transistor High mobility characteristics can be obtained.

In this case, the silicon (n + a-Si) layer 500 to which the impurity is added is in direct contact with the metal film to serve as an ohmic contact layer having ohmic contact characteristics.

Next, referring to FIG. 4D, an inorganic insulating material such as silicon nitride (SiNx) is entirely deposited to cover the source electrode 600 and the drain electrode 650 to form a protective film 700.

The passivation layer 700 is patterned through a photolithography process to form a contact hole 770 exposing the drain electrode 650.

4E, for example, ITO is deposited and patterned among the transparent conductive metal groups on the passivation layer 700 to form a pixel electrode 800 electrically connected to the drain electrode.

The thin film transistor formed as described above is provided in a matrix form in a liquid crystal display device or an organic light emitting display device. When a predetermined gate voltage is applied to the gate electrode, electrons formed in the source electrode 600 are formed below the source electrode 600. Passing through the ohmic contact layer 500 passes through the active layer 400 formed of microcrystalline silicon and the channel Ch formed in the active layer 400. Since the electrons having passed through the channel Ch tunnel through the ohmic contact layer 500 and move to the drain electrode 650, the electrons serve as a switching element.

According to the present invention, by thinly depositing the source / drain metal in the thin film transistor to which microcrystalline silicon is applied, and forming the channel portion of the thin film transistor on the side of the gate electrode, it is more stable than the conventional thin film transistor, and has high mobility and response. It has the advantage of exhibiting speed characteristics.

Claims (14)

Forming a gate electrode on the substrate; Forming a gate insulating film on the entire surface of the substrate on which the gate electrode is formed, and sequentially forming a microcrystalline silicon (uc-Si) layer and an amorphous silicon (n + a-Si) layer to which impurities are added on the gate insulating film; ; And depositing a metal layer obliquely on a substrate including the microcrystalline silicon (uc-Si) layer and the amorphous silicon ((n + a-Si) layer to which impurities are added. The method of claim 1, By depositing the metal layer obliquely, a source and a drain electrode are formed without an additional etching process, and a channel between the source and the drain electrode is formed in one step portion of the gate electrode on which the metal layer is not deposited. Way. The method of claim 1, The thickness of the gate electrode is a thin film transistor manufacturing method, characterized in that about 4000 ~ 6000Å. The method of claim 1, The microcrystalline silicon (uc-Si) layer is a thin film transistor manufacturing method, characterized in that formed by Chemical Vapor Deposition (CVD) method. The method of claim 1, The thickness of the microcrystalline silicon (uc-Si) layer is formed to about 300Å thin film transistor manufacturing method. The method of claim 1, The predetermined metal layer is a thin film transistor manufacturing method characterized in that the selected one of chromium (Cr), molybdenum (Mo) or aluminum (Al). The method of claim 1, The impurity-added silicon (n + a-Si) layer is in direct contact with a metal film to serve as an ohmic contact layer having an ohmic contact characteristics. 3. The method of claim 2, Depositing an inorganic insulating material covering the source electrode and the drain electrode on the entire surface to form a passivation layer, and forming a contact hole for patterning the passivation layer to expose the drain electrode; And forming one of the transparent conductive metal groups on the passivation layer to form a pixel electrode electrically connected to the drain electrode. A gate electrode formed on the substrate; A gate insulating film, a microcrystalline silicon (uc-Si) layer, and an amorphous silicon (n + a-Si) layer to which impurities are added, sequentially formed on the entire surface of the substrate on which the gate electrode is formed; Source and drain electrodes formed by obliquely depositing a metal layer on a substrate including the microcrystalline silicon (uc-Si) layer and an amorphous silicon ((n + a-Si) layer to which impurities are added; And a channel between the source and drain electrodes formed on one side of the gate electrode on which the metal layer is not deposited. The method of claim 9, The thickness of the gate electrode is a thin film transistor, characterized in that about 4000 ~ 6000Å. The method of claim 9, The thin film transistor, characterized in that the thickness of the microcrystalline silicon (uc-Si) layer is formed to about 300Å. The method of claim 9, The metal layer is a thin film transistor, characterized in that selected one of chromium (Cr), molybdenum (Mo) or aluminum (Al). The method of claim 9, And the silicon (n + a-Si) layer to which the impurity is added is in direct contact with the metal film to serve as an ohmic contact layer having ohmic contact characteristics. The method of claim 9, A passivation layer overlying the source electrode and the drain electrode, and a contact hole patterning the passivation layer to expose the drain electrode; The thin film transistor of claim 1, further comprising a pixel electrode deposited on the passivation layer and electrically connected to the drain electrode.

Images