KR101019701B1 - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

The present invention discloses a semiconductor device capable of preventing a bridge between a word line and a bit line in a semiconductor device having a vertical transistor and a method of manufacturing the same. The disclosed semiconductor device includes a semiconductor substrate having a plurality of pillar-type active patterns, an ion implantation region formed in a surface of the semiconductor substrate between the pillar-type active patterns, and a gate disposed on sidewalls of the pillar-type active pattern, respectively. And a bit line formed in the semiconductor substrate portion under the pillar-shaped active pattern, and formed in the ion implantation region and the semiconductor substrate portion below, and having a relatively thicker thickness in the portion in contact with the ion implantation region than in the other portions. And an insulating film having a sidewall insulating film.

Description

Semiconductor device and method for manufacturing same {SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same that can prevent a bridge between a word line and a bit line in a semiconductor device having a vertical transistor.

As the degree of integration of semiconductor devices increases, the area occupied by each unit cell decreases in plan. In response to such a reduction in the unit cell area, various methods for forming buried contacts for storage node contacts of transistors, bit lines, word lines, and capacitors over a limited area have been studied. As one of the methods, a semiconductor device having a transistor (hereinafter referred to as a vertical transistor) having a vertical channel in a semiconductor substrate by arranging a junction region up and down in an active region has been proposed.

The vertical transistor forms a gate to surround sidewalls of a pillar-type active pattern formed on a surface of a semiconductor substrate, and forms junction regions at upper and lower portions of the pillar-type active pattern around the gate, respectively. A vertical transistor having a vertical channel with respect to the main surface of the semiconductor substrate is formed. Therefore, reducing the area of the transistor does not depend on the channel length.

Hereinafter, a manufacturing method of a semiconductor device having a vertical transistor according to the prior art will be briefly described.

After etching a portion of the semiconductor substrate to form a pillar-type active pattern, a gate having a structure including a gate insulating layer and a gate conductive layer is formed on a sidewall of a lower portion of the pillar-type active pattern. A buried bit line is formed in a portion of the semiconductor substrate under the pillar-type active pattern including the gate. Subsequently, portions of the semiconductor substrate between the pillar-type active patterns are etched to form trenches.

After forming an insulating film on the resultant of the semiconductor substrate including the trench, the insulating film is etched to a predetermined thickness so that the side wall of the gate is exposed. After depositing a conductive film on the etched insulating film, the conductive film is etched to form a word line connecting the gates.

However, in the above-described prior art, if the uniformity of the semiconductor substrate is not good when the insulating layer is etched, the etching margin is insufficient, so that the insulating layer not only exposes the sidewall of the gate but also the height below the buried bit line. For this reason, the buried bit line is exposed. As a result, in the above-described prior art, a bridge between the word line and the buried bit line is generated.

The present invention provides a semiconductor device capable of preventing a bridge between word lines and bit lines in a semiconductor device having a vertical transistor, and a method of manufacturing the same.

In an embodiment, a semiconductor device may include a semiconductor substrate including a plurality of pillar-type active patterns, an ion implantation region formed in a surface of the semiconductor substrate between the pillar-type active patterns, and sidewalls of the pillar-type active pattern, respectively. A gate, a bit line formed in the semiconductor substrate portion below the pillar-type active pattern, and formed in the ion implantation region and the semiconductor substrate portion below, and having a thickness relatively thicker than that in the other portions in contact with the ion implantation region. It includes an insulating film having a sidewall insulating film having a.

Fluorine is ion implanted into the ion implantation region.

The gate includes a gate insulating film having a relatively thick thickness at a portion in contact with the ion implantation region than at the other portions, and a gate conductive layer formed on the gate insulating film.

The word line may further include a word line disposed on the insulating layer and contacting the gate.

In addition, according to an embodiment of the present invention, a method of manufacturing a semiconductor device may include forming a plurality of pillar-type active patterns on a semiconductor substrate, and forming an ion implantation region in a surface of the semiconductor substrate between the pillar-type active patterns. And forming a gate on a sidewall of the pillar-type active pattern, the gate insulating layer having a relatively thicker thickness than the other portions in contact with the ion implantation region and a gate conductive layer disposed on the gate insulating layer. Forming a bit line in a portion of the semiconductor substrate under the pillar-shaped active pattern including the gate, and in the portion in contact with the ion implantation region in the ion implantation region and in the portion of the semiconductor substrate below, relative to the other portions. Insulation with sidewall insulating films with thick thickness Forming a film.

The method may further include forming a channel ion implantation layer in the semiconductor substrate before forming the pillar type active pattern.

The ion implantation region is formed by ion implantation of fluorine.

The ion implantation of fluorine is carried out with a dose of 1.0 × 10 ^{12 to} 1.0 × 10 ¹⁶ ions / cm ² .

Ion implantation of the fluorine is performed by a gradient ion implantation method.

After the forming of the insulating film, further comprising forming a word line on the insulating film in contact with the gate.

In addition, a method of manufacturing a semiconductor device according to another embodiment of the present invention may include forming a plurality of pillar-type active patterns on a semiconductor substrate, respectively forming gates on sidewalls of the pillar-type active pattern, and including the gates. Forming an ion implantation region in the surface of the semiconductor substrate between the pillar-shaped active patterns, forming a bit line in a portion of the semiconductor substrate below the pillar-type active region including the gate and the ion implantation region and the underlying Forming an insulating film having a sidewall insulating film having a relatively thick thickness in a portion of the semiconductor substrate contacting the ion implantation region than in the other portions.

The method may further include forming a channel ion implantation layer in the semiconductor substrate before forming the pillar type active pattern.

The ion implantation region is formed by ion implantation of fluorine.

The ion implantation of fluorine is carried out with a dose of 1.0 × 10 ^{12 to} 1.0 × 10 ¹⁶ ions / cm ² .

Ion implantation of the fluorine is performed by a gradient ion implantation method.

After the forming of the insulating film, further comprising forming a word line on the insulating film in contact with the gate.

In addition, the method for manufacturing a semiconductor device according to another embodiment of the present invention, forming a channel ion implantation layer in the semiconductor substrate, forming an ion implantation region in the portion of the semiconductor substrate under the channel ion implantation layer, Etching a semiconductor substrate on which the ion implantation region is formed to form a plurality of pillar-type active patterns; a gate insulating layer having a relatively thicker thickness on a sidewall of the pillar-type active pattern in contact with the ion implantation region than on the other portions And forming a gate including a gate conductive layer disposed on the gate insulating layer, forming a bit line in a portion of a semiconductor substrate under the pillar-shaped active pattern including the gate, and forming the bit implantation region and the ion implantation region and the substrate. Contacting the ion implantation region in a semiconductor substrate portion of the And a step of forming an insulating film having a minute sidewall insulation film having a thickness in a more relative the other parts of the.

The ion implantation region is formed by ion implantation of fluorine.

The ion implantation of fluorine is carried out with a dose of 1.0 × 10 ^{12 to} 1.0 × 10 ¹⁶ ions / cm ² .

After the forming of the insulating film, further comprising forming a word line on the insulating film in contact with the gate.

According to the present invention, in the manufacture of a semiconductor device having a vertical transistor, fluorine is implanted into a portion of the semiconductor substrate where the word line and the buried bit line are in contact with each other, whereby the portion where the fluorine is ion implanted has a relatively thicker thickness than that of the other portions. A gate insulating film and a sidewall insulating film can be formed.

Accordingly, the present invention can prevent the bridge between the word line and the bit line in a semiconductor device having a vertical transistor, thereby improving device characteristics and reliability.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

As illustrated, a plurality of pillar-type active patterns P are provided on the semiconductor substrate 100, a junction region 104 is formed at an upper end of the pillar-type active pattern P, and a channel region is formed at a lower end thereof. 102 are formed respectively. An impurity ion implantation region 120 is formed in a surface of the semiconductor substrate 100 between the pillar-shaped active patterns P. Fluorine is ion implanted into the impurity ion implantation region 120.

The annular gates G are formed on sidewalls of the pillar-shaped active pattern P, respectively. The gate G includes a gate insulating film 132 formed of an oxide film and a gate conductive film 134 formed on the gate insulating film 132, wherein the gate insulating film 132 is the impurity ion implantation region 120. ) Has a relatively thicker thickness than in the other parts.

An embedded bit line BL extending in a first direction is formed in a portion of the semiconductor substrate 100 under the pillar-shaped active pattern P including the gate G. A trench T is formed by etching the impurity ion implantation region 120 and a portion of the semiconductor substrate 100 below. An insulating film 150 having a sidewall insulating film 142 made of an oxide film and a gap fill insulating film 144 formed on the sidewall insulating film 142 is formed in the trench T. The sidewall insulating layer 142 has a thickness relatively thicker than that of the rest of the portion in contact with the impurity ion implantation region 120.

A damascene word line WL is formed on the insulating layer 150 to contact the gate G and extend in a second direction perpendicular to the first direction.

As described above, the semiconductor device according to the exemplary embodiment of the present invention includes an impurity ion implantation region 120 in which fluorine is ion-implanted in the surface of the semiconductor substrate 100 between the pillar-shaped active patterns P. Referring to FIG. In the semiconductor device according to the embodiment of the present invention, as shown in part A, the gate insulating film 232 and the sidewall insulating film 142 are in contact with the impurity ion implantation region 120 relative to the other parts. To have a thick thickness.

Accordingly, the present invention can prevent the bridge between the word line WL and the buried bit line BL generated in the gate insulating layer 132 and the sidewall insulating layer 142 having a relatively thick thickness. Characteristics and reliability can be improved.

2A to 2H are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, the junction region 104 and the channel region 102 are sequentially formed in the semiconductor substrate 100 from the surface thereof. The hard mask layer pattern 110 is formed on the semiconductor substrate 100 on which the junction region 104 and the channel region 102 are formed.

Anisotropically etch the portion of the semiconductor substrate 100 using the hard mark layer pattern 110 as an etch mask, and then form a spacer 112 on sidewalls of the hard mask layer pattern 110 and the junction region 104. do. Then, the portion of the semiconductor substrate 100 is isotropically etched using the spacer 112 and the hard mask layer pattern 110 as an etching mask, and thus, a plurality of pillar-type active patterns P are formed on the semiconductor substrate 100. ).

Referring to FIG. 2B, an impurity ion implantation region 120 is formed in a surface of the semiconductor substrate 100 between the pillar-type active patterns P. Referring to FIG. The impurity ion implantation region 120 is formed by ion implantation of fluorine, and the ion implantation of fluorine is performed with a dose of 1.0 × 10 ^{12 to} 1.0 × 10 ¹⁶ ions / cm ² . In addition, the ion implantation of the fluorine is carried out by a vertical ion implantation method and a gradient ion implantation method giving a tilt of 1 ~ 10 °, preferably about 7 °.

Referring to FIG. 2C, a gate insulating layer 132 is formed on the surface of the pillar-type active pattern P. Referring to FIG. The gate insulating layer 132 is formed of, for example, an oxide film, and has a relatively thicker thickness than that of the other portions in the portion in contact with the impurity ion implantation region 120, as shown in portion B. FIG.

Referring to FIG. 2D, after the gate conductive layer 134 is formed on the gate insulating layer 132, the gate conductive layer 134 is etched to form a gate insulating layer 132 on the sidewall of the pillar-type active pattern P. Referring to FIG. ) And the annular gate G including the gate conductive layer 134 are formed.

Referring to FIG. 2E, an embedded bit line BL extending in a first direction is formed in a portion of the semiconductor substrate 100 under the pillar-shaped active pattern P including the gate G. Referring to FIG. The buried bit line BL is formed through, for example, an ion implantation process.

Referring to FIG. 2F, a liner insulating layer 140 is formed on the resultant of the semiconductor substrate 100 on which the buried bit line BL is formed. The liner insulating layer 140 is, for example, formed of a nitride film. The liner insulating layer 140, the gate insulating layer 132, the impurity ion implantation region 120, and a portion of the semiconductor substrate 100 beneath the pillar-type active patterns P including the gate G are etched. The trench T is formed.

Meanwhile, since the impurity ion implantation region 120 located on both sides of the trench T has a characteristic of being etched by a subsequent cleaning process, for example, a wet cleaning process, the CD of the upper portion of the trench T is increased. do. Through this, the present invention can prevent the bridge between the buried bit line (BL) on both sides of the trench (T).

Referring to FIG. 2G, a sidewall insulating layer having a relatively thicker thickness on the surface of the trench T may be in contact with the impurity ion implantation region 120 than in the other portions as shown in part C. 142). The sidewall insulating film 142 is formed of, for example, an oxide film.

After the gap fill insulating film 144 is formed on the sidewall insulating film 142 to fill the trench T, the liner insulating film having the gap fill insulating film 144 and the sidewall insulating film 142 formed on the sidewall of the gate G is formed. Etch until 140 is exposed. As a result, the buried bit line BL is separated in the trench T, and an insulating layer 150 including the sidewall insulating layer 142 and the gap fill insulating layer 144 is formed.

Referring to FIG. 2H, a portion of the exposed liner insulating layer 140 is removed. After depositing a conductive film on the insulating layer 150, a predetermined thickness of the conductive film is etched to contact the gate G and extend in a second direction perpendicular to the first direction of the buried bit line BL. The word line WL is formed.

Here, in an embodiment of the present invention, as shown in part A by forming the impurity ion implantation region 120 in which fluorine is ion-implanted in the surface of the semiconductor substrate 100 between the pillar-shaped active patterns P, A gate insulating layer 232 and a sidewall insulating layer 142 having a relatively thicker thickness than that of the other portions may be formed in a portion in contact with the impurity ion implantation region 120.

Subsequently, although not shown, a series of subsequent known processes are sequentially performed to complete the manufacture of the semiconductor device according to the exemplary embodiment.

In an exemplary embodiment of the present invention, an impurity ion implantation region is formed by implanting fluorine into a semiconductor substrate surface between pillar-type active patterns, thereby having a relatively thicker thickness than that of other portions in contact with the impurity ion implantation region. A gate insulating film and a sidewall insulating film can be formed.

Accordingly, the present invention can prevent the gap fill insulating film is etched to a height below the buried bit line to prevent the bridge between the damascene word line and the buried bit line generated in the impurity ion implantation region, thereby reducing the semiconductor device characteristics and reliability. Can improve.

Meanwhile, in the above-described embodiment of the present invention, the fluorine ion implantation is performed after the pillar-type active pattern is formed and before the gate insulating film is formed. As another embodiment of the present invention, the fluorine ion implantation is performed. May be performed after the gate is formed and before the sidewall insulating film is formed.

In this case, the gate insulating film is formed to have a uniform thickness, and the sidewall insulating film is formed to have a relatively thick thickness at the portion in contact with the impurity ion implantation region than at the other portions.

Hereinafter, a method of manufacturing a semiconductor device according to another exemplary embodiment of the present invention will be described with reference to FIGS. 3A to 3G.

Referring to FIG. 3A, the junction region 104 and the channel region 102 are sequentially formed in the semiconductor substrate 100 from the surface thereof. The hard mask layer pattern 110 is formed on the semiconductor substrate 100 on which the junction region 104 and the channel region 102 are formed.

Anisotropically etch the portion of the semiconductor substrate 100 using the hard mark layer pattern 110 as an etch mask, and then form a spacer 112 on sidewalls of the hard mask layer pattern 110 and the junction region 104. do. Then, the portion of the semiconductor substrate 100 is isotropically etched using the spacer 112 and the hard mask layer pattern 110 as an etching mask, and thus, a plurality of pillar-type active patterns P are formed on the semiconductor substrate 100. ).

Referring to FIG. 3B, a gate insulating layer 132 is formed on the surface of the pillar-type active pattern P, and then a gate conductive layer 134 is formed on the gate insulating layer 132. The gate insulating film 132 is formed of, for example, an oxide film. The gate conductive layer 134 and the gate insulating layer 132 are etched to form an annular gate G including a gate insulating layer 132 and a gate conductive layer 134 on sidewalls of the pillar-type active pattern P, respectively. do.

Referring to FIG. 3C, an impurity ion implantation region 120 is formed in the surface of the semiconductor substrate 100 between the pillar-shaped active patterns P including the gate G. Referring to FIG. The impurity ion implantation region 120 is formed by ion implantation of fluorine, and the ion implantation of fluorine is performed with a dose of 1.0 × 10 ^{12 to} 1.0 × 10 ¹⁶ ions / cm ² . In addition, the ion implantation of the fluorine is carried out by a vertical ion implantation method and a gradient ion implantation method giving a tilt of 1 ~ 10 °, preferably about 7 °.

Referring to FIG. 3D, an embedded bit line BL extending in a first direction is formed in a portion of the semiconductor substrate 100 under the pillar-shaped active pattern P including the gate G. Referring to FIG. The buried bit line BL is formed through, for example, an ion implantation process.

Referring to FIG. 3E, the liner insulating layer 140 is formed on the resultant of the semiconductor substrate 100 on which the buried bit line BL is formed. The liner insulating layer 140 is, for example, formed of a nitride film. The liner insulating layer 140, the gate insulating layer 132, the impurity ion implantation region 120, and a portion of the semiconductor substrate 100 beneath the pillar-type active patterns P including the gate G are etched. The trench T is formed.

On the other hand, the impurity ion implantation region 120 located on both sides of the trench T has a characteristic of being etched by a subsequent cleaning process, for example, a wet cleaning process, so that the CD of the upper portion of the trench T is increased. . Through this, the present invention can prevent the bridge between the buried bit line (BL) on both sides of the trench (T).

After the gap fill insulating film 144 is formed on the sidewall insulating film 142 to fill the trench T, the liner insulating film having the gap fill insulating film 144 and the sidewall insulating film 142 formed on the sidewall of the gate G is formed. Etch until 140 is exposed. As a result, the buried bit line BL is separated in the trench T, and an insulating layer 150 including the sidewall insulating layer 142 and the gap fill insulating layer 144 is formed.

Referring to FIG. 3G, a portion of the exposed liner insulating layer 140 is removed. After depositing a conductive film on the insulating layer 150, a predetermined thickness of the conductive film is etched to contact the gate G, and the damascene extends in a second direction perpendicular to the first direction of the buried bit line BL. The word line WL is formed.

Subsequently, although not shown, a series of subsequent known processes are sequentially performed to complete the manufacture of the semiconductor device according to the embodiment of the present invention.

As described above, in another embodiment of the present invention, a sidewall insulating film having a thickness relatively thicker than that of the other portions in the portion in contact with the impurity ion implantation region may be formed. In addition, the present invention can prevent the bridge between the damascene word line and the buried bit line through the sidewall insulating film portion having a relatively thick thickness, thereby improving semiconductor device characteristics and reliability.

Meanwhile, in another embodiment of the present invention described above, the fluorine ion implantation is performed after the gate is formed and before the sidewall insulating film is formed, but as another embodiment of the present invention, the fluorine ion implantation is pillar-shaped. It is also possible to carry out before forming the active pattern.

Hereinafter, a method of manufacturing a semiconductor device according to still another embodiment of the present invention will be described with reference to FIGS. 4A to 4I.

Referring to FIG. 4A, an ion implantation process is performed on the semiconductor substrate 100 to form the junction region 104 and the channel region 102 sequentially arranged from the surface of the semiconductor substrate 100.

Referring to FIG. 4B, an impurity ion implantation region 120 is formed in a portion of the semiconductor substrate 100 under the channel region 102. The impurity ion implantation region 120 is formed by ion implantation of fluorine, and the ion implantation of fluorine is performed with a dose of 1.0 × 10 ^{12 to} 1.0 × 10 ¹⁶ ions / cm ² .

Referring to FIG. 4C, a hard mask layer pattern 110 is formed on the semiconductor substrate 100 on which the impurity ion implantation region 120 is formed. Anisotropically etch the portion of the semiconductor substrate 100 using the hard mark layer pattern 110 as an etch mask, and then form a spacer 112 on sidewalls of the hard mask layer pattern 110 and the junction region 104. do.

Then, the portion of the semiconductor substrate 100 is isotropically etched using the spacer 112 and the hard mask layer pattern 110 as an etching mask, and thus, a plurality of pillar-type active patterns P are formed on the semiconductor substrate 100. ).

Referring to FIG. 4D, a gate insulating layer 132 is formed on the surface of the pillar-type active pattern P. Referring to FIG. The gate insulating layer 132 is formed of, for example, an oxide film, and has a relatively thicker thickness than that of the other portions in the portion in contact with the impurity ion implantation region 120, as shown in portion B. FIG.

Referring to FIG. 4E, after the gate conductive layer 134 is formed on the gate insulating layer 132, the gate conductive layer 134 is etched to form a gate insulating layer 132 on the sidewall of the pillar-type active pattern P. Referring to FIG. ) And the annular gate G including the gate conductive layer 134 are formed.

Referring to FIG. 4F, an embedded bit line BL extending in a first direction is formed in a portion of the semiconductor substrate 100 under the pillar-shaped active pattern P including the gate G. Referring to FIG. The buried bit line BL is formed through, for example, an ion implantation process.

Referring to FIG. 4G, a liner insulating layer 140 is formed on the resultant of the semiconductor substrate 100 on which the buried bit line BL is formed. The liner insulating layer 140 is, for example, formed of a nitride film. The liner insulating layer 140, the gate insulating layer 132, the impurity ion implantation region 120, and a portion of the semiconductor substrate 100 beneath the pillar-type active patterns P including the gate G are etched. The trench T is formed.

On the other hand, the impurity ion implantation region 120 located on both sides of the trench T has a characteristic of being etched by a subsequent cleaning process, for example, a wet cleaning process, so that the CD of the upper portion of the trench T is increased. . Through this, the present invention can prevent the bridge between the buried bit line (BL) on both sides of the trench (T).

Referring to FIG. 4H, a sidewall insulating layer having a relatively thicker thickness on the surface of the trench T may be in contact with the impurity ion implantation region 120 than in the other portions as shown in part C. 142). The sidewall insulating film 142 is formed of, for example, an oxide film.

After the gap fill insulating film 144 is formed on the sidewall insulating film 142 to fill the trench T, the liner insulating film having the gap fill insulating film 144 and the sidewall insulating film 142 formed on the sidewall of the gate G is formed. Etch until 140 is exposed. As a result, the buried bit line BL is separated in the trench T, and an insulating layer 150 including the sidewall insulating layer 142 and the gap fill insulating layer 144 is formed.

Referring to FIG. 4I, a portion of the exposed liner insulating layer 140 is removed. After depositing a conductive film on the insulating layer 150, a predetermined thickness of the conductive film is etched to contact the gate G and extend in a second direction perpendicular to the first direction of the buried bit line BL. The word line WL is formed.

Here, in another embodiment of the present invention described above, by forming the impurity ion implantation region 120 implanted with fluorine in the surface of the semiconductor substrate 100 between the pillar-shaped active patterns P, As described above, the gate insulating layer 232 and the sidewall insulating layer 142 having a relatively thicker thickness than that of the other portions may be formed in the portion contacting the impurity ion implantation region 120.

Subsequently, although not shown, a series of subsequent known processes are sequentially performed to complete the manufacture of the semiconductor device according to the embodiment of the present invention.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

2A through 2H are cross-sectional views illustrating processes of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

3A to 3G are cross-sectional views illustrating processes of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

4A to 4I are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with still another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 channel region

104: junction region 110: hard mask film pattern

112: spacer P: pillar type active pattern

120 impurity ion implantation region 132 gate insulating film

134: gate conductive film G: gate

BL: investment bit line 140: liner insulating film

T: trench 142: sidewall insulating film

144: gap fill insulating film 150: insulating film

WL: word line

Claims (20)

A semiconductor substrate having a plurality of pillar-type active patterns; An ion implantation region formed in a surface of the semiconductor substrate between the pillar-type active patterns; Gates respectively disposed on sidewalls of the pillar-type active pattern; A bit line formed in a portion of the semiconductor substrate under the pillar-type active pattern; A trench formed by etching the ion implantation region and a portion of the semiconductor substrate below the ion implantation region; And A sidewall insulating film formed in the trench and formed on the surface of the trench and having a relatively thicker thickness in contact with the ion implantation region than in the other parts and a gapfill insulating film formed to fill the trench on the sidewall insulating film; An insulating film comprising; Semiconductor device comprising a. The method of claim 1, And fluorine ions are implanted into the ion implantation region. The method of claim 1, And the gate includes a gate insulating film having a relatively thick thickness at a portion in contact with the ion implantation region than at the other portions, and a gate conductive layer formed on the gate insulating film. The method of claim 1, A word line disposed on the insulating layer and in contact with the gate; A semiconductor device further comprising. Forming a plurality of pillar-type active patterns on the semiconductor substrate; Forming an ion implantation region in a surface of the semiconductor substrate between the pillar-type active patterns; Forming a gate on a sidewall of the pillar-type active pattern, the gate insulating layer having a relatively thicker thickness than the other portions in contact with the ion implantation region and a gate conductive layer disposed on the gate insulating layer; Forming a bit line in a portion of the semiconductor substrate below the pillar-type active pattern including the gate; Etching the ion implantation region and a portion of the semiconductor substrate underneath to form a trench; And In the trench, a sidewall insulating film disposed on the surface of the trench and in contact with the ion implantation region, the sidewall insulating film having a relatively thicker thickness than the other portions, and a gapfill insulating film formed to fill the trench on the sidewall insulating film. Forming an insulating film; Method of manufacturing a semiconductor device comprising a. The method of claim 5, Before forming the pillar type active pattern, Forming a channel ion implantation layer in the semiconductor substrate; Method of manufacturing a semiconductor device further comprising. The method of claim 5, And the ion implantation region is formed by ion implantation of fluorine. The method of claim 7, wherein Ion implantation of the fluorine is a method for manufacturing a semiconductor device, characterized in that the dose of 1.0 × 10 ¹² ~ 1.0 × 10 ¹⁶ ions / cm ² . The method of claim 7, wherein The method of manufacturing a semiconductor device, characterized in that the ion implantation of fluorine is performed by a gradient ion implantation method. The method of claim 5, After forming an insulating film including the sidewall insulating film and the gapfill insulating film, Forming a word line in contact with the gate on an insulating film including the sidewall insulating film and a gap fill insulating film; Method of manufacturing a semiconductor device further comprising. Forming a plurality of pillar-type active patterns on the semiconductor substrate; Forming gates on sidewalls of the pillar-type active pattern, respectively; Forming an ion implantation region in a surface of the semiconductor substrate between the pillar-shaped active patterns including the gate; Forming a bit line in a portion of the semiconductor substrate below the pillar-type active region including the gate; Etching the ion implantation region and a portion of the semiconductor substrate underneath to form a trench; And In the trench, a sidewall insulating film disposed on the surface of the trench and in contact with the ion implantation region, the sidewall insulating film having a relatively thicker thickness than the other portions, and a gapfill insulating film formed to fill the trench on the sidewall insulating film. Forming an insulating film; Method of manufacturing a semiconductor device comprising a. The method of claim 11, Before forming the pillar type active pattern, Forming a channel ion implantation layer in the semiconductor substrate; Method of manufacturing a semiconductor device further comprising. The method of claim 11, And the ion implantation region is formed by ion implantation of fluorine. The method of claim 13, Ion implantation of the fluorine is a method for manufacturing a semiconductor device, characterized in that the dose of 1.0 × 10 ¹² ~ 1.0 × 10 ¹⁶ ions / cm ² . The method of claim 13, The method of manufacturing a semiconductor device, characterized in that the ion implantation of fluorine is performed by a gradient ion implantation method. The method of claim 11, After forming an insulating film including the sidewall insulating film and the gapfill insulating film, Forming a word line in contact with the gate on an insulating film including the sidewall insulating film and a gap fill insulating film; Method of manufacturing a semiconductor device further comprising. Forming a channel ion implantation layer in the semiconductor substrate; Forming an ion implantation region in a portion of the semiconductor substrate below the channel ion implantation layer; Forming a plurality of pillar-type active patterns by etching the semiconductor substrate on which the ion implantation region is formed; Forming a gate on a sidewall of the pillar-type active pattern, the gate insulating layer having a relatively thicker thickness than the other portions in contact with the ion implantation region and a gate conductive layer disposed on the gate insulating layer; Forming a bit line in a portion of the semiconductor substrate below the pillar-type active pattern including the gate; Etching the ion implantation region and a portion of the semiconductor substrate underneath to form a trench; And In the trench, a sidewall insulating film disposed on the surface of the trench and in contact with the ion implantation region, the sidewall insulating film having a relatively thicker thickness than the other portions, and a gapfill insulating film formed to fill the trench on the sidewall insulating film. Forming an insulating film; Method of manufacturing a semiconductor device comprising a. The method of claim 17, And the ion implantation region is formed by ion implantation of fluorine. The method of claim 18, Ion implantation of the fluorine is a method for manufacturing a semiconductor device, characterized in that the dose of 1.0 × 10 ¹² ~ 1.0 × 10 ¹⁶ ions / cm ² . The method of claim 18, After forming an insulating film including the sidewall insulating film and the gapfill insulating film, Forming a word line in contact with the gate on an insulating film including the sidewall insulating film and a gap fill insulating film; Method of manufacturing a semiconductor device further comprising.

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