KR100963015B1 - method and circuit for error location Processing of the discrepancy-computationless Reformulated inversionless Berlekamp-Massey algorithm for high-speed low-complexity BCH decoder - Google Patents

Abstract

In a high speed low complex BCH decoder, an error position calculation method and an error position calculation circuit using the RiBM algorithm, which do not require an incongruity calculation, are disclosed. In the error-position calculation method using the reformulated inversion-free Belkamp-Mesh algorithm (RiBM), which finds the root by performing iterative calculation of error-position polynomials in a finite sieve from a syndrome value, two odd-numbered and even-valued syndromes Iterative operation is initialized and stored in a latch of a plurality of basic cells including two latches, one D-flip-flop, five multiplexers, one galloise adder, and two galloise multipliers, and 2t clock divisions. Calculating a coefficient of the error position polynomial by performing the calculation.

BCH, Decoder, DcRiBM, Algorithm, Error Position Polynomial

Description

Method and circuit for error location Processing of the discrepancy-computationless Reformulated inversionless Berlekamp-Massey algorithm for high-speed low- complexity BCH decoder}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error location calculation method and an error location calculation circuit using an RiBM algorithm that does not require an inconsistency calculation in a high speed low complexity BCH decoder. In particular, the present invention provides a method for calculating an error location without using an incompatibility calculation control block. It relates to a method and a circuit.

Recently, Bose-Chaudhuri-Hocquenghen (hereinafter referred to as 'BCH') decoder, which can find and correct a large number of errors occurring during transmission, is widely used in data transmission in optical communication, digital video broadcasting, memory, and data storage system. .

In general, the structure of a BCH decoder consists of a part for detecting and correcting an error. The first part is a Syndrome Polynomial Computation block (hereinafter referred to as 'SC') and the SC block generates the syndrome polynomial and represents the error pattern of the received codeword. Syndrome polynomials are used in the Key-Equation Solver (KES) block, which is the second part of the BCH decoder. The KES block uses the Berlecamp-Massay algorithm, the Euclidean algorithm, and the Modified Euclidean algorithm to solve the key equation. Can be used. At this time, there is a reformulated inversionless Berlekamp-Massey (hereinafter referred to as 'RiBM'), which is a structural improvement of the existing Belkamp-mesh algorithm. However, in the case of RiBM algorithm, hardware complexity and power consumption may increase.

Therefore, there is no need to calculate the inconsistency, and there is an urgent need for an error location calculation method and an error location calculation circuit using the RiBM algorithm which reduces hardware complexity and power consumption.

The present invention provides an error location calculation method and arithmetic circuit that are efficient and can be easily speeded up for continuous data stream processing by reducing the number of basic cells of the RiBM algorithm arithmetic circuit.

The present invention provides an error location calculation method and a calculation circuit for reducing hardware complexity by eliminating the inconsistency calculation control block of the RiBM algorithm calculation circuit to reduce the number of basic cells.

Error location calculation method according to an embodiment of the present invention, error location using a reformulated inversion-less Belkamp-Mesh algorithm (RiBM) to find the root by performing an iterative operation of the error location polynomial in the finite sieve from the syndrome value In the calculation method, the odd-valued and even-valued syndromes are placed in a latch of a plurality of basic cells including two latches, one D-flip-flop, five multiplexers, one galloach adder, and two galloche multipliers. Initializing storing and performing iterative operation by 2t clock division to calculate the coefficient of the error position polynomial.

를 이용할 수 있다.According to an aspect of the invention, the step of calculating the coefficient of the error position polynomial, the equation of calculating the even syndrome using the square value of the odd syndrome

Can be used.

값을 저장하고,

의 값과

의 제곱 값과의 갈로아체 곱셈연산을 대기하는 제 1 단계, 상기 기본 셀 PE₀로부터 전파되는

값과 상기 기본 셀로부터 업데이트된 불합도

와의 갈로아체 곱셈연산 후, PE₀로부터 전파되어 오는

과의 갈로아체 곱셈 연산을 대기하는 제 2 단계 및 상기 기본 셀의 멀티플렉서 신호가 '1'로 바뀌는 경우, 상기 대기하는 제 1 단계 및 제 2 단계의 갈로아체 곱셈 연산 및 상기 제 1 단계의 곱셈연산 결과에서 상기 제 2 단계의 곱셈연산 결과를 뺄셈연산하여 불합도 업데이트를 수행하는 단계를 포함할 수 있다.According to one aspect of the invention, the step of calculating the coefficient of the error position polynomial, the D-flip flop of the base cell

Save the value,

And the value of

Propagating from the base cell PE ₀ , waiting for a Galoache multiplication with a squared value of

Updated mismatch from value and base cell

Propagated from PE ₀ after Galoache multiplication with

A second step of waiting for a Galoache multiplication operation with and the multiplexer signal of the basic cell is changed to '1', and the multiplication operation of the first and second step of Galoache multiplication operation and the first step of waiting The subtraction operation may be performed by subtracting the multiplication result of the second step from the result.

를 D-플립플롭에 카운터 신호 '0'에 저장하고 매 반복 연산시마다 기본 셀 PE_2t에 전파하는 단계 및 짝수번째 연산마다 기본 셀 PE₀ 로부터 전파되는

신호를 상기 복수개의 기본 셀 각각에 전파하는 단계를 포함할 수 있다.According to one aspect of the invention, the step of calculating the coefficient of the error position polynomial, the non-propagation propagation from the base cell PE ₀

Is stored in the D-flip-flop as the counter signal '0' and propagated to the base cell PE _2t in every repetitive operation and propagated from the base cell PE _{0 in} every even operation.

Propagating a signal to each of the plurality of basic cells.

를 저장하고, 상기 불합도

를 반복 연산시마다 기본 셀에 전파하는 제 1 D-플립플롭, 상기 제 1 D-플립플 롭에 저장되는 값을 제어하는 한 개의 멀티플렉서, 짝수번째 연산마다

신호를 상기 복수개의 기본 셀 각각에 전파하는 제 2 D-플립플롭 및 상기 복수개의 기본 셀을 제어하는 1 bit 카운터를 포함한다.An error position calculating circuit according to an embodiment of the present invention includes a plurality of basic cells including two latches, one D-flip-flop, five multiplexers, one galloise adder, and two galloise multipliers. Degree

Save and said mismatch

Is a first D flip-flop that propagates to the base cell at every repetitive operation, and one multiplexer that controls a value stored in the first D flip-flop, every even operation.

A second D-flip-flop for propagating a signal to each of the plurality of basic cells and a 1 bit counter for controlling the plurality of basic cells.

According to one embodiment of the present invention, by reducing the number of base cells of the RiBM algorithm calculation circuit, an error location calculation method and a calculation circuit are provided that are efficient for continuous data stream processing and are easy to speed up.

According to one embodiment of the present invention, an error location calculation method and a calculation circuit are provided to reduce hardware complexity by eliminating the inconsistency calculation control block of the RiBM algorithm calculation circuit to reduce the number of basic cells.

Hereinafter, with reference to the contents described in the accompanying drawings will be described in detail an embodiment according to the present invention. However, the present invention is not limited to or limited by the embodiments. Like reference numerals in the drawings denote like elements.

이다.

은 부호화되는 전체 비트 (bit)의 수이고,

는 부호화 되는 전체 비트 수 중에 정정할 수 있는 비트의 수를 의미하며 이는

로 표현되는 갈로아체(Galois Field)의 지수인

으로부터

의 수식에 의한 관계로 정의된다. k는 실제 데이터의 비트 수를 의미하며,

에서

개의 패리티(parity) 비트로부터 t개의 데이터 전송상에서 생길 수 있는 오류를 정정할 수 있다.In general, the BCH code is the most widely used code in communication systems in recent years and includes various standards such as the International Telecommunication Union (ITU) optical communication standard and the European Telecommunication Standards Association (ETSI) next generation digital video broadcasting (DVB-S2) standard. Forward Error Correction (FEC) technology widely used in the field. Typical form of BCH code is BCH

to be.

Is the total number of bits to be encoded,

Is the number of bits that can be corrected out of the total number of bits to be coded.

The exponent of Galois Field,

From

It is defined as the relationship by the formula of. k means the number of bits of the actual data,

in

Errors that can occur on t data transmissions can be corrected from the parity bits.

1 is a block diagram showing a BCH decoding apparatus according to an embodiment of the present invention.

를 감지하고 정정하는 세 개의 주요한 부분으로 구성되어 있다. 첫 번째 부분은 신드롬 다항식 계산 SC 블록(110)이고 SC블록(110)은 신드롬 다항식

를 생성하고 수신된 코드워드 (codeword)의 오류 패턴을 표현한다. 신드롬 다항식

는 BCH 복호기의 두 번째 부분인 KES 블록(120)에서 사용된다. KES 블록(120)은 해결 방정식 Key equation을 해결하기 위해 벨르캄프-메시(Berlecamp-Massay) 알고리즘, 유클리드 (Euclidean) 알고리즘, 수정 유클리드(Modified Euclidean) 알고리즘 등이 오류위치 다항식(error locator polynomial)

을 구하기 위하여 사용될 수 있다.Referring to FIG. 1, a structure of a BCH decoder that is generally used has an error as shown in FIG. 1.

It consists of three main parts that detect and correct. The first part is syndrome polynomial calculation SC block 110 and SC block 110 is syndrome polynomial

Create and represent the error pattern of the received codeword. Syndrome polynomial

Is used in KES block 120, which is the second part of the BCH decoder. The KES block 120 uses an error locator polynomial to solve the solution equation Key equation.

Can be used to obtain

의 유한체 내에서의 반복연산으로서 그 근을 찾아나가는 연산을 수행하는 알고리즘이다. 해결 방정식을 선형 회기(Linear Feedback)로 생각하고 최소길이를 갖는 시프트 레지스터 회기 등가회로를 찾아가는 알고리즘이다. 각 반복연산의 단계마다 뉴튼(Newton)의 항등식을 만족하는 계수를 갖는 다항식의 최소해와 불합 도(discrepancy)와 연관된 교정항을 유지해야 한다. 모든 체에 대하여 적용 가능한 상기 알고리즘은 먼저 초기조건을 하기 [수학식 1]과 같이 정의하여 반복연산을 준비한다.The Belkamp-Mesh algorithm uses error-position polynomials from syndrome values.

It is an iterative operation in finite field of which performs the operation to find the root. It is an algorithm that considers the solution equation as linear feedback and finds the shift register recursion equivalent circuit with the minimum length. At each iteration of the iteration, we must maintain the correction term associated with the minimum solution and the discrepancy of the polynomial whose coefficients satisfy Newton's identity. The algorithm applicable to all sieves prepares an iterative operation by first defining an initial condition as shown in Equation 1 below.

[Equation 1]

과 오류위치 다항식

, 그리고 스크래치(scratch) 다항식

의 초기값을 설정한다.The initial condition is the length of the shift register

And error location polynomials

, And scratch polynomials

Set the initial value of.

동안의

번의 반복연산을 거쳐 하기 [수학식 2]의 방정식을 반복적으로 수행하여 최종적으로

을 계산한다.The algorithm is

While

After repeating iteratively, the equation of Equation 2 is repeatedly performed.

.

[Equation 2]

값은

이고

의 경우에

이 되고 그 외의 경우에는 0이 된다. 반복연산에 따라 업데이트 된 불합도 값에 하기 [수학식 3]에 의한 뉴튼의 방정식과 하기 [수학식 4]를 통해 오류위치 다항식의 계수의 값을 구할 수 있다.Incongruity

The value is

ego

in case of

Or 0 otherwise. The value of the coefficient of the error position polynomial can be obtained from Newton's equation according to [Equation 3] and [Equation 4] to the updated non-confidence value according to the iterative operation.

&Quot; (3) "

[Equation 4]

은

의 신드롬을 발생시키는 가장 짧은 선형회기가 되며,

의 오류위치 다항식을 구할 수 있다.Through the above equation

silver

Is the shortest linear session that generates the syndrome of

We can get the error location polynomial of.

FIG. 2 is a diagram illustrating an RiBM algorithm calculating circuit 200 using one basic cell repeatedly in accordance with one embodiment of the present invention.

의 계산을 현재 연산 수순의

과

를 동시에 업데이트 할 수 있게 구조적으로 개선한 알고리즘이다. The reformulated Belkamp-Mesh algorithm (RiBM) without reversal is a sequential mismatch in the existing Belkamp-Mesh algorithm.

Calculation of the current operation

and

It is a structurally improved algorithm to update both at the same time.

개의 부가적인 rDC PE로서 그 임무를 수행하게 되며 이를 통해 정규적인 구조 설계가 가능하게 되어 종래의 구조에 비해 집적회로 레이아웃(layout)이 쉬어지는 이점을 가지고 있다.

은

에 대한 감소하지 않는 함수(nondecreasing function)이기 때문에 채널 내에서 오류정정가능 능력 t개 내에서

를 만족할 수 있다. 그러므로 모든

에 대해

의 수식을 만족하게 되고, 따라서

와

는 구조내에서 다음 연산 차수로 연산이동을 하지만

와

의 계수의 값을 갱신시키지 못한다.Referring to FIG. 2, the hardware structure of the RiBM algorithm is one that removes an ELU block and configures an rDC as compared to a conventional inverted Velkamp-Mesh (iBM) structure, which is divided into an rDC block and an ELU block. It is typical to obtain the coefficient of error value polynomial and error location polynomial of Reed-Solomon (hereinafter referred to as 'RS') or the error location polynomial of BCH decoder through Processing Element (hereinafter referred to as 'PE'). It is a KES structure. The RiBM structure is derived from an ELU block that is more efficiently optimized than the existing riBM structure.

As an additional rDC PE, it performs its task, thereby allowing a regular structure design, which has the advantage of easier integrated circuit layout than the conventional structure.

silver

Because it is a nondecreasing function for, within t error correction capabilities within the channel

Can be satisfied. Therefore all

About

Will satisfy the formula

Wow

Does arithmetic shift to the next arithmetic order in the structure,

Wow

It does not update the value of the coefficient of.

와

는 초기값

을 갖게 되며, 아래 [표 1]의 [수식 9]에서부터 [수식 19]에 이르는 의사코드 형태의 알고리즘으로 풀이할 수 있으며 도 2에 도시된 것와 같이 표현할 수 있다.Of the structure of PE array within RiBM

Wow

Is the initial value

It can be solved by the algorithm in the form of a pseudo code ranging from [Equation 9] to [Equation 19] of the following [Table 1] and can be expressed as shown in FIG.

[수학식 10] Input :

for

step

until

do
[수학식 11]
RiBM.1.

RiBM.2. if

and

[수학식 12]

[수학식 13]

[수학식 14]

else
[수학식 15]

[수학식 16]

[수학식 17]

[수학식 18] Output :

[수학식 19]

RiBM Algorithm
Equation 9 Initialization:

[Equation 10] Input:

for

step

until

do
[Equation 11]
RiBM.1.

RiBM.2. if

and

[Equation 12]

[Equation 13]

[Equation 14]

else
[Equation 15]

[Equation 16]

[Equation 17]

Equation 18 Output:

[Equation 19]

인 이진 BCH 부호의 생성다항식 g(x)는 갈로아체 GF

내에서 근을 갖게 되는데, 이는

에 대응하는 최소다항식

,

의 곱으로 이루어진다. 여기서 갈로아체 GF(2 ^m )내의

는 원시다항식(primitive polynomial)

의 근이다. 이진 BCH 부호는 0과 1을 계수로 갖는

을 부호다항식이라 할 때, 부호다항식

가

을 근으로 갖는다면 이 근들에 대응하는 최소다항식

로 나누어 떨어지므로 생성다항식

는 이들 최소다항식의 최소공배수이다. 또한 짝수지수를 가지는 홀수지수의 최소다항식과 같은 값을 가지게 되므로 생성다항식은 아래 [수학식 5]와 같이 표현된다.The length of the sign

The generator polynomial g (x) of the BCH code is binary Galois field GF

You have a muscle within

Least polynomial corresponding to

,

Is multiplied by Where in Galloiche GF ( 2 ^m )

Is a primitive polynomial

Is the root of. Binary BCH code has 0 and 1 as coefficients

Is a sign polynomial,

end

If we have, then the minimum polynomial corresponding to these roots

Generated by the polynomial

Is the least common multiple of these least polynomials. Also, since the polynomials have the same value as the minimum polynomial of the odd index with the even index, the generated polynomial is expressed as Equation 5 below.

[Equation 5]

LCM{

}

LCM {

}

를 전송했을 때 수신다항식은 오류다항식의 합의 형태로

와 같이 표현할 수 있다. Codeword

When we send, the receive polynomial is in the form of a consensus of error polynomials.

It can be expressed as

개의 오류가 아래 [수학식 6]와 같이 임의의 위치

에서 발생하였다고 가정할 때,

가 부호다항식의 근이므로

가 된다. in reality

Errors at random locations as shown in Equation 6 below

Assuming that occurred at

Since is the root of the sign polynomial

Becomes

&Quot; (6) "

Therefore, if the sign polynomial does not converge to '0', it can be seen that an error occurs in sign reception. On the other hand, the syndrome, which is an element for finding the error position polynomial, is obtained from Equation 7 below.

[Equation 7]

일 때의 나머지를 신드롬이라 하는데 이는

로부터

를 구할 수 있다. 따라서 신드롬은 오류형태인 오류다항식에 의존함을 알 수 있다.From here

The rest of the time is called syndrome.

from

Can be obtained. Therefore, it can be seen that syndrome depends on the error polynomial which is an error form.

FIG. 3 is a diagram illustrating an RiBM (DcRiBM) algorithm error location calculation circuit 300 that does not require a mismatch calculation according to an embodiment of the present invention.

Equation 9 to Equation 19 (Table 1) of the RiBM algorithm to Equation 20 to Equation 28 of the RiBM algorithm to remove the non-unity calculation control block ] In the form of.

[수학식 20]

[수학식 20]

[수학식 21]

[수학식 22]

[수학식 23] Input :

[수학식 24]

for

step

until

do
begin
[수학식 25]

[수학식 26]

[수학식 27]

end
[수학식 28] Output :

Discrepancy - computationless RiBM Algorithm
Equation 20 Initialization:

[Equation 20]

[Equation 20]

[Equation 21]

[Equation 22]

[Equation 23] Input:

[Equation 24]

for

step

until

do
begin
[Equation 25]

[Equation 26]

[Equation 27]

end
[Equation 28] Output:

저장 래치(412)로 구성될 수 있다.Here, referring to FIG. 4, the basic cell of the DcRiBM may be composed of two latches and one D-flip flop. In more detail, as shown in FIG. 4B, the DcRiBM structure includes two latches 411 and 412, one D-flip-flop 413, and two galloche multipliers 414 in the base cell, respectively. 415, one Galoache adder 416, and five multiplexers 417-421. In this case, each of the two latches is a non-confidence storage latch 411 and

Storage latch 412.

를 저장하고 상기 불합도

를 반복 연산시마다 기본 셀에 전파하는 제 1 D-플립플롭(330), 제 1 D-플립플롭(330)에 저장되는 값을 제어하는 한 개의 멀티플렉서(340), 짝수번째 연산마다

신호를 상기 복수개의 기본 셀 각각에 전파하는 제 2 D-플립플롭(350) 및 복수개의 기본 셀(310)을 제어하는 1 bit 카운터(350)를 포함할 수 있다.Referring back to FIG. 3, the DcRiBM algorithm error position calculation circuit 300 includes a plurality of basic cells 310 and a mismatch.

Save the above and

The first D-flip-flop 330 to propagate to the base cell for each iteration operation, one multiplexer 340 to control the value stored in the first D-flip-flop 330, every even operation

It may include a second D-flip-flop 350 for propagating a signal to each of the plurality of basic cells and a 1 bit counter 350 for controlling the plurality of basic cells 310.

에서부터

까지의 신드롬 값을 기본 셀의 불합도 저장 래치(411)에 저장하고, PE₀ 에서부터 PE_{2t -3}까지의 기본셀의

저장 래치(412)에 신드롬 값을 저장한다. 각 기본셀에 래치에 저장되어 있는 초기값은

번의 클락 분주에 의해 반복연산을 거쳐 오류위치 다항식의 계수를 얻을 수 있다. 이때, 아래 [수학식 8]의 짝수 신드롬은 홀수 신드롬의 제곱이라는 성질을 이용하여 다음 순차의 반복연산에

값을

의 기본 셀에 넘겨주지 않고 임시적인 귀환경로를 통해 기본 셀 내부의 D-플립플롭(413)에 저장하여

의 값과

의 제곱의 값과의 갈로아체 곱셈연산을 대기한다.Initialization in the DcRiBM algorithm is described below with reference to FIGS. 3 and 4. As shown in [Equation 20], the basic cell from PE ₀ to PE _{2t -4} is calculated in the syndrome generating block.

From

Syndrome values up to are stored in the base cell's nonconformity storage latch 411, and the base cells from PE ₀ to PE _{2t -3}

The syndrome value is stored in the storage latch 412. The initial value stored in the latch in each basic cell is

The coefficient of error position polynomial can be obtained by iterative operation by the clock division of times. In this case, the even syndrome of Equation 8 below is used to repeat the next sequence using the property of the square of the odd syndrome.

Value

It is stored in the D-flip flop 413 inside the base cell through the temporary return path without passing it to the base cell of

And the value of

Wait for galloise multiplication with the square of.

[Equation 8]

와 귀환경로를 통해 전파되는 불합도

와의 갈로아체 곱셈(414)을 하여 D-플립플롭(411)에 그 값을 저장하여 다음 연산을 대기한다. 또한 기본 셀의 하단부에서는

의 값과 D-플립플롭(412)에 저장되어 있던

값은 갈로아체 곱셈(415) 연산후에 다시 D-플립플롭(412)에 저장된다. 그리고 기본셀 내에 유지되고 있던

값은 셀내의 내부 귀한 경로를 통해 D-플립플롭(413)에 저장되어 다음 연산을 대기한다.Here, the toggle signal of '0' and '1' from the 1-bit counter acts as a control signal of the multiplexers 417, 418, 419, 420 and 421 inside all basic cells. First, at signal '0', the internal disparity at the top of the base cell

And propagation through the environment

Galoache multiplication 414 with and stores the value in D-flip-flop 411 to wait for the next operation. Also, at the bottom of the main cell,

And the D-flip-flop (412)

The value is stored in D-flip-flop 412 again after Galoache multiplication 415 operation. And it was kept in the base cell

The value is stored in D-flip-flop 413 via the internal precious path in the cell to wait for the next operation.

의 갈로아체 곱셉 연산 값은 PE₀로부터 전파되어 오는

과의 갈로아체 곱셈(414)으로

값을 생성하도록 하단부의 연산값과 갈로아체 뺄셈(416) (갈로아체 덧셈기를 통한 연산)을 대기한다. 기본 셀 하단부에서는 D-플립플롭(412)에 저장되어 있던

값이 상단부의 불합도

와의 갈로아체 곱셈(415)을 통해 상단부의 갈로아체 덧셈(416)에 연산을 준비하여 최종적으로 D-플립플롭(412)에

의 값으로 저장된다. 그리고 D-플립플롭(413)의 값은 1bit 카운터 '1'의 신호 직전의 D-플립플롭(411)의 값으로 갱신된다. 이로서 [수학식 25](표 2)의 두 항의 갈로아체 곱셈 연산과 함께 덧셈연산을 통해 불합도

값이 생성되었으며 다음 클락 분주에 t 위치에 전파될

값으로 업데이트가 이루어지게 된다. 기본 셀 PE_2t에는 매 클럭 분주마다

로서 '0'의 값을 전파시켜 줌으로

번의 클락 분주 후에 오류 위치 다항식의

개의 계수 값이 쓰레기 값(Dummy Value)를 갖지 않도록 할 수 있다.When the signal of the 1-bit counter changes to '1', all signals of the multiplexers 417, 418, 419, 420, and 421 in all basic cells are controlled. Stored in the D-flip-flop 411 at the top of the base cell.

The Galoache multiply of is computed from PE ₀

With Galoache multiplication (414)

Wait for the computed value at the bottom and the Galoache subtraction 416 (operation with the Galoache adder) to generate the value. At the bottom of the main cell, the D-flip-flop 412

Value mismatch at the top

Prepare the operation on Galoache Addition (416) at the top via Galoache Multiplication (415) with and finally to D-Flip-Flop (412).

Is stored as. The value of the D-flip flop 413 is updated to the value of the D-flip flop 411 immediately before the signal of the 1-bit counter '1'. Thus, in addition to the Galoache multiplication of the two terms in [Equation 25] (Table 2), the mismatch through the addition operation

Value is generated and propagated to position t in the next clock division.

The value is updated. Base cell PE _2t contains every clock division

By propagating the value of '0'

Error position polynomial after 1 clock division

It is possible to ensure that the count values do not have a dummy value.

번의 클락 분주 후 기본 셀은 DcRiBM 의 복호 반복연산을 마치게 되며 PE₀부터 PE_t 까지의 불합도 저장 래치에서 연산된 불합도

의 값을

부터

까지

개의 오류 위치 다항식의 계수의 값을 얻어낼 수 있다.

After one clock division, the base cell completes the decoding iteration of the DcRiBM, and the disparity calculated from the PE ₀ to PE _t storage latch.

Value of

from

Till

Get the coefficients of the two error-position polynomials.

In this way, the complexity of the hardware and the power consumption can be reduced by eliminating the inconsistency calculation control block and reducing the number of basic cells in which a large number of Galoache adders and multipliers are used.

The structure of the present invention has a critical path delay which is almost similar to that of the conventional RiBM algorithm, which is a two multiplexer signal which undergoes two Galoache multiplications, one Galoache addition operation, and an iterative operation. Is in the flow.

개보다 t개가 줄어든

개의 기본 셀의 수 만으로도 BCH 복호 연산을 수행할 수 있다.The conventional RiBM algorithm has a purpose for decoding operations of the RS decoder, but the DcRiBM algorithm of the present invention has a purpose for decoding operations optimized for a BCH decoder. Therefore, it is possible to find the position of an error value and to correct the error value only by obtaining the error location polynomial without obtaining the error value polynomial present in the RS decoding operation. Therefore, the coefficient value of the error value polynomial is obtained in the conventional RiBM algorithm. The number of t basic cells can be reduced by initializing and storing an odd value syndrome and an even value syndrome in a latch form in the base cell. Therefore, the conventional RiBM algorithm calculation circuit

T fewer than

The BCH decoding operation can be performed only by the number of base cells.

In addition, the DcRiBM algorithm can check the property that the value of the degree of inconsistency always converges to '0' in the even-numbered iterative decoding process as shown in Equation 29 below in the BCH iterative decoding process. As a result, a structure using the DcRiBM algorithm which eliminates the inconsistency calculation control block by arranging the inconsistency calculation process of the conventional RiBM algorithm can be designed.

[Equation 29]

| _{r= even number}

| _{r = even number}

의 값을 생성하고 저장하고 있는 PE₀는 항상 짝수 번째 반복 복호과정에서는 그 값이 '0'으로 수렴한다. 종래의 RiBM 알고리즘 연산 회로의 불합도 계산 제어블록은 PE₀로부터 전파되어 오는 불합도

의 값이 '0'이 아닌 값을 가지고 불합도 계산 제어블록 내의

의 값의 양을 값을 가진 경우에는 전체 기본셀의

의 값을 불합도의 값으로 업데이트를 하고,

의 값을

로 갱신한다. 불합도

값이 그 외의 값을 갖거나 불합도 계산 제어블록 내의 음의

값을 가는 경우에는

는 기존의

의 값을 유지하며,

값 또한

이 유지된다. Inconsistency in Iterative Decoding Process

PE ₀ , which generates and stores the value of, always converges to '0' in the even-numbered iterative decoding process. The disparity calculation control block of the conventional RiBM algorithm computation circuit is the disparity propagated from PE ₀ .

Has a nonzero value and the value in

If the value of the value has a value of

Update the value of to the value of inconsistency,

Value of

Update to. Incongruity

The value has any other value or is negative

If you go for a price

Existing

Keeps the value of,

Value also

Is maintained.

값이 '0'과 그 외의 값을 갖는 다는 것을 확인할 수 있다. 이로서 불합도 계산 제어블록 내에서 MC

신호는 '0'과 '1'의 값을 가지게 됨으로 해서 규칙적으로 홀수 번째 반복과정에서는

값을 불합도의 값으로 업데이트하고

의 값을

로 갱신하게 된다. 마찬가지로 짝수 번째 반복과정에서는

는 기존의

값을,

값은 역시 기존의

값을 유지한다. 위와 같은 기법을 통하여 기본 셀을 제어하는 MC

를 1bit의 카운터(350)로 대체하여 기본 셀을 제어하게 하였으며, PE₀로부터 전파되는

는 기본 셀 외부에서 D-플립플롭(330)에 카운터(350) 신호가 '0'일 때 저장되어 매번 반복 연산마다 PE_2t 기본 셀에 전파된다. 또한 PE₀로부터 전파되는

는 짝수번 째 연산시에 모든 기본 셀에 전파될 수 있다.However, in the BCH decoding process described in [Equation 29], the degree of inconsistency is always obtained through [Equation 14] and [Equation 17].

You can see that the value has a value of '0' and anything else. This allows the MC in the disagreement calculation control block

The signal has values of '0' and '1' so that the odd numbered iterations

Update the value to the value of the mismatch

Value of

Will be updated. Likewise, for even-numbered iterations

Existing

Value,

The value is also existing

Keep the value. MC to control the basic cell through the above technique

Is replaced with a 1-bit counter 350 to control the base cell, which is propagated from PE ₀

Is stored in the D-flip-flop 330 outside the basic cell when the signal of the counter 350 is '0', so that PE _{2t is used} for each iteration. It is propagated to the base cell. Also propagated from PE ₀

Can be propagated to all base cells in even-numbered operations.

As described above, the RiBM algorithm error location calculation method and error location calculation circuit that do not need the inconsistency calculation for the BCH decoder are efficient for continuous data stream processing by reducing the number of basic cells for high speed processing, and easy to speed up. The hardware complexity can be reduced by eliminating the inconsistency calculation control block of the RiBM algorithm computation circuit.

As described above, the present invention has been described by way of limited embodiments and drawings, but the present invention is not limited to the above-described embodiments, which can be variously modified and modified by those skilled in the art to which the present invention pertains. Modifications are possible. Accordingly, the spirit of the present invention should be understood only by the claims set forth below, and all equivalent or equivalent modifications thereof will belong to the scope of the present invention.

1 is a block diagram showing a BCH decoding apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an RiBM algorithm arithmetic circuit that repeatedly uses one basic cell according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating an RiBM (DcRiBM) algorithm arithmetic circuit that does not require a mismatch calculation according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a RiBM (DcRiBM) algorithm base cell without requiring a mismatch calculation according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110: syndrome polynomial calculation block

120: KES (Key-Equation Solver) Block

Claims (5)

In the error position calculation method using a reformulated inversion-free Belkamp-Mesh algorithm (RiBM) that finds the root by performing an iterative operation of the error-position polynomial in a finite sieve from a syndrome value, Initial storing the odd value syndrome and the even value syndrome in a latch of a plurality of basic cells comprising two latches, one D-flip-flop, five multiplexers, one galloise adder, and two galloise multipliers; And Calculating coefficients of the error position polynomial by performing iterative operation by 2t clock division Error location calculation method comprising a. here, T is the number of bits that can be corrected among the total number of bits to be encoded. Means. The method of claim 1, Computing the coefficient of the error position polynomial, Error position calculation method characterized by using the following Equation (8) to calculate the even syndrome using the square value of the odd syndrome. [Equation 8]

The method of claim 2, Computing the coefficient of the error position polynomial, On the D-flip flop of the base cell

Save the value,

And the value of

A first step of waiting for a Galoache multiplication with a squared value of; Propagated from the base cell PE ₀

Updated mismatch from value and base cell

Propagated from PE ₀ after Galoache multiplication with

A second step of waiting for a Galoache multiplication operation with; And When the multiplexer signal of the base cell is changed to '1', the multiplication operation of the second step is subtracted from the Galoache multiplication operation of the first and second steps of waiting and multiplication operation of the first step. To perform an inconsistency update Error location calculation method comprising a. here, remind

Is the value stored in the D-flip-flop of the base cell (PE), remind

Is a non-confidence value propagated from the base cell (PE), remind

Is a signal value propagated from the base cell (PE) Respectively. The method of claim 1, Computing the coefficient of the error position polynomial, Incompatibility propagated from base cell PE ₀

Storing in the D-flip-flop the counter signal '0' and propagating to the base cell PE _2t at every iteration; And Propagated from base cell PE _{0 for} every even operation

Propagating a signal to each of the plurality of basic cells Error location calculation method comprising a. here, PE ₀ is the first basic cell, PE _2t is the 2t + 1th basic cell, T is the number of bits that can be corrected among the total number of bits to be encoded. Respectively. A plurality of basic cells comprising two latches, one D-flip-flop, five multiplexers, one galloise adder, and two galloise multipliers; Incongruity

Save and said mismatch

A first D flip-flop that propagates to the base cell at every iterative operation; One multiplexer controlling a value stored in the first D-flip-flop; Every even operation

A second D flip-flop that propagates a signal to each of the plurality of basic cells; And 1 bit counter for controlling the plurality of basic cells Error position calculation circuit comprising a. here, remind

Is the mismatch of the first basic cell (Processing Element 0, PE ₀ ), remind

Is a signal value propagated from the base cell (PE) Respectively.

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