KR100957321B1 - Software mobile terminal and signal processing method using that - Google Patents

Abstract

A software radio is disclosed that minimizes the number of combinations of software, including application software and driver software. The software radio sets a signal processing unit capable of reconfiguring an internal functional configuration by instructions from software corresponding to a plurality of realization means for a designated function, and sets a parameter corresponding to any one of the plurality of realization means to the signal processing unit. In a software radio having a control unit, the signal processing unit converts the parameter into a parameter corresponding to the function configuration of the signal processing unit when the parameter set by the control unit does not correspond to the functional configuration of the signal processing unit. In the software radio having such a configuration, the control unit is not concerned with the format of the parameter, and it is possible to set parameters according to the situation of the control unit to the signal processing unit.

Software, Radios, Signal Processing, Parameters, Quadrature Detection, Decimators, Complex Mixers

Description

SOFTWARE MOBILE TERMINAL AND SIGNAL PROCESSING METHOD USING THAT}             

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing an example of correspondence between a driver software and a signal processor of a conventional software radio;

2 is a block diagram showing the basic configuration of a software radio according to an embodiment of the present invention;

3 is a diagram showing an example of correspondence between the driver software of FIG. 2 and the signal processor;

4 is a block diagram illustrating an example of a configuration of a signal processing unit of FIG. 2;

5 is a block diagram showing the configuration of the 1 / N decimator of FIG.

6 is a block diagram showing the configuration of the filter of FIG.

FIG. 7 is a block diagram showing another configuration example of the signal processing unit of FIG. 2; FIG.

8 is a block diagram showing a configuration of an orthogonal carrier oscillator by the frequency synthesizer of FIG.

9 is a block diagram showing the configuration of the first decimator of FIG.

9 is a block diagram illustrating a configuration of a second decimator of FIG. 7.                 

Explanation of symbols on the main parts of the drawings

1 antenna 2 RF / IF analog part

3: ADC (A / D converter) 4: Signal processor

5: DAC (D / A converter) 6: control unit

11: digital quadrature detector 12: 1 / N decimator

12a, 12b: CIC filter 13: filter

14 detector 21,61,98 orthogonal carrier oscillator

22,23,62,63,65,66,81,99,100: Multiplier

31,67,71,76,96: adder 32,34: delay

33,64,95,97: Subtractor 35,101,102,113,114: Down Sampler

41,42,111,112: Low Pass Filter

51: first decimator 52: complex mixer

53: second decimator 72,77: phase register

73: ROM-A 74: ROM-B

78: ROM-C 79: ROM-D

91,92,93,94: Digital Filter

The present invention relates to a software radio apparatus and a signal processing method using the same. More particularly, the internal functional configuration can be reconfigured by an instruction from software corresponding to a plurality of realization means for a designated function. The present invention relates to a software radio and a signal processing method of the software radio.

Generally, a system applied to the product has a signal processing function that requires high speed or low power consumption that is not suitable for processing by software such as application software, operating system (OS), driver software, and the like. There are mixed configurations that can achieve this. At this time, for the purpose of extending the product life due to the versatility of the product or changing the specifications, the replacement of the software executed in the CPU (Central Processing Unit) prepared in advance in the system or the reconfiguration of the field-programmable gate array (FPGA), etc. It is possible to reconfigure the hardware of possible devices. In addition, by performing software reconfiguration of a reconfigurable device such as a digital signal processor (DSP), flexibility can be provided to the corresponding system.

A radio using such a system or technology is called a software radio. To provide the flexibility of these systems, software reconfigurable devices can be reconfigured, such as software replacement of the CPU or reconfigurable FPGAs or DSPs. Accordingly, it is possible to implement a radio corresponding to a plurality of communication schemes or signal processing functions through a device having one hardware.

Moreover, in such a reconfigurable software radio, in order to minimize the influence on the software side by the reconfiguration of the signal processing function side, the software side absorbs the change of the signal processing function side by using the driver software, It enables exchange of information between the OS and the signal processing function.

Fig. 1 is a diagram showing a corresponding example of the configuration of a unit that performs a signal processing function with driver software of a conventional software radio. As shown, Fig. 1 shows an example of correspondence between a hardware signal processing section configuration by an FPGA and a software configuration by a CPU.

1, application software 1, 2,... Corresponding to a communication method. For N, signal processing configurations A, B, and C, which represent a method of realizing a plurality of hardware, and signal processing configurations D, E, F, and signal processing configurations O, P, and Q, respectively, are provided. It can be seen that. Further, it can be seen that driver software X, driver software Y, and driver software Z are provided corresponding to each signal processing configuration for information exchange between the OS or application software and hardware.

By the way, in the software radio, since the application software needs to be changed for each communication method, there is a problem that the number of combinations of the software including the application software and the driver software increases considerably as in the example shown in FIG. . In addition, when combining the software as shown in Figure 1, there is a problem that may increase the number of development process of the software, which may lead to an increase in the possibility that the bug is included in the software.

An object of the present invention for solving the above problems is to minimize the effect on the software side by the reconfiguration of the signal processing function side, and at the same time to realize the minimum number of combinations of software including application software and driver software. To provide a software radio and a signal processing method using the same.

The above object is, according to the present invention, a signal processing unit capable of reconfiguring an internal functional configuration by an instruction from software corresponding to a plurality of realization means for a designated function, and a parameter corresponding to any of the plurality of realization means. In a software radio having a control unit for setting the signal processing unit, the signal processing unit converts the parameter into a parameter corresponding to the function configuration of the signal processing unit when the parameter set by the control unit does not correspond to the functional configuration of the signal processing unit. In the software radio having such a configuration, the control unit is not concerned with the format of the parameter, and it is possible to set the parameter according to the situation of the control unit to the signal processing unit.

Preferably, the designated function refers to functions such as generation of a carrier signal, filtering of a signal, modulation and demodulation of a signal, and conversion of a sampling rate of a signal. In addition, the parameter conversion refers to functions such as bit division, bit insertion, bit merge, numerical addition and subtraction, and multiplication of parameter data. Such a software radio can realize a software radio that can perform parameter conversion without putting a load on the signal processing unit by limiting the function of the signal processing unit and the content of parameter conversion.

Preferably, the signal processor includes a plurality of frequency synthesizers (e.g., orthogonal carrier oscillators 21, 61) in which the signal processor generates a carrier signal of a frequency specified by frequency setting data indicating a change in phase. In the case of one frequency converter, the frequency setting data in a predetermined format set as a parameter from the control unit is divided into bits and set as the frequency setting data of each of the plurality of frequency synthesizers. Accordingly, if the final frequency of the frequency-converted signal is correct, a frequency converter capable of dividing the frequency synthesizer in any way can be realized.

The signal processing unit includes first and second frequency synthesizers (eg, orthogonal carrier oscillators 21 and 61) in which the signal processing unit generates a carrier signal of a frequency specified by frequency setting data indicating a change in phase. In the case of a double conversion frequency converter, the frequency setting data in a predetermined format set as a parameter from the control unit is divided into two frequency setting data, and the MSB (Most Significant) of the divided frequency setting data Bit side is set in the first frequency synthesizer (e.g., orthogonal carrier oscillator 21) for generating a first local signal for performing frequency conversion between the transmit and receive signal and the first intermediate frequency signal, The LSB (Least Significant Bit) side of the frequency setting data has a frequency higher than that of the first intermediate frequency signal and the first intermediate frequency signal. Is set to a second frequency synthesizer (e. G., Perpendicular to the carrier oscillator 61) for generating a second local signal to perform a frequency conversion between the second intermediate frequency signal or a baseband signal. Accordingly, the frequency converter can be operated by freely setting the frequencies of the first frequency synthesizer having a low spurious frequency and the coarse frequency step, and the second synthesizer having a large spurious frequency and subdivided frequency step.

The signal processing unit includes a digital filter (eg, digital filters 91, 92, 93, 94 and digital filters 111, 112) in which the signal processing unit filters the input signal using its impulse response as a coefficient. When the control signal is set, the coefficient of the low pass filter or the complex coefficient band pass filter of the real coefficient set as a parameter is multiplied by the carrier signal corresponding to the frequency setting data set as the parameter from the control unit, and the filter coefficient corresponding to the target frequency is multiplied. Create Thereby, while the frequency characteristic of a digital filter can be set freely by the coefficient which a control part sets as a parameter, the center frequency of a filter can also be set freely by the frequency setting data which a control part sets as a parameter.

The signal processor includes a digital filter (eg, digital filters 91, 92, 93, 94, and digital filters 111, 112) in which the signal processor performs filtering of an input signal using its impulse response as a coefficient. If the value is set, the carrier signal corresponding to the frequency setting data set as a parameter from the control unit is multiplied to the target frequency by multiplying the coefficient of the low pass filter of the real coefficient or the band pass filter of the complex coefficient previously included in the reconstruction data of the signal processing unit. Generate one filter coefficient. Thereby, the center frequency of a digital filter can be set freely by the coefficient which a control part sets as a parameter.

The signal processing unit may include a plurality of sampling rate converters (eg, downsamplers 101 and 102 and downsamplers 113 and 114) for converting a sampling rate of a signal represented by a discrete time sequence. Sampling rate converted data in a predetermined format set as a parameter is divided and set as sampling rate converted data in each of the plurality of sampling rate converters. Accordingly, if the final sampling rate of the sampled signal converted is correct, the sampling rate converter can be divided and configured in any way.

The signal processing unit may include first and second sampling rate converters (eg, downsamplers 101, 102, and downsamplers 113, 114) for converting a sampling rate of a signal expressed by a discrete time sequence into two stages. ), The sampling rate converted data in a predetermined format set as a parameter from the control unit is divided into first sampling rate converted data set in the first sampling rate converters (e.g., downsamplers 101 and 102), The second sampling rate converter (e.g., down samplers 113 and 114) is set as second sampling rate converted data. Accordingly, by sampling rate conversion of the output of the first sampling rate converter by the second sampling rate converter, a signal after the sampling rate conversion specified in the sampling rate conversion data set as a parameter from the control unit can be obtained.

On the other hand, the above object is stored in advance in the signal processing method of the software radio which can reconstruct an internal functional configuration by an instruction from software, corresponding to a plurality of realization means for a designated function according to the present invention. When the specified signal processing parameter does not correspond to an internal functional configuration, it is achieved by a signal processing method using a software radio that converts the parameter into a parameter corresponding to the internal functional configuration.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the same elements in the figures are represented by the same numerals wherever possible. In addition, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

2 is a block diagram showing the configuration of a software radio according to an embodiment of the present invention.

In Figure 2, the received signal received from the antenna 1, RF / IF (Radio Frequency / RF) to convert the frequency of the received signal into an intermediate frequency signal, performing amplification of the level of the received signal or filtering to a desired frequency bandwidth Intermediate Frequency (ADC) is input to an analog to digital converter (ADC) 3 through an analog unit 2. The ADC 3 is an analog-to-digital converter that samples the received signal converted into an intermediate frequency signal and digitalizes it (signalized by a discrete time sequence), and the output of the ADC 3 is It is input to the signal processing section 4 realized by a device such as a field-programmable gate array (FPGA) or a digital signal processor (DSP) capable of reconfiguring the internal functional configuration. The signal processing unit 4 performs designated function processing, such as orthogonal detection, frequency conversion, filtering, and signal demodulation, by, for example, an FPGA or a DSP whose internal functional configuration is reconfigurable.

On the other hand, the transmission signal transmitted from the antenna 1 is subjected to designated functional processing such as signal modulation, frequency conversion, filtering, or quadrature modulation, etc., by a reconfigurable FPGA or DSP of the signal processing section 4. The output signal of the signal processing section 4 is an analog signal by a DAC (Digital to Analog Converter) 5, which is a D / A (Digital to Analog) converter that converts a sampling signal (signal represented by a discrete time sequence) into an analog signal. And input to the RF / IF analog unit 2. The RF / IF analog unit 2 frequency-converts the input transmission signal to the transmission frequency at the time of output from the antenna 1, or amplifies the level of the transmission signal and filters the transmission frequency bandwidth at the same time. Send through.

On the other hand, the RF / IF analog unit 2 and the signal processing unit 4 perform frequency conversion, filtering, or the like, on the basis of operating parameters or control signals supplied from the control unit 6, respectively.

The control unit 6 includes a CPU (Read Only Memory) storing memory executed by the CPU and the CPU, and the like, and replaces application software stored in advance in correspondence with a plurality of communication methods to execute the corresponding processing.

In addition, in the software radio of the present embodiment, an object-oriented way of thinking is applied to function realization by the control unit 6 and the signal processing unit 4 to configure the software and the signal processing function. That is, in the software radio device, when the required function is considered as an object, in order to realize this function, a plurality of means for realizing the signal processing unit 4 are defined as a method, and the method is described from the outside. Prepare a public way, and a private way that can't be seen from the outside that actually does the work inside.

Then, the parameter set for the open system from the control unit 6 is converted into a parameter for the private system in the signal processing unit 4, and the specified function processing is executed using the private system.

FIG. 3 is a diagram showing an example of correspondence between the hardware signal processing unit configuration by the FPGA of the signal processing unit 4 of FIG. 2 and the software configuration by the CPU of the control unit 6. For example, application software 1, 2,... Corresponding to a communication method. Signal processing section 4 by hardware, which is a signal processing configuration A, B, C, and signal processing configuration D, E, F, and signal processing configuration O, P, and Q, respectively, showing a method of realizing a plurality of hardware with respect to N; In a private manner, the control section 6 discloses one hardware configuration (for example, all signal processing configurations A, B, and C) in the signal processing section 4 corresponding to the application software. The driver software X, the driver software Y, and the driver software Z are prepared for taking in a conventional manner and for setting parameters.

Next, with reference to the drawings, an operation for realizing a designated function in the software radio of the present embodiment will be described using the configuration in the specific signal processing section 4 and the parameter designation method by the control section 6.

FIG. 4 is a block diagram showing an example of the configuration of the signal processor 4 of FIG. Here, the signal processor 4 performs orthogonal detection and sampling rate conversion, filtering, and demodulation (detection) of the received signal.

In FIG. 4, the digital quadrature detector 11 inputs an input signal expressed in discrete time sequence, 90 degrees from the real axis signal " cos " of the local signal generated by the orthogonal carrier oscillator 21, and the real axis signal. And multipliers 22 and 23 that multiply the imaginary axial signal " -sin " At this time, the digital quadrature detector 11 converts the complex signal into a complex signal and simultaneously converts the complex signal output of the digital quadrature detector 11 into a 1 / N decimator (downsampled). 12) to perform sampling rate conversion. In addition, the output of the 1 / N decimator 12 is filtered by the filter 13 to the desired signal, and then the signal is demodulated by the detector 14.

Here, the frequency setting data F indicating the change in phase of the phase set by the control unit 6 is input to the orthogonal carrier oscillator 21 of the digital quadrature detector 11. In addition, sampling rate conversion data N set by the control unit 6 is input to the 1 / N decimator 12. At this time, the frequency setting data F and the sampling rate conversion data N are numbers represented by powers of two.

FIG. 5 is a detailed view of the 1 / N decimator 12 of FIG. 4. According to FIG. 4, the 1 / N decimator 12 of the signal processing section 4 includes a CIC filter 12a for converting the sampling rate of the real axis signal of the complex signal output of the digital quadrature detector 11 to 1 / N. And a CIC filter 12b for converting the sampling rate of the imaginary-axis signal of the complex signal output of the digital quadrature detector 11 to 1 / N. According to FIG. 5, the CIC filters 12a and 12b each include an adder 31 and a retarder 32 forming a low pass filter of M section, and a subtractor forming a comb filter of M section ( 33) and a retarder 34, and also have a 1 / N times downsampler 35 provided between the low pass filter and the comb filter. Here, the sampling rate conversion data N set by the control part 6 is set in each downsampler 35 of CIC filter 12a, 12b.

FIG. 6 is a block diagram showing the configuration of the filter 13 used in one configuration example of the signal processing section 4 of FIG. The filter 13 is a real axis signal of the complex signal output of the 1 / N decimator 12 inputted to the input terminal O. I and the 1 / N decimator 12 inputted to the input terminal O. Q. To the imaginary-axis signal of the complex signal output of the?) By the filter realized by the filter coefficient set as a parameter from the control section 6, respectively. ) And low pass filters 41 and 42 for outputting to P. Q. In addition, the filter coefficient set as a parameter from the control part 6 may be previously stored as configuration data of the filter 13 in the signal processing part 4.

FIG. 7 is a block diagram showing a configuration example according to another embodiment of the signal processor 4 of FIG. In the signal processing unit 4, similarly to the configuration examples shown in Figs. 3 to 6, orthogonal detection and sampling rate conversion, filtering, and demodulation (detection) of the received signal are performed. In this configuration example, however, as an example of the software radio after the reconstruction of the signal processing unit 4, two frequency synthesizers are used to divide the frequency of the received signal into two stages and convert the frequency of the received signal to a lower frequency, and at the same time, the frequency of the signal. A down conversion receiver for converting a sampling rate of a signal in two steps in accordance with a decrease in the following description will be described.

As shown in FIG. 7, in this configuration example, the digital quadrature detector 11 converts an input signal represented by a discrete time sequence into a real axis signal of a first frequency local signal in which a quadrature carrier oscillator 21 is generated. and multipliers 22 and 23 that multiply "cos" and the imaginary axis signal "-sin" 90 degrees out of phase with the real axis signal. At this time, the digital quadrature detector 11 converts the complex signal output of the digital quadrature detector 11 into a low IF complex signal and converts (downsamples) the sampling rate of the signal to 1 / N1 as a first step. Input to the first decimator 51, the conversion of the sampling rate.

In addition, the low IF complex signal output of the first decimator 51 is orthogonal to the real axis signal S. I and the imaginary axis signal S. Q of the complex signal output of the first decimator 51. Multiplier 62 and multiplier 63 for multiplying real axis signal " cos " of local signal of second frequency generated by oscillator 61 and imaginary axis signal " -sin " And a subtractor 64 which subtracts the output of the multiplier 63 from the output of the multiplier 62 to form a real axis signal output, and at the same time, the real axis of the complex signal output of the first decimator 51. The signal S.I and the imaginary axis signal S.Q multiply the imaginary axis signal "-sin" of the second frequency local signal generated by the quadrature carrier oscillator 61 and the real axis signal "cos", respectively. A multiplier 65 and a multiplier 66, and an adder 67 that adds the output of the multiplier 66 to the output of the multiplier 65 to form an imaginary axis signal output. By a small mixer 52, and converted to a baseband signal.

On the other hand, the received signal converted into the baseband signal is input to the second decimator 53 which converts (downsamples) the sampling rate of the signal to 1 / N2 again as the second step when the frequency decreases, The conversion is performed, and the signal is demodulated in the detector 14.

Here, the frequency setting data F1 divided from the frequency setting data F indicating the change width of the phase set by the control unit 6 is input to the orthogonal carrier oscillator 21 of the digital quadrature detector 11. In the orthogonal carrier oscillator 61 of the complex mixer 52, frequency setting data F2 divided from frequency setting data F indicating the change width of the phase set by the control unit 6 is input.

In addition, the sampling rate conversion data N1 obtained by dividing the sampling rate conversion data N set by the control unit 6 is input to the first decimator 51. The sampling rate conversion data N2 obtained by dividing the sampling rate conversion data N set by the control unit 6 is input to the second decimator 53.

FIG. 8 is a block diagram showing the configuration of the orthogonal carrier oscillator 21 and the orthogonal carrier oscillator 61 by the frequency synthesizer used in the signal processor 4 of FIG.

As shown in Fig. 8, when the frequency setting data F expressed by the change range ΔΦ of the phase is input to the "j0" bit from the control section 6, the frequency setting data ΔΦ is set to the frequency of the "j1" bit from the MSB side. Data F1 is divided into frequency setting data F2 of "j2" bits on the LSB side. The " j1 " bits on the divided MSB side are cumulatively added by the adder 71 and the phase register 72 forming the phase calculating section to form phase data Af.

Phase data Af of the "j1" bits includes "corse cos" ROM-A 73 having an address signal line of "k1" bits of j1 = k1 and a table for converting phase data into amplitude data; A table for converting phase data into amplitude data having an address signal line of k1 " bits is input to the " corse sin " ROM-B 74, which is recorded as an address signal. As the output signals of the ROM-A 73 and the ROM-B 74, amplitude data cos (F1) and sin (F1) having an "m" bit width are sequentially output. Here, the ROM-A 73 and the ROM-B 74 are ROMs for quantizing and recording the cosine and sine waves of the frequency corresponding to the "j1" bits of the MSB side of the frequency setting data F, respectively. As described above, the adder 71, the phase register 72, and the ROM-A 73 and the ROM-B 74 form an orthogonal carrier oscillator 21 of the digital quadrature detector 11.

On the other hand, the remaining "j2 " bits located on the LSB side from the phase data j1 of the " j0 " bits are " multiplied by the multiplier 81 by the coefficient N1 of the " j0 " bits corresponding to the sampling rate conversion data N1. After conversion to the frequency conversion data F2 'of the j0 "bit, it accumulates and adds by the adder 76 and the phase register 77 which form a phase calculating part, and it becomes phase data Bf'.

Phase data Bf 'of the "j0" bit includes the "fine cos" ROM-C 78 having an address signal line of the "k2" bit of j0> k2 and a table for converting the phase data into amplitude data; A table having address signal lines of " k2 " bits and converting phase data into amplitude data is input to the " fine sin " ROM-D 79 as an address signal. As the output signals of the ROM-C 78 and the ROM-D 79, amplitude data cos (F2) and sin (F2) of "m" bit width are sequentially output. Here, ROM-C 78 and ROM-D 79 are ROMs which quantized and recorded the cosine wave and the sine wave of the frequency corresponding to the remaining "j2" bits of the frequency setting data F, respectively. Thus, the orthogonal carrier oscillator 61 of the complex mixer 52 is formed by the adder 76 and the phase register 77, and the ROM-C 78 and the ROM-D 79.

On the other hand, when two frequency synthesizers of the same bit length are operated at the sampling frequency 1 and the sampling frequency N1, the output frequency also becomes N1, so the sampling frequency of the orthogonal carrier oscillator 61 of the complex mixer 52 is In order to reduce the calculation amount by dropping to 1 / N1 of the sampling frequency of the quadrature carrier oscillator 21 of the digital quadrature detector 11, the frequency setting data F2 is N1 times and corrected by the frequency setting data F2 ', The cumulative addition adds phase data Bf '.

Moreover, according to the above structure, in the signal processing part 4 of this structural example, the local signal of the frequency f produced | generated by the frequency setting data F set by the control part 6 is local of the frequency f1 produced | generated by the frequency setting data F1. A signal and a local signal of a frequency f2 generated by the frequency setting data F2, and are generated by dividing the multipliers 22, 23 of the digital quadrature detector 11 and the multipliers 62, 63, 65 of the complex mixer 52, respectively. 66) enables two-stage frequency conversion.

FIG. 9 is a block diagram showing in detail a configuration example of the first decimator 51 of FIG. As shown, the first decimator 51 is a real axis signal of the complex signal output of the digital quadrature detector 11 input to the input terminal R. I and the digital input to the input terminal R. Q. The complex signal output of the quadrature detector 11 is a imaginary-axis signal, and has a complex band pass filter for filtering the low band signal and the high band signal. Here, the complex band pass filter includes a digital filter 91 which receives the real axis coefficient of the complex filter with respect to the real axis signal of the complex signal output of the digital quadrature detector 11, and the imaginary axis coefficient of the complex filter with respect to the contraction signal. The digital filter 93 which receives the real-axis coefficient of the complex filter with respect to the imaginary signal of the complex signal output of the receiving digital filter 92 and the digital quadrature detector 11, and the imaginary-axis coefficient of the complex filter with respect to the imaginary signal And a digital filter 94 for receiving the output of the digital filter 94 to the output of the subtractor 95 and the digital filter 92 which subtracts the output of the digital filter 93 from the output of the digital filter 91. It is comprised by the adder 96 to add.

Here, the real axis coefficients of the complex band pass filters set in the digital filters 91 and 93 and the imaginary axis coefficients of the complex band pass filters set in the digital filters 92 and 94 are respectively given to the quadrature carrier oscillator 98. The real axis signal cos and the imaginary axis signal -sin of the orthogonal carrier generated by the multiplication are multiplied by the multiplier 99 and the multiplier 100 to the filter coefficient 1 of the reference low pass filter set as a parameter from the control unit 6, respectively. Let it be the generated complex coefficient.

In addition, the frequency of the orthogonal carrier generated by the orthogonal carrier oscillator 98 is a local signal generated by the orthogonal carrier oscillator 21 in which the frequency setting data F1 is set from the frequency F _DIF1 of the input signal of the digital orthogonal detector 11. The frequency is determined based on the frequency subtracted by the subtractor 97. In addition, the filter coefficient 1 set as a parameter from the control part 6 may be a reference band pass filter (complex filter) instead of the reference low pass filter. In this case, the synthesis of the filter coefficient 1 set as a parameter and the output of the orthogonal carrier oscillator 98 is multiplication of complex numbers. Moreover, the filter coefficient 1 set as a parameter from the control part 6 may be memorize | stored in advance as the configuration data of the 1st decimator 51 in the signal processing part 4.

On the other hand, the first decimator 51 is a digital band (91, 92, 93, 94) and the complex band pass filter composed of the subtractor 95 and the adder 96, the unnecessary aliasing is removed. The sampling rate of the complex signal is converted (downsampled) to 1 / N1 by the sampling rate conversion data N1 obtained by dividing the sampling rate N set as a parameter from the control unit 6, and the output terminals S. I and (S. The down sampler 101 for real-axis signals and the down sampler 102 for imaginary-axis signals output to Q) are provided.

FIG. 10 is a block diagram showing in detail a configuration example of the second decimator 53 of FIG. 7. The second decimator 53 complexes the real axis signal of the complex signal output of the plurality of mixers 52 input to the input terminal T. I and the complex mixer 52 input to the input terminal T. Q. The low-pass filters 111 and 112 which perform filtering to cut the high-band signals without passing the high-band signals, respectively, by the characteristics realized by the filter coefficient 2 set as a parameter from the control section 6 to the imaginary axis signal of the signal output. Equipped. Further, the second decimator 53 is cut by the low pass filters 111 and 112 without outputting the high band signal, and the sampling rate of the complex signal from which unnecessary aliasing is removed is set as a parameter from the control unit 6. Down sampler 113 for a real axis signal which is converted (downsampled) to 1 / N2 by sampling rate converted data N2 obtained by dividing sampling rate converted data N, and outputted to output terminals U.I and U.Q. And a down sampler 114 for the imaginary-axis signal.

In addition, the sampling rate conversion data N2 deletes the sampling rate conversion data N set as a parameter from the control unit 6 from the sampling rate conversion data N1 set in the down samplers 101 and 102 of the first decimator 51. Value. In addition, the filter coefficient 2 set as a parameter from the control unit 6 may be stored in advance in the signal processing unit 4 as private data of the second decimator 53.

In the above-described embodiment, a configuration example for realizing the designated function in the signal processing section 4 is described as an example of the receiver. However, the signal processing section 4 is also set by the control section 6 in the case of configuring a transmitter. It is assumed that the parameter is converted into a parameter matching the signal processing function configuration for realizing the function of the transmitter configured in the signal processing unit 4.

In addition, in the above-described embodiment, the signal processing unit 4 is described as being configured as a reconfigurable device such as an FPGA or a DSP, but a reconfigurable device that performs hardware reconfiguration such as an FPGA, or It may consist of only one reconfigurable device of a reconfigurable device which performs software reconfiguration, such as a DSP.

As described above, the software radio of the present embodiment corresponds to a plurality of realization means for the designated function, and includes a signal processing unit 4 capable of reconfiguring the internal functional configuration by instructions from software, and a plurality of realization means. A software radio having a control unit 6 for setting a parameter corresponding to any one of them in the signal processing unit 4, and a signal processing requiring high speed and low power consumption, which are not suitable for processing by the software of the control unit 6; When configuring the signal processing section 4 to realize the function, the software and the signal processing function are configured by applying an object-oriented way of thinking.

Therefore, when a function required for a software radio is considered as an object, in order to realize this function, a plurality of realization means configured in the signal processing section 4 are defined as a method, and an open method that is visible from the outside with respect to this method. By preparing a private method that is not visible from the outside that actually performs the processing inside, the parameter set for the public method from the control unit 6 is converted into a parameter for the private method in the signal processing unit 4. Thus, the effect of reducing the influence on the software of the control section 6 by reconfiguring the signal processing function on the signal processing section 4 side can be obtained.

As a result, the type of driver software to be prepared in the control section 6 is reduced, so that the number of software development steps can be reduced, and the product development period can be shortened and the product cost can be reduced.

In addition, signal processing is limited to simple functions such as generation of carrier signals, frequency conversion, filtering of signals, and sampling rate conversion of signals, and bit division, bit insertion, bit merging, and numerical subtraction of parameter data. By converting the parameter by any of the multiplication and the numerical multiplication, a software radio capable of freely performing the parameter conversion without applying a load to the signal processing unit 4 can be realized.

Therefore, without increasing the type of driver software, for example, a frequency synthesizer with less spurious, a filter having various characteristics and a center frequency, and an effect of free sampling rate conversion can be obtained.

According to the present invention, by setting a parameter format suitable for communication between the control unit and the signal processing unit without involving the internal processing in the signal processing unit with respect to the parameter to be set, the software of the control unit by the reconstruction of the signal processing function side is set. The driver software can be adapted to the control unit side while the influence on the controller is reduced, and the combination of the application software and the software including the driver software can also be minimized. In addition, since the kind of driver software is reduced, sufficient verification of individual driver software can be performed, and the operation stability of the entire software radio can be improved. In addition, since the number of software development processes is reduced, the product development period can be shortened and the product cost can be reduced.

In addition, by limiting the functions and parameter conversion contents in the signal processing section, it is possible to realize a software radio that can perform parameter conversion without putting a load on the signal processing section. As a result, the effect on the software of the controller by the reconfiguration on the signal processing function side can be made smaller, and the effect on the software can be minimized.

On the other hand, if the final frequency of the frequency-converted signal is correct, a frequency converter that can be configured by dividing the frequency synthesizer in any way can be realized. Accordingly, more flexibility can be given to a software radio including a frequency converter, and in a device having one hardware, a radio corresponding to a plurality of communication frequencies can be easily realized without increasing the driver software. Can achieve the effect.

In addition, the frequency converter is operated by freely setting the frequencies of the first frequency synthesizer having a low spurious frequency and the approximate frequency step, and the second frequency synthesizer having a large spurious frequency and fine frequency step, thereby increasing the digital driver frequency without increasing the driver software. It is possible to realize a frequency converter in which a uniformly occurring spurious unique to a synthesizer is limited to the vicinity of a carrier.

The frequency characteristic of the digital filter can be freely set by a coefficient set by the controller as a parameter, and the center frequency of the filter can be set freely by the frequency setting data set by the controller as a parameter. As a result, it is possible to obtain an effect that a free frequency characteristic and a filter of any center frequency can be simply configured without increasing the driver software.

In addition, the center frequency of the digital filter can be freely set by the frequency setting data set by the controller as a parameter. Thereby, the effect that the filter of the frequency characteristic set previously by the coefficient contained in the signal processing part reconstruction data can be comprised easily in any center frequency, without increasing driver software.

Also, if the final sampling rate of the sampled rate converted signal is correct, the sampling rate converter can be divided and configured in any way. As a result, more flexibility can be given to a software radio apparatus including a sampling rate converter, and in an apparatus having one hardware, sampling can be performed freely corresponding to a plurality of communication frequencies easily without increasing the driver software. The effect of realizing a radio capable of selecting a rate can be obtained.

Claims (10)

A signal processing unit capable of reconfiguring an internal functional configuration in response to a plurality of realization means for a designated function, by an instruction from software; A control unit including a single driver software for setting a single open parameter corresponding to an interface of the signal processing unit as data for executing a functional configuration inside the signal processing unit, The signal processing unit, A function processing unit corresponding to the plurality of realization means; A parameter processing unit for converting the public parameter set by the single driver software into a private parameter required by the function processing unit, And the function processing unit executes the designated function using the converted private parameter. The method of claim 1, And the designated function comprises at least one of generation of a carrier signal, filtering of the signal, modulation and demodulation of the signal, and conversion of the sampling rate of the signal. The method of claim 1, And the conversion of the public parameter comprises at least one of bit division, bit insertion, bit merge, addition and subtraction of a numerical value, and multiplication of the numerical value for the data set to the public parameter. The method of claim 3, wherein When the signal processing unit is composed of a frequency converter having a plurality of frequency synthesizers for generating a carrier signal of a frequency specified by frequency setting data indicating a change in phase, And the parameter processing unit divides the frequency setting data according to a predetermined format set as the open parameter from the control unit into the frequency setting data of the plurality of frequency synthesizers. The method of claim 3, wherein When the signal processing unit is configured as a frequency converter of a double conversion method including a first and a second frequency synthesizer for generating a carrier signal of a frequency specified by frequency setting data indicating a change in phase, The parameter processing unit bit-divides the frequency setting data in a predetermined format set as the public parameter from the control unit into two frequency setting data, and transmits / receives a signal to the MSB (Most Significant Bit) side of the divided frequency setting data. Set the frequency setting data of the first frequency synthesizer to generate a first local signal for performing frequency conversion between the intermediate frequency signals of 1, and set the LSB (Least Significant Bit) side of the divided frequency setting data to the first signal. Setting the frequency setting data of a second frequency synthesizer that generates a second local signal for performing frequency conversion between the intermediate frequency signal and a second intermediate frequency signal or a baseband signal having a frequency lower than that of the first intermediate frequency signal. Characterized by a software radio. The method of claim 3, wherein When the signal processing unit is configured as a digital filter for filtering the input signal by using its impulse response as a coefficient, The parameter processing unit multiplies a coefficient of a low pass filter of a real coefficient or a band pass filter of a complex coefficient set by the control unit with the carrier signal corresponding to the frequency setting data set as the disclosure parameter by the control unit. And a filter coefficient corresponding to the frequency of the software radio. The method of claim 3, wherein When the signal processing unit is configured as a digital filter for filtering the input signal by using its impulse response as a coefficient, The parameter processing unit multiplies a coefficient of a low pass filter of a real coefficient or a band pass filter of a complex coefficient previously included in the reconstruction data of the signal processing unit by a carrier signal corresponding to the frequency setting data set as the public parameter from the control unit. And generating a filter coefficient corresponding to the target frequency. The method of claim 3, wherein When the signal processing unit is composed of a plurality of sampling rate converters for converting the sampling rates of signals expressed in discrete time sequences, And the parameter processing unit divides the sampling rate converted data in a predetermined format set as the public parameter from the control unit, and sets the sampling rate converted data in each of the plurality of sampling rate converters. The method of claim 3, wherein  When the signal processing unit is composed of first and second sampling rate converters for dividing and converting the sampling rate of the signal represented by the discrete time sequence in two stages, The parameter processing unit divides the sampling rate converted data in a predetermined format set as the open parameter from the control unit into first sampling rate converted data set in the first sampling rate converter, and supplies the second sampling rate converter to the second sampling rate converter. Software radio set to 2 sampling rate conversion data. In a signal processing method using a software radio having a signal processing unit capable of reconfiguring an internal functional configuration by instructions from software, corresponding to a plurality of realization means for a designated function, Setting, by the single driver software, a single open parameter corresponding to the interface of the signal processing unit as data for executing a functional configuration inside the signal processing unit; Converting, by the parameter processing unit, the public parameter set by the single driver software into a private parameter required by a function processing unit corresponding to the plurality of realization means; And performing, by the function processing unit, the designated function by using the converted private parameter.

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