KR100956946B1 - Method for programming nonvolatile memory device - Google Patents

Abstract

Nonvolatile memory that improves the data detection margin during read operation by normally insulating and destroying the anti-fuse of OTP (One Time Programmable) unit cell during write operation, and thereby improving the reliability of read operation of OTP unit cell by preventing malfunction A write method of a device is provided, wherein the write method of a nonvolatile memory device having an OTP unit cell is characterized by applying a pulse write voltage having a plurality of cycles during a write operation.

Nonvolatile Memory Devices, Unit Cells

Description

Write method of nonvolatile memory device {METHOD FOR PROGRAMMING NONVOLATILE MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a semiconductor memory device, and more particularly, to a method of driving a nonvolatile memory device, and more particularly, to a nonvolatile memory device having a one time programmable unit cell (OTP). It is about how to write.

The OTP unit cell is formed in a volatile or nonvolatile memory device such as DRAM, EEPROM, or FLASH, and is used for memory repair. In addition, a mixed-signal chip in which an analog chip and a digital chip are mixed is used for internal trimming and frequency trimming.

In general, an OTP unit cell includes an antifuse consisting of a metal-oxide-semiconductor field effect transistor (MOSFET) (hereinafter referred to as a MOS transistor), and one or more MOS transistors. The OTP unit cells are formed in a single or array form in each memory chip and used for repair or trimming.

1 is an equivalent circuit diagram illustrating a general OTP unit cell.

Referring to FIG. 1, a typical OTP unit cell includes an antifuse ANT_FS connected between an input terminal A and a node B to which a write voltage is input, and a node B and a bit line BL (in a read operation). Transistors NM1 and NM2 having n-channels connected in series between the data output stages).

2 is a diagram illustrating a memory cell array of a general nonvolatile memory device.

Referring to FIG. 2, a memory cell array of a general nonvolatile memory device includes a plurality of unit cells UC arranged in a matrix type. In this case, as shown in FIG. 1, the unit cell UC includes transistors NM1 and NM2 having n-channels connected in series with each other, and one antifuse ANT_FS connected in series with these NM1 and NM2. It is provided.

Also, a memory cell array of a general nonvolatile memory device includes a plurality of word lines WL0 to WLn (where n is a natural number) for selecting the second transistor NM2 of the unit cell UC. In addition, a plurality of bit lines BL0 to BLm (in which m is a natural number) for sensing data and transmitting the data to a drain of the first transistor NM1 may be provided. In addition, a plurality of control lines CL0 to CLn for controlling the operation of the first transistor NM1 by supplying a bias voltage to the gate of the first transistor NM1 is provided.

Hereinafter, a write and read operation of a nonvolatile memory device according to the related art will be described.

3 is an operation waveform diagram of a nonvolatile memory device according to the related art during a write operation.

Operation mode / stage A CL0 ~ CLn WL0 ~ WLn BL0 ~ BLm Write operation VPP H H or L VSS Read operation VDD H H or L VSS

Write operation

Referring to Table 1 and FIG. 2, a high voltage VPP is applied to the input terminal A during the write operation period tpgm. In addition, a first control signal having a logic level H (hereinafter referred to as logic high) corresponding to the power supply voltage VDD is input to the control lines CL0 to CLn. In addition, among the word lines WL0 to WLn, the selected word line has a logic level (H) corresponding to a logic high (H), and an unselected word line corresponds to a ground voltage (VSS). The second control signal is input. In addition, the ground voltage VSS is applied to the bit lines BL0 to BLm.

In the case of a selection cell (a cell in which the gate insulating film of the anti-fuse is broken down during a write operation), the first and second transistors (NM1 and NM2) are turned on by the first and second control signals to be selected. The bit line is electrically connected to the node B, which causes the node B to receive the ground voltage VSS. As a result, a high electric field is formed between the gate and the substrate of the anti-fuse ANT_FS formed of the MOS transistor to destroy the gate insulating film formed between the gate and the substrate. Thus, the gate and the substrate of the antifuse ANT_FS are electrically shorted.

Read operation

After the write operation is completed, the power supply voltage VDD is applied to the input terminal A, and the first control signal in a logic high (H) state is input to the control lines CL0 to CLn. The second control signal of logic high (H) is selected as the selected word line among the word lines WL0 to WLn, and a logic low (L) state is input to the unselected word line. In addition, the bit lines BL0 to BLm are connected to a sensing unit (not shown). As a result, a current path leading to the input terminal A, the antifuse ANT_FS, the first and second transistors NM1 and NM2, and the bit line is formed. Therefore, the power supply voltage VDD applied to the input terminal A is transferred to the bit line and detected.

However, the following problem occurs in the write operation of the conventional nonvolatile memory device.

As illustrated in FIG. 3, in a write operation of a nonvolatile memory device according to the related art, a write operation of continuously insulating a gate insulating film of an anti-fuse ANT_FS by continuously applying a write voltage to a predetermined size during a write operation period tpgm. It is performed in a static stress mode. In this static stress method, electrons are trapped at the interface of the gate insulating film of the anti-fuse ANT_FS, thereby reducing the electric field during the write operation. For this reason, the electric field is not sufficiently applied to the gate insulating film of the antifuse during the write operation, and the dielectric breakdown of the gate insulating film is not normally performed. Accordingly, in the read operation, a sensing margin of data is lowered and a malfunction occurs, thereby causing a problem in that the read operation reliability of the OTP unit cell is degraded.

Accordingly, the present invention has been proposed to solve the problem according to the prior art, and by properly insulating and destroying the anti-fuse of the unit cell during the write operation to improve the data detection margin during the read operation, thereby preventing the malfunction OTP unit cell An object of the present invention is to provide a writing method of a nonvolatile memory device capable of improving the reliability of a read operation.

According to an aspect of the present invention, there is provided a nonvolatile memory device including an OTP unit cell, wherein a write voltage having a plurality of cycles is applied during a write operation. A method of writing a memory device is provided.

According to the present invention having the above-described configuration, the write operation is performed in a manner of applying a pulse type write voltage to which a frequency is added during a write operation of the nonvolatile memory device. Electrons trapped at the interface of the gate insulating layer of the fuse to reduce the electric field may be removed from the interface of the gate insulating layer to minimize the reduction of the electric field, thereby preventing malfunction and thereby improving the read operation reliability of the OTP unit cell.

The write method of a nonvolatile memory device according to the present invention does not perform a write operation in a manner of applying a fixed voltage having a fixed size to a unit cell (static stress method), but in the form of a pulse having a frequency added thereto. The write operation is performed by applying a write voltage of (pulse type). That is, by applying a pulse-type write voltage having a plurality of periods to the unit cell, electrons trapped at the interface of the gate insulating film of the antifuse in the unit cell during the write operation to reduce the electric field are turned on and off of the pulse. The electric field reduction is minimized by removing from the interface of the gate insulating film between the sections.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. In addition, in describing each of the embodiments, a memory cell array structure of the nonvolatile memory device illustrated in FIG. 2 will be described as an example. However, the technical idea of the present invention is not limited thereto. In addition, "section" described throughout the specification corresponds to the X-axis in each waveform diagram means time. In addition, in each embodiment, other bias conditions (word line voltage, bit line voltage, control signal, etc.) other than the write voltage during the write operation are the same as in the general method.

Example 1

4 is a waveform diagram illustrating a write method of a nonvolatile memory device according to the first embodiment of the present invention.

Referring to FIG. 4, in the nonvolatile memory device according to the first embodiment of the present invention, a pulse type write voltage (see A) having a plurality of cycles C1 to C4 is applied during a write operation period tpgm. do. At this time, the write voltage has the same amplitude V for each cycle C1 to C4.

Each of the periods C1 to C4 has the same section. In addition, each of the periods C1 to C4 is a pulse to which a voltage having a voltage magnitude different from the voltage magnitude applied to the on period t1 (hereinafter, referred to as a first period) of the pulse and applied to the first period t1 is applied. It consists of an off section t2 (hereinafter referred to as a second section). Preferably, a voltage having a voltage level lower than the voltage applied in the first section t1 is applied to the second section t2. More preferably, the high voltage VPP is applied in the first section t1, and the ground voltage (or negative voltage) is applied in the second section t2. In addition, the first section t1 has a section longer than the second section t2. Preferably, the second section t2 has a section of 1/2 to 1/10 of the first section t1.

The writing method according to the first embodiment of the present invention with reference to FIG. 2 is as follows.

First, during the first period t1 of each of the cycles C1 to C4, the high voltage VPP is applied to the unit cell UC to insulate and destroy the gate insulating film of the antifuse ANT_FS. During the second period t2, the high voltage VPP applied to the unit cell UC is cut off, and a ground voltage or a negative voltage is applied to one end of the anti-fuse ANT_FS. As a result, electrons trapped at the interface of the gate insulating layer of the antifuse ANT_FS are removed during the first period t1.

Example 2

FIG. 5 is a waveform diagram illustrating a write method of a nonvolatile memory device according to a second exemplary embodiment of the present invention.

Referring to FIG. 5, the write method of the nonvolatile memory device according to the second exemplary embodiment of the present invention has a pulse-type write voltage having a plurality of cycles C1 to C4 during the write operation period tpgm as in the first exemplary embodiment. (See A). However, like the first embodiment, the write voltage does not have the same amplitude V for each of the cycles C1 to C4, but has different amplitudes V1 to V4. At this time, the amplitude of the write voltage increases as the cycles C1 to C4 are repeated. That is, the amplitude becomes larger as it goes from C1 to C2 to C3 to C4. In addition, the amplitude difference between each period C1-C4 may or may not be the same.

Example 3

6 is a waveform diagram illustrating a write method of a nonvolatile memory device in accordance with a third embodiment of the present invention.

Referring to FIG. 6, in the nonvolatile memory device according to the third embodiment of the present invention, as in the second embodiment, the amplitude of the write voltage does not increase as the cycles C1 to C4 are repeated, but rather the cycles C1 to C4. It decreases as C4) is repeated. That is, the amplitude becomes smaller as it goes from C1 to C2 to C3 to C4. At this time, the amplitude difference between each period (C1 ~ C4) may or may not be the same.

Example 4

FIG. 7 is a waveform diagram illustrating a write method of a nonvolatile memory device in accordance with a fourth exemplary embodiment of the present invention.

Referring to FIG. 7, the write method of the nonvolatile memory device according to the fourth exemplary embodiment of the present invention has the same amplitude for each period C1 to C4 during the write operation period tpgm, as in the first exemplary embodiment. A pulse write voltage (see A) with periods C1 to C4 is applied. However, the lengths of the cycles C1 to C4 are not the same as in Embodiment 1, but the lengths of the cycles are different for each cycle C1 to C4. At this time, the length of each cycle C1 to C4 increases as the cycles C1 to C4 are repeated. That is, the length of the cycle becomes larger as it goes from 'C1 → C2 → C3 → C4'. In this case, the interval length difference between the periods C1 to C4 may or may not be the same.

Example 5

FIG. 8 is a waveform diagram illustrating a write method of a nonvolatile memory device in accordance with a fifth exemplary embodiment of the present invention.

Referring to FIG. 8, the write method of the nonvolatile memory device according to the fifth embodiment of the present invention is a combination of the first embodiment and the third embodiment, wherein a period in which the amplitude of the write voltage is set, for example, one half of the entire period. The period increases as the cycle repeats around 'C3' corresponding to the cycle, and decreases as the cycle repeats from 'C3'. At this time, the amplitude difference between each period (C1 ~ C5) may or may not be the same.

Example 6

FIG. 9 is a waveform diagram illustrating a write method of a nonvolatile memory device in accordance with a sixth embodiment of the present invention.

Referring to FIG. 9, the write method of the nonvolatile memory device according to the sixth embodiment of the present invention is the reverse of that of the fifth embodiment, and corresponds to a period in which the amplitude of the write voltage is set, for example, one half of the entire period. It decreases as the cycle is repeated around 'C3' and increases as the cycle is repeated from 'C3'. At this time, the amplitude difference between each period (C1 ~ C5) may or may not be the same.

As described above, although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that this is for the purpose of description and not of limitation. In addition, as in the fourth embodiment, an embodiment in which the intervals are different for each period and other embodiments in which the amplitudes are different in each period, for example, the fourth and second embodiments, the fourth and third embodiments, and the fourth embodiment The combination of Example 5, Example 4, and Example 6, etc. is possible. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention through the combination of Examples 1 to 6.

1 is an equivalent circuit diagram illustrating a typical OTP unit cell.

FIG. 2 illustrates a memory cell array of a nonvolatile memory device having a typical OTP unit cell. FIG.

3 is a waveform diagram illustrating a method of writing a nonvolatile memory device according to the prior art.

4 is a waveform diagram illustrating a write method of a nonvolatile memory device according to the first embodiment of the present invention;

FIG. 5 is a waveform diagram illustrating a write method of a nonvolatile memory device according to Embodiment 2 of the present invention; FIG.

FIG. 6 is a waveform diagram illustrating a write method of a nonvolatile memory device according to Embodiment 3 of the present invention; FIG.

FIG. 7 is a waveform diagram illustrating a write method of a nonvolatile memory device according to Embodiment 4 of the present invention; FIG.

FIG. 8 is a waveform diagram illustrating a write method of a nonvolatile memory device according to Embodiment 5 of the present invention; FIG.

FIG. 9 is a waveform diagram illustrating a write method of a nonvolatile memory device according to Embodiment 6 of the present invention; FIG.

Claims (27)

A write method of a nonvolatile memory device having an OTP unit cell, When writing, A write method of a nonvolatile memory device which applies a pulse type write voltage having a plurality of cycles. The method of claim 1, And each of the cycles has the same length as each other. The method of claim 2, And the amplitude of the write voltage is the same every period. The method of claim 2, And the amplitude of the write voltage is different for each period. The method of claim 4, wherein And the amplitude of the write voltage increases as the cycle is repeated. The method of claim 4, wherein And the amplitude of the write voltage decreases as the cycle is repeated. The method of claim 4, wherein The amplitude of the write voltage increases as the cycle is repeated up to a set period, and decreases as the cycle is repeated from the set period. The method of claim 4, wherein The amplitude of the write voltage decreases as the period is repeated until the set period, and increases as the period is repeated from the set period. 9. The method according to any one of claims 1 to 8, Each of the periods comprises a first section and a second section in which a voltage having a voltage level different from that of the voltage applied to the first section is applied. 9. The method according to any one of claims 1 to 8, Each of the cycles comprises a first section and a second section to which a voltage having a voltage magnitude lower than that applied in the first section is applied. The method of claim 10, The first period is longer than the second period. The method of claim 10, And the second section is 1/2 to 1/10 of the first section. The method of claim 10, A high voltage is applied in the first section, and a ground voltage or a negative voltage is applied in the second section. The method of claim 1, And each of the cycles has a different length from each other. The method of claim 14, The length of the cycle increases as the cycle is repeated. The method of claim 14, And the length of the cycle becomes smaller as the cycle is repeated. The method of claim 14, And the amplitude of the write voltage is the same in each period. The method of claim 14, And the amplitude of the write voltage is different for each period. The method of claim 18, The amplitude of the write voltage increases as the period is repeated. The method of claim 18, The amplitude of the write voltage decreases as the period is repeated. The method of claim 18, The amplitude of the write voltage increases as the cycle is repeated until the set period, and decreases as the cycle is repeated from the set period. The method of claim 18, The amplitude of the write voltage decreases as the period is repeated until the set period, and increases as the period is repeated from the set period. The method according to any one of claims 14 to 22, Each of the periods comprises a first section and a second section in which a voltage having a voltage level different from that of the voltage applied to the first section is applied. The method according to any one of claims 14 to 22, Each of the cycles comprises a first section and a second section to which a voltage having a voltage magnitude lower than that applied in the first section is applied. The method of claim 24, The first period is longer than the second period. The method of claim 24, And the second section is 1/2 to 1/10 of the first section. The method of claim 24, A high voltage is applied in the first section, and a ground voltage or a negative voltage is applied in the second section.

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