KR100945340B1 - A data interface synchronization method for base station system operating multiple standard - Google Patents

Abstract

The present invention provides a synchronization signal in an idle slot inside a data group slot for a data interface between a baseband processor and an RF processor in a base station system accommodating multiple standards, wherein the synchronization signal is in a layered frame. Provided is a data interface synchronization method for inserting and inserting an IDLE slot into a data group slot. Therefore, the present invention can reduce the load in the module processor by inserting the synchronization signal into the data interface between the baseband processing unit and the RF processing unit of the mobile communication base station system, in particular can utilize the idle slot (IDLE) portion transmitted without meaning This can reduce the overhead area of the master frame.

Multi-Standard, Interface Sync, Idle Slot, Mart Frame, Sync Signal

Description

A method for synchronizing data interfaces in a base station system that accepts multiple standards {A DATA INTERFACE SYNCHRONIZATION METHOD FOR BASE STATION SYSTEM OPERATING MULTIPLE STANDARD}

1 is a block diagram of a conventional base station system.

2 is a diagram illustrating a synchronization signal transmission method in a conventional TDM scheme.

3 is a diagram illustrating a synchronization method in a conventional layered frame structure.

4 is a diagram illustrating a concept of a data interface synchronization method according to the present invention in a hierarchical frame structure.

5 is a flowchart illustrating a data interface synchronization method according to the present invention in a base station system using multiple standards.

The present invention relates to a synchronization transmission method between a baseband processor and a radio frequency (RF) processor, and more particularly, to a data interface synchronization method suitable for a base station system that accommodates multiple standards.                         

1 is a block diagram of a conventional base station system including a main processor 10, a baseband processor 20, and an RF processor 30.

Referring to FIG. 1, the conventional base station system is configured to service only one standard (CDMA / GSM / WCDMA) in units of a base station (BTS). Therefore, in the base station system, the interface between the baseband processor 20 and the radio frequency (RF) processor 30 is performed in a time division multiplexing (TDM) scheme.

That is, as shown in Fig. 2, the baseband processing unit (hereinafter referred to as BB processing unit) 20 and the RF processing unit 30 are the antenna and the carrier (carrier) to each data (I, Q) with sync bits for one frame. Pairs are sent.

With the recent rapid development of mobile communication system technology and the advent of the global era, the necessity of a global communication system has become urgent, and this necessity has led to the emergence of base station systems that accommodate multiple standards within a single system. It became.

However, since the interface area between the conventional BB processing unit 20 and the RF processing unit 30 uses only a simple TDM method, there is a limitation in processing multiple standards. That is, the interface synchronization method between the BB processing unit 20 and the RF processing unit 30 of the conventional base station system was able to ensure stability by using an individual synchronization signal transmission method (ex. EvenSec, etc.) by the TDM method. However, in a structure that accommodates multiple standards, one standard interface method (TDM) cannot handle multiple standards. Accordingly, a layered frame structure as shown in FIG. 3 has been proposed to perform interface synchronization in a base station system that accommodates multiple standards.

The hierarchical frame structure shown in FIG. 3 accommodates all the standards (CDMA / GSM / WCDMA) in the data interface area between the BB processing unit 20 and the RF processing unit 30. In view of the characteristics of the scheme, CDMA and GSM / It is recommended that the format be divided into two areas of WCDMA.

In the conventional TDM scheme, when the data interface synchronization between the baseband processor 20 and the RF processor 30 is synchronized, the data path and the synchronization signal path are clearly distinguished, but the hierarchical frame structure shown in FIG. 2 is synchronized using only one data interface. There is a problem that needs to be corrected. That is, the data transmission synchronization signal is included in the data interface between the baseband processor 20 and the RF processor 30.

That is, one master frame has a period of X msec, and the period of the master frame is determined in consideration of the capacity of the system and the processing speed of the link. The master frame is again divided into any number of timeslots, and the arbitrary number of timeslots includes data group slot bundles SG which are bundles of data group slots S divided by control slot CTRL units. At this time, the maximum number of data group slots S is L, and the maximum number of data group slots is N.

One data group slot bundle SG includes at least one control slot CTRL, one idle slot IDLE, and up to L data group slots S1 to SL. In addition, one or more chip information is carried in one data group slot S and the maximum number of chips is four.

In the above-described hierarchical frame structure, a synchronization clock necessary for data transmission is included in the data group slot S in the data interface between the BB processing unit 20 and the RF processing unit 30. Therefore, when the BB processor 20 and the RF processor 30 are initialized, if the number of slots is known in advance, synchronization may be performed for each slot. On the basis of the master frame unit, the number of data group slots S is differently allocated between CDMA and GSM / WCDMA. That is, in case of CDMA, 24 data group slots (S20, L = 24) are defined between two control slots (CTRL) of a master frame, and in case of GSM or WCDMA, between two control slots (CTRL) of a master frame. 20 data group slots S20 and L = 20 are defined. Of course, the same slot can be allocated to both CDMA and WCDMA / GSM, but in this case, the overhead of either standard system is increased and efficiency is inevitably separated into CDMA and GSM / WCDMA. It is defined.

As described above, in the conventional hierarchical frame structure, the BB processing unit 20 and the RF processing unit 30 recognize the number of data group slots (S20 or S24) at initialization, so that each data group slot (S) and control slot (CTRL) are recognized. Every time motivated. However, the conventional synchronization method has a problem in that the load of the module processor is increased because synchronization is performed too frequently. In addition, since the number of data group slots S (L = 20 or L = 24) is differently allocated between the CDMA and the WCDMA in units of master frames, the BB processing unit 20 and the RF processing unit 30 each module has a standard system ( At least two synchronization signals (clocks) must be maintained in accordance with CDMA / WCDMA. As a result, the load increases due to the synchronization of the two clocks and the frequent generation of the corresponding synchronization signals.

 Accordingly, an object of the present invention is to provide an effective synchronization signal method of a data interface section between a baseband processor and an RF processor inside a base station.

In the base station system to accommodate the multiple standards according to the present invention in order to achieve the above object, the data interface synchronization method is a synchronization signal in the data interface section between the baseband processor and the RF processor-the synchronization signal is a hierarchical frame ( Layered frame) is inserted into the IDLE slot in the data group slot.

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Preferably, the baseband processor and the RF processor check the synchronization signal during initialization and during data transmission to synchronize interface synchronization.

In order to achieve the above object, in the baseband processing unit and the RF processing module for transmitting a mutual synchronization signal through a hierarchical frame structure, the data interface synchronization method according to the present invention is a data group slot constituting a hierarchical frame in each module A synchronization signal is inserted into an internal idle slot and transmitted to a counterpart module to synchronize data interface.

Preferably, the synchronization signal is transmitted in units of frame slots.

In order to achieve the above object, a data interface synchronization method in a base station system accommodating multiple standards according to the present invention includes determining a transmission speed between a baseband processor and an RF processor; Determining a master frame period to accommodate the determined rate; Defining a link interface, a data group slot number, and a data group slot bundle for each service standard to be provided by the base station system;

Inserting and transmitting a synchronization signal into a idle slot (IDLE) in a defined data group slot bundle; Checking the synchronization signal inserted into the idle slot to synchronize data interface.

Preferably, the data interface synchronization checks the synchronization signal at system initialization and during data transmission to synchronize the interface.

The present invention is applied in a base station (BTS) system that accommodates multiple standards (CDMA / GSM / WCDMA). However, the present invention can also be applied to communication systems operating according to other standards. Hereinafter, preferred embodiments of the present invention will be described in detail.

Data communication area between baseband processor (hereinafter referred to as BB processor) and RF processor according to mobile communication base station system has shifted from the concept of accommodating a single standard system to a concept of accommodating multiple standards in one base station rack. In addition, plans to accommodate multiple standards are being considered.

The layered frame structure, which is emerging as a physical protocol structure of the data interface section, accommodates both CDMA / WCDMA in the data interface region of the BB processing section and the RF processing section, and the recommendation is divided into two areas of CDMA and WCDMA. It is recommended to use separate formats.

The present invention proposes a synchronization signal transmission method between a BB processor and an RF processor of a base station (BTS) system. To this end, the present invention uses the idle slot IDLE of the hierarchical frame, that is, the idle slot IDLE inside the data group slot bundle GS as a synchronization slot.

4 is a hierarchical frame structure applied to the present invention, and FIG. 5 is a flowchart illustrating a data interface synchronization method according to the present invention in a base station system using multiple standards.

4 and 5, in a hierarchical frame structure, one master frame has a period of X msec, and the period is determined according to a capacity of a system and a processing speed of a link. The master frame is divided into a plurality of timeslots, and the plurality of timeslots are composed of a group of data group slots SG, which is a group of data group slots S divided by a control slot CTRL. At this time, the number of data group slots (S) is at most L, the group of data group slots is at most N, each slot is defined as a byte (Byte stage).

The one data group slot bundle SG includes at least one control slot CTRL, one idle slot IDLE, and up to L data group slots S1 to SL. In addition, one or more chip information is carried in one data group slot S and the maximum number of chips is four.

In the hierarchical frame structure as described above, the present invention uses the idle slot IDLE of the hierarchical frame, that is, the idle slot IDLE in the data group slot bundle GS as a synchronization slot. Therefore, it is mutually defined that the idle slot is used as a synchronization part in the interface format definition step when the BB processor and the RF processor module are manufactured.

That is, the user determines the transmission speed between the BB processor module and the RF processor module when designing the mobile communication base station (S10). After the transmission rate is determined, the period of the master frame suitable for the link that accommodates the transmission rate is determined, and then the link interface, data group slot (S), and data group slot bundle (GS) are defined for each service standard to be provided by the base station system. (S11, S12).

Once the necessary rules are defined, the BB processor and the RF processor utilize the idle slot in the data group slot bundle GS as the data synchronization signal part between the BB processor and the RF processor module. That is, the BB processor and the RF processor insert and transmit their own synchronization signals inside the idle slot (S13, S14). Therefore, the BB processing unit and the RF processing unit may naturally synchronize by checking the synchronization signals promised at each time only at a specific time point (IDLE slot) (S15).

In addition, even after the initialization is completed, the BB processing unit and the RF processing unit can easily interface synchronization by checking only the idle slot portion during data transmission. At this time, the value for the synchronization signal inserted into the idle slot can be defined and used by the prior agreement of the BB processing unit and the RF processing unit, and only the number of bytes of the idle slot determined according to the period of the master frame needs to be kept.

In addition, assuming that the base station system accommodates the multi-standard, the most efficient method of utilizing the present invention is to take some overhead increase in the interface part for a specific standard service and to support the message of all the standards supported by the system. To match the frame format. Although the present invention cannot synchronize the CDMA and WCDMA data interfaces at the same time, the data interface format can be sufficiently matched by increasing the overhead of a specific standard or by adjusting the antenna path allocation or other capacity.

As described above, the present invention inserts and transmits a synchronization signal to a data interface between a baseband processor and an RF processor of a mobile communication base station system. That is, the present invention inserts its own synchronization signal into the idle slot IDLE, so that the synchronization can be naturally achieved by checking a predefined value only at the corresponding time point when the baseband processor and the RF processor are initialized. Therefore, the present invention can reduce the load in the module processor compared to the conventional synchronization method in the hierarchical frame structure, and in particular, can utilize the idle slot portion transmitted without meaning, thereby reducing the overhead area of the master frame.

 In addition, although the present invention has been described with reference to the embodiments illustrated in the drawings, this is merely exemplary and will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. . Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (7)

delete In a base station system that accommodates multiple standards, And inserting a synchronization signal in a data interface section between the baseband processor and the RF processor, wherein the synchronization signal is inserted into an idle slot in a data group slot in a layered frame. Data interface synchronization method. The method of claim 2, wherein the baseband processing unit and the RF processing unit A data interface synchronization method characterized in that interface synchronization is performed by checking synchronization signals during system initialization and data transfer. In the baseband processor and the RF processor module for transmitting a mutual synchronization signal through a layered frame, And synchronizing data interface synchronization by inserting a synchronization signal into an idle slot in a data group slot constituting the hierarchical frame and transmitting the synchronization signal to a counterpart module. The method of claim 4, wherein the synchronization signal is Data interface synchronization method characterized in that the transmission in the idle slot unit. In a base station system that accommodates multiple standards, Determining a transmission rate between the baseband processor and the RF processor; Determining a master frame period to accommodate the determined rate; Defining a link interface, a data group slot number, and a data group slot bundle for each service standard to be provided by the base station system; Inserting and transmitting a synchronization signal into a idle slot (IDLE) in a defined data group slot bundle; And synchronizing the data interface by checking the synchronization signal inserted into the idle slot. The method of claim 6, wherein the data interface synchronization is A data interface synchronization method characterized in that interface synchronization is performed by checking synchronization signals during system initialization and data transfer.

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