KR100943284B1 - Pad structure of chip on glass package liquid crystal display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the formation of an auto probe inspection pattern on a pad in a liquid crystal display device having a COG structure in which a driving IC is directly mounted on a substrate.

Before attaching the driving IC, the liquid crystal panel is inspected for defects. At this time, the liquid crystal panel needs to input an image signal to the gate wiring and the data wiring, and the auto probe has a needle that can input a signal by contacting each wiring. And the needle is brought into contact with the gate face of the liquid crystal panel and a part of the data pad to input an image signal for defect inspection. At this time, since the pad portion in contact with the needle of the autobub portion should be conductive, the protective layer formed on the pad is removed.

However, as described above, the pad portion, in which the protective layer is removed and opened, causes a problem such as a short by foreign matter and a short during bonding of the driving IC due to the expansion of the conductive region.

In the present invention, by providing a COG mounting structure liquid crystal display device having a pad structure that opens only the contact portion of the autobrobe needle for defect inspection, it is possible to prevent the short and the like when bonding the driving IC.

COG structure liquid crystal display, gate pad, date pad, wiring number, intaglio

Description

Pad structure of chip on glass package liquid crystal display device}             

1 is a plan view showing a schematic structure of an array substrate for a COG mounting structure liquid crystal display device;

FIG. 2 is a plan view of a data pad portion of a non-display area in which a driving IC on an array substrate of a COG mounted structure liquid crystal display device is in contact. FIG.

3 is a plan view of a data pad portion of an array substrate of a conventional COG mounting structure liquid crystal display device.

4 is a plan view of a data pad portion of an array substrate of a COG mounting structure liquid crystal display device according to a first embodiment of the present invention;

5A to 5C are cross-sectional views taken along the lines A-A, B-B and C-C of FIG. 4.

6 is a plan view of a gate pad portion of an array substrate of a COG mounting structure liquid crystal display device according to a second embodiment of the present invention;

7A to 7C are cross-sectional views taken along AA, BB, and CC of FIG. 6.

<Description of Major Symbols in Drawing>                 

115: array substrate 125: data wiring

150: data pad hole 155: data dummy pad hole

BA: Data pad hole forming part DPA: Data dummy pad part

PA: Pad

The present invention relates to a liquid crystal display device, and more particularly, to a gate pad and a data pad pattern formation of a COG mounted structure liquid crystal display device.

Recently, with the rapid development of the information society, there is a need for a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption, among which a liquid crystal display has a resolution, It is excellent in color display and image quality, and is actively applied to notebooks and desktop monitors.

In general, a liquid crystal display device arranges two substrates on which electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injects a liquid crystal material between the two substrates, and applies a voltage to the two electrodes to generate an electric field. By moving the liquid crystal molecules, the image is expressed by the transmittance of light that varies accordingly.

The liquid crystal display device includes a liquid crystal panel in which liquid crystal is injected between two substrates, a backlight disposed under the liquid crystal panel and used as a light source, and a driving unit for driving the liquid crystal panel, which is positioned outside the liquid crystal panel.

Here, the driving unit includes a drive integrated circuit (IC) for applying a signal to the wiring of the liquid crystal panel, and according to a method of packaging the driving IC on the liquid crystal panel, chip on glass (COG) , Tape carrier package (TCP), chip on film (COF), and the like.

The COG method is a method of directly attaching a driving IC to an array substrate of a liquid crystal display device to directly connect an output electrode of the driving IC to a wiring pad on the array substrate. The COG method is simple in structure and simple in manufacturing cost. There is an advantage.

An array substrate structure of a liquid crystal display device formed by such a COG method is briefly shown in FIG. 1.

As shown, the array substrate 10 of the liquid crystal display device is divided into a display area 12 inside the dotted line on which an image is displayed and a non-display area 15 outside the dotted line.

First, a plurality of gate wirings 17 and data wirings 25 are formed in the display area 12. The gate wirings 17 and the data wirings 25 cross each other to define the pixel region P. As shown in FIG. Although not shown, a thin film transistor is positioned at the intersection of the gate wiring 17 and the data wiring 25, and the thin film transistor displays an image by switching a signal to the pixel electrode in the pixel region.

Next, gate and data link lines 30 and 33 connected to the gate line 17 and the data line 25 are formed in the non-display area 15, and the gate and data link lines 30 and 33 are formed. One end is connected to the gate pad 40 and the data pad 45, respectively, and the gate pad 40 and the data pad 45 are each provided with a gate driver IC 50 mounted on the array substrate 10. It is connected to the data driver IC 60, respectively. The gate driver IC 50 and the data driver IC 60 are connected to an external printed circuit board (PCB) (not shown), respectively, through FPCs 70 and 72. have. In the printed circuit board (PCB), a plurality of elements such as integrated circuits are formed on the substrate 10 to generate various control signals and data signals for driving the liquid crystal display. In this case, the printed circuit board (PCB) may be formed of a gate portion and a data portion, respectively, which are connected to each other by the FPCs 70 and 72 so that the gate signal and the data signal are organically connected to supply a signal.

FIG. 2 is an enlarged view of a portion of a data pad of a non-display area in which a driving IC on an array substrate of a COG mounted structure liquid crystal display device is in contact. At this time, the bumps in the driving IC are also shown.

The dotted line indicates the location where the drive IC is mounted. As shown in the drawing, the portion where the driving IC 60 is mounted may include an out lead bonding portion (OLB) in which the bump IC 65 of the driving IC 60 and the array substrate 15 contact each other, and an external printed circuit. It consists of an inner lead bonding (ILB) contacting the FPC connected to the substrate PCB, a dummy bump 63 and an intermediate part pattern in the driving IC. In this case, a portion in contact with the driving IC bump 65 may be a data pad portion PA connected to the data line 25, and the data pad 45 may be extended to be long in addition to the portion in contact with the driving IC bump 65. It is formed. Before attaching the driving IC, defect inspection using an auto probe is performed after completion of the liquid crystal panel or during manufacturing. A needle for inputting a signal included in the auto probe is performed. It is because it includes the area for contacting with a.

A data pad formed at one end of the data line will be described with reference to FIG. 3. The same applies to the gate pad portion.

As illustrated, the data pad 45 is connected to a data line 25 made of a metal material in the array substrate 15 to receive a signal by contacting a bump (not shown) of the driving IC. A protective layer (not shown) formed on the entire surface of the substrate 15 is etched on the data pad 45 to expose the data pad electrode (not shown) connected to the outside to the data line under the protective layer. A data pad electrode (not shown) connected to 25 is exposed.

Next, in the data pad part PA, a portion NCA in contact with the needle of the auto probe is formed in a zigzag form. Since the data pad spacing (pitch) is dense, it is difficult to contact the needle of the auto probe with the pad area of the same part, and thus the needle is provided in a zigzag form to form a zigzag shape on the data pad 45. Contact with. Therefore, while the area BA that is in contact with the bump of the actual driving IC is few, the area ANCA that is in contact with the needle of the auto probe for defect inspection occupies most of the area.

In the above-described pad structure, during the auto probe inspection of the liquid crystal panel, it is easy to connect the needle of the auto probe on the pad, but after mounting the drive IC after the defect inspection, In the process, the exposed pad area other than the part in contact with the bump of the driving IC becomes an unnecessary area. At this time, short between the pads and shorts due to foreign matters are generated in areas other than the areas in contact with the exposed bumps, resulting in defects.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to contact a needle of an auto probe in a pad on an array substrate of a liquid crystal display device having a COG structure in which a driving IC is formed on a substrate. It is an object of the present invention to provide an array substrate having a pad pattern capable of preventing short defects caused by short or foreign matter of the opened pad in a later step of mounting a driving IC or the like by opening only the bay.

In order to achieve the above object, an array substrate for a COG mounting structure liquid crystal display device according to the present invention includes a substrate; A plurality of gate wires formed on the substrate in a horizontal direction; A plurality of data lines crossing the plurality of gate lines and formed in a vertical direction; A thin film transistor formed at an intersection point of the gate line and the data line; A protective layer covering the gate wiring, the data wiring and the thin film transistor and formed on an entire surface of the substrate; A gate pad formed at one end of each gate wiring line and having a gate pad hole connected to a bump of a driving IC and having a gate dummy pad hole spaced apart from the gate pad hole; A data pad formed at one end of each data line and having one data pad hole connected to a bump of a driving IC and spaced apart from the one data pad hole; A driving IC formed in contact with the gate pad through the gate pad hole and in contact with the data pad through the data pad hole, wherein the gate and data pad holes are formed at the same position on each gate and data pad. The gate dummy pad hole and the data dummy pad hole may be formed at different positions from the gate and data dummy pad hole provided in the gate and the data pad adjacent thereto.

In this case, the gate dummy pad hole on the gate pad is formed at one position on each gate pad so as to have three zigzag structures by sequentially repeating the first position, the second position, and the third position, and the gate dummy pad. The first position of the hole is the gate pad end position furthest from the gate pad hole in contact with the bump of the driving IC, the third position is the position closest to the gate pad hole, and the second position is the position of the first and third positions. It is characterized by an intermediate position.

In addition, the data dummy pad hole on the data pad is formed at one position on each data pad so as to have a zigzag structure of three rows by sequentially repeating the fourth position, the fifth position, and the sixth position. The fourth position of the hole is the data pad end position furthest from the data pad hole in contact with the bump of the driving IC, the sixth position is the position closest to the data pad hole, and the fifth position is the fourth and sixth positions of the It is characterized by an intermediate position.

In addition, the gate dummy pad holes on the gate pads are formed at one position on each gate pad so as to have a zigzag structure of two rows by sequentially repeating the seventh position and the eighth position, and the seventh position of the gate dummy pad hole. Is a gate pad end position furthest from the gate pad hole in contact with the bump of the driving IC, and the eighth position is a position close to the gate pad hole.                     

In addition, the data dummy pad hole on the data pad is formed at one position on each data pad so as to have a zigzag structure of two rows by sequentially repeating the ninth position and the tenth position, and the ninth position of the data dummy pad hole. Is the end position of the data pad farthest from the data pad hole in contact with the bump of the driving IC, and the tenth position is a position close to the data pad hole.

In addition, the gate pad has a protective layer formed at a portion except the gate pad hole and the gate dummy pad hole, and the data pad has a protective layer formed at the portion except the data pad hole and the data dummy pad hole. And a gate dummy pad electrode contacting the gate pads through the gate dummy pad holes, and a data dummy pad electrode contacting the data pads through the data dummy pad holes. It is characteristic.

Hereinafter, a pad pattern structure in a liquid crystal display device having a COG structure according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is an enlarged view of a data pad part of the COG mounting structure liquid crystal display device according to the first embodiment of the present invention.

As illustrated, a plurality of data pads 145 connected to the data lines 125 are spaced apart at regular intervals in a vertical direction on the array substrate 115 for the COG mounting structure liquid crystal display device. A data pad hole 150 for contacting the driving IC is formed in a portion of the data pad 145 of the portion connected to the 125. In addition, one data dummy pad hole 155 on one data pad 145 is spaced apart from the data pad hole 150 on one data pad 145 in a first position, a second position, and a third position. It is formed by repeating sequentially. In this case, the first position where the data dummy pad hole 155 is formed is the furthest position from the data pad hole 150, and the third position is the closest position spaced apart from the data pad hole 150 by a predetermined distance. The second position is also a position between the first position and the third position. The data dummy pad hole 150 is in contact with a needle of an auto probe for defect inspection of a liquid crystal panel formed by bonding a color filter substrate to the substrate through a liquid crystal layer therebetween. It is formed to input a signal.

The dummy pad area DPA in the data pad 145 other than the data pad area BA in contact with the driving IC is not necessary in a subsequent process of forming the driving IC and the like, and is actually an element for driving the liquid crystal panel. However, it is necessary to perform a defect inspection of the liquid crystal panel. At this time, in the array substrate of the conventional COG-mounted liquid crystal display device, all of the protective layers are removed on the dummy data pad portion, and the data pad electrode connected to the data wiring underneath is opened to prevent wiring defects between the pads due to foreign matters in a later process. However, in the present invention, only the gate dummy pad hole 155 is opened, and the remaining dummy data pad region is not removed from the protective layer, thereby preventing a short pad-to-pad defect to some extent.

Next, the lower structure will be described with reference to 5a to 5c which are cross-sectional views cut along A-A, B-B and C-C of FIG.

As shown, the gate insulating film 103 of the inorganic insulating film is formed on the substrate 115. A plurality of data pad electrodes 120 connected to a data line (not shown) are formed on the gate insulating layer 103 at predetermined intervals. A protective layer 127 of an inorganic insulating layer or an organic insulating layer is formed on the data pad electrodes 120a to 120e. In FIG. 5A, the protective layers 127 on the first and fourth data pad electrodes 120a and 120d of the plurality of data pad electrodes 120a to 120e are removed to form data dummy pad holes 155a and 155d. The data dummy pad holes 155a and 155d are not formed on the second, third and fifth data pad electrodes 120b, 120c and 120e. In this case, the second and fifth data dummy pad holes (not shown) are formed in the second position (second position in FIG. 4), and the third data dummy pad holes (not shown) are in the third position (third position in FIG. 4). Are not shown on the drawing. Indium tin- which is a transparent conductive material contacting the data pad electrodes 120a and 120d through the data dummy pad holes 155a and 155d over the passivation layer 127 including the data dummy pad holes 155a and 155d. A gate pad electrode protection pattern 130 made of oxide (ITO) or indium-zinc-oxide (IZO) is formed. Since it is a conductive material, it contacts the lower data electrodes 120a and 120d and serves as a data pad electrode itself. Since the ITO and IZO are corrosion resistant materials, the ITO and IZO prevent corrosion of the data pad electrodes 120a and 120d.

Next, FIG. 5B is a cross-sectional view of a data dummy pad region in which data dummy pad holes are not formed. As illustrated, a gate insulating layer 103 is formed on the substrate 115, and a plurality of data pad electrodes 120 are formed on the gate insulating layer 103. The protective layer 127 is formed thereon. Therefore, since the data pad electrode 120 is covered with the protective layer 127, a short due to a foreign material between the data pad electrodes 120 does not occur in the region.                     

Next, FIG. 5C is a cross-sectional view of a portion in which a data pad hole in contact with a bump of a driving IC is formed.

As illustrated, a plurality of data pad electrodes 120 are formed on the substrate 115 over the gate insulating layer 103 at predetermined intervals, and the data pads exposing the respective data pad electrodes 120 thereon. The protective layer 127 including the hole 150 is formed. In addition, the data pad electrode protection patterns 130 made of a transparent conductive material contacting the data pad electrodes 120 are formed on the data pad contact holes 150 at predetermined intervals. The data electrode protection pattern 130 prevents corrosion of the data pad electrode 120.

Since the gate pad is formed in the same manner as the data pad formation described above, the description thereof will be omitted. In this case, in the gate pad cross-sectional structure, the gate pad electrode is formed on the substrate, and the gate pad electrode is formed in the same manner as the data pad except that a gate insulating layer and a protective layer are formed on the gate pad electrode.

FIG. 6 shows a part of a gate pad portion of an array substrate for a COG mounting structure liquid crystal display device according to a second embodiment of the present invention.

Although only the gate pad portion is shown in the drawing, only the gate pad portion will be described since the data pad portion has the same planar structure.

As shown in the drawing, a plurality of gate pads 245 connected to the gate wiring 225 are formed on the array substrate 215 for the COG mounting structure liquid crystal display device in a horizontal direction and spaced apart from each other. A gate pad hole 250 for contacting the driving IC is formed at a position of the gate pad 245 connected to the 225. In addition, one gate dummy pad hole 255 is sequentially spaced from the gate pad hole 250 on one gate pad 225 in the seventh and eighth positions on each pad 245. Formed. In this case, a seventh position where the gate dummy pad hole 255 is formed is a position far from the gate pad hole 250, and the eighth position is a close position spaced apart from the gate pad hole 250 by a predetermined distance. The gate dummy pad hole 255 is a needle of an auto probe for defect inspection of a liquid crystal panel formed by bonding a color filter substrate to the substrate 215 through a liquid crystal layer therebetween. It is formed in order to input a signal in contact with. Although not shown in the figure, a protective layer is formed on the pad region except for the gate pad hole 250 and the gate dummy pad hole 255 on the gate pad 245.

The cross-sectional structure of the gate pad will be described with reference to FIGS. 7A to 7C.

7A to 7C are cross-sectional views cut along the lines D-D, E-E, and F-F of FIG. 6, respectively.

As shown in FIG. 7A, a plurality of gate pad electrodes 220 are formed on the substrate 215 at regular intervals, and a gate insulating film 203 is formed on the entire surface thereof. Next, a passivation layer 227 is formed on the gate insulating layer 203. In this case, gate dummy pad holes 255 are formed on the first, third, and fifth gate pad electrodes 220a, 220c, and 220e to expose the gate pad electrodes 220a, 220c, and 220e. Gate pad electrode protection patterns 230 made of a transparent conductive material are formed through the pad holes 255, respectively. The gate pad electrode protection pattern 230 contacts the lower gate pad electrodes 220a, 220c, and 220e and forms the gate pad electrode itself.

Next, a description will be given with reference to 7b, which is a cross-sectional view of the gate dummy pad region in which the gate dummy pad hole is not formed.

As illustrated, a plurality of gate pad electrodes 220 are formed on the substrate 215 at regular intervals, and a gate insulating film 203 and a protective layer 227 are formed thereon. Since the region does not come into contact with the needle of the auto probe, the gate pad electrode 220 is not exposed and is covered by the protective layer 227.

Next, referring to FIG. 7C, which is a cross-sectional view of the gate pad hole forming portion, a plurality of gate pad electrodes 220 are formed on the substrate 215 at a predetermined interval, and the gate insulating film 203 is protected thereon. Layer 227 is formed. In addition, a gate pad hole 250 in which the gate insulating layer 203 and the protective layer 227 are removed is formed on the plurality of gate pad electrodes 220 spaced apart from each other, and each gate pad hole 250 is formed. The gate pad electrode protection patterns 230 of the transparent conductive material contacting the gate pad electrodes 220 are formed to be spaced apart from each other.

In the data pad section, the cross-sectional structure is as shown in the first embodiment, and the planar structure is the same as that of the gate pad section in FIG.

 The present invention is not limited to the above embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

In the present invention, a liquid crystal display (LCD) device having a COG structure for forming a driving IC on a substrate, wherein the gate pad and data pad of the array substrate protect the entire dummy pad region except for the gate and data pad hole forming portions in contact with the bump of the driving IC. Removes the protective layer on the part of the auto probe that does not remove the layer, and forms a dummy pad hole to prevent the short circuit between the gate pad and the data pad electrode due to foreign matters. can do.

Therefore, since the pad area to be conducted in the pad is reduced, a stable post process can be performed to prevent short and shortness defects.

In addition, since the exposed pad area is reduced, the reliability due to high temperature and high humidity of the pad may be improved to some extent.

Claims (12)

A substrate; A plurality of gate wires formed on the substrate in a horizontal direction; A plurality of data lines crossing the plurality of gate lines and formed in a vertical direction; A thin film transistor formed at an intersection point of the gate line and the data line; A protective layer covering the gate wiring, the data wiring and the thin film transistor and formed on an entire surface of the substrate; A gate pad formed at one end of each gate wiring line and having a gate pad hole connected to a bump of a driving IC and having a gate dummy pad hole spaced apart from the gate pad hole; A data pad formed at one end of each data line and having one data pad hole connected to a bump of a driving IC and spaced apart from the one data pad hole; A driving IC in contact with the gate pad through the gate pad hole and in contact with the data pad through the data pad hole The gate and the data pad hole are formed at the same position on each gate and the data pad, and the gate dummy pad hole and the data dummy pad hole are respectively disposed in the gate and the data pad adjacent to the gate and data pad hole. An array substrate for a COG mounting structure liquid crystal display device, characterized in that formed in a different position from the pad hole. The method of claim 1, The gate dummy pad hole on the gate pad is formed in one position on each gate pad so as to have three zigzag structures by sequentially repeating the first position, the second position, and the third position. Array substrate. The method of claim 2, The first position of the gate dummy pad hole is a gate pad end position furthest from the gate pad hole in contact with the bump of the driving IC, the third position is a position closest to the gate pad hole, and the second position is the first and second positions. An array substrate for a COG mounting structure liquid crystal display device, which is an intermediate position of the third position. The method of claim 1, The data dummy pad hole on the data pad is formed at one position on each data pad so as to have three zigzag structures by sequentially repeating the fourth position, the fifth position, and the sixth position. Array substrate. The method of claim 4, wherein The fourth position of the data dummy pad hole is a data pad end position furthest from the data pad hole in contact with the bump of the driving IC, the sixth position is the position closest to the data pad hole, and the fifth position is the fourth and An array substrate for a COG mounting structure liquid crystal display device, which is an intermediate position of a sixth position. The method of claim 1, And a gate dummy pad hole on the gate pad is formed at one position on each gate pad so as to have two rows of zigzag structures by sequentially repeating the seventh and eighth positions. The method of claim 6, And a seventh position of the gate dummy pad hole is a gate pad end position furthest from the gate pad hole in contact with the bump of the driving IC, and the eighth position is a position close to the gate pad hole. The method of claim 1, And a data dummy pad hole on the data pad is formed at one position on each data pad so as to have a zigzag structure of two rows by sequentially repeating the ninth position and the tenth position. The method of claim 8, And a ninth position of the data dummy pad hole is a data pad end position furthest from the data pad hole in contact with the bump of the driving IC, and the tenth position is a position close to the data pad hole. The method of claim 1, The gate pad is a COG mounting structure liquid crystal display device substrate having a protective layer formed in the portion except the gate pad hole and the gate dummy pad hole. The method of claim 1, The data pad is a COG mounting structure liquid crystal display device array substrate having a protective layer formed in the portion except the data pad hole and the data dummy pad hole. The method of claim 1, Gate dummy pad electrodes are formed on the passivation layer to contact the gate pads through the gate dummy pad holes, and data dummy pad electrodes are formed to contact the data pads through the data dummy pad holes. Array substrate for COG mounted structure liquid crystal display.

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