KR100936601B1 - Multi-processor system - Google Patents

Abstract

A hardware operating system based and / or shared cache based multiprocessor system is disclosed. A multiprocessor system comprising a plurality of processor cores, the plurality of processor cores coupled to the plurality of processor cores for interrupt handling, task synchronization, task scheduling, context switching and task resume operations for operating system service requests from the plurality of processor cores. Hardware operating system; A shared instruction cache in which instructions supporting the plurality of processor cores are stored in advance; And a shared data cache in which data supporting the plurality of processor cores is stored in advance. Compared to the conventional method, it has less performance delay and overhead when operating a multi-processor core, uses a lighter processor, and is effective in area, and thus can be optimally applied to a mobile multimedia system.

Processor, Multiprocessor, Cache, Hardware, Multi Threading

Description

Multi-processor system

The present invention relates to a multi-processor system, and more particularly, to a hardware operating system-based and / or shared cache-based multi-processor system.

Recently, as well as digital information devices such as mobile phones, PDAs, electronic dictionaries, white appliances such as TVs, refrigerators, artificial intelligence and informatization have been rapidly made. Accordingly, the proportion of software in the electronics industry is rapidly increasing, and accordingly, the demand for a processor for executing software is also increasing. The processor embedded in a digital information device is called an embedded processor, and the software running on the embedded processor is called an embedded software.

In general, because digital information devices respond quickly to various external stimuli and execute real-time tasks simultaneously, embedded software is implemented as a multi-threaded program consisting of multiple threads. .

In general, the process by which the embedded processor executes a multi-threaded program includes interrupt handling, job / task synchronization, task scheduling, context switching, and task resume. It consists of five detailed steps. Each detailed step is described in more detail as follows.

(1) When an external stimulus (interrupt) such as a timer is applied to the processor in the interrupt handling step, the processor finds out which hardware device caused the external stimulus and calls the corresponding interrupt handler routine. (2) Task Synchronization is a waiting queue where the interrupt handler routine wakes up an application task that has been suspended by changing the value of synchronization related variables such as semaphores and barriers after performing appropriate tasks according to the request of the hardware device. ) To insert. (3) Job scheduling means selecting the highest priority job among the jobs stored in the waiting queue. (4) Context exchange is to evacuate various information about the task being executed in the embedded processor to the designated memory area, and to read the information about the task selected in the task scheduling step from the specific memory area and to set the internal registers of the embedded processor. Say. (5) Resuming a task means starting the execution of a task set in a processor through the above process.

In a typical system, the above processes are performed in software. The software in charge of the above processes is called an operating system. In order to perform the above processes in software, the computing power of the processor must be consumed. The amount of computational resources to run the operating system is called multithreading overhead. The computational resources required to perform the five steps described above depend on the algorithm and complexity of the operating system, but they range from hundreds to thousands of cycles. This amount of overhead isn't much of a problem for software where the transition between threads is in the tens of thousands or more cycles. For example, on Windows or Linux, which are popular on personal PCs, the multithreading overhead is no more than 5% of the total computational resources.

Meanwhile, recently developed mobile multimedia systems adopt a multiprocessor system structure in which several processors collaborate to execute an application. It has a built-in hardware accelerator for accelerating voice and 3D graphics. In these applications, thread switching is very frequent to maximize performance. For example, a video codec with hardware accelerators and software collaboratively causes thread switching every 1,000 to 5,000 cycles, which adds a significant amount of multithreading overhead. For example, if the computational resources required to perform the five steps described above are about 1,000 cycles, and the thread transition occurs every 3,000 cycles, then the multithreading overhead is about 25%. This assumes that a system has four embedded processors, so one of the embedded processors is wasted for multithreading overhead. It's impractical to take this much multithreading overhead, so you usually write embedded software to make thread switching rare. However, in this case, there is a limit in performance because it cannot respond to the request of an external stimulus or a hardware accelerator as agile.

The root cause of the multithreading overhead is that the interrupt handling, task synchronization, task scheduling, context exchange, and task resumption processes described above are performed in software. If the five operations for multithreading are performed in hardware, the multithreading overhead can be minimized. In fact, improving performance by implementing parts of software tasks as hardware accelerators is a common strategy, and many processors have been announced to reduce multithreading overhead. However, the processor architectures published so far are solutions that support only one processor core or hardware implementation of some of the above five steps. The advantages and disadvantages of the existing methods are as follows.

The set of information that can define a state at any moment in a thread is called the thread's context. A typical RISC (Reduced Instruction Set Computer) processor has a register set that can store only one context internally. In contrast, processors such as Microprocessors without Interlocked Pipeline Stages (MIPS) 32K and Scalable Processor Architecture (SPARC) V9 have an extra set of registers to store multiple contexts, allowing different threads to run on different cycles. .

The multiple context multithreading processor can reduce the task scheduling overhead and the context exchange overhead because the context exchange and the thread selection is made in hardware. In general, however, multi-context multi-threading processors provide four or more context sets, so if the total number of tasks is greater than the number of context sets supported by hardware, the software operating system requires intervention. Will increase. In addition, commercially available multi-context multithreading processors do not take into account interrupt handling, task synchronization, etc., so multithreading overhead is still significant in systems with frequent requests from external stimuli and hardware accelerators. On the other hand, a multi-context multi-threading processor has a plurality of contexts but only one datapath to perform an operation, and thus the performance effect can not be expected other than reducing the multi-threading overhead. Moreover, for lightweight processors, the datapath occupies about 20K to 30K gates, whereas the register set for one context occupies about 10K gates and the area for four contexts is about 40K gates. This is inefficient in terms of area because the register set, which is a resource that cannot be shared, is much larger than the data path, which is a resource to do. For example, an area of a multi-context multithreading processor supporting four contexts is about 60K gates, whereas an RISC processor supporting one context is only about 30K gates. That is, when using the same area, RISC processor that can use two processors in parallel is rather advantageous in terms of performance.

Simultaneous Multithreading (hereinafter referred to as SMT) processor is a processor of a structure that supports a plurality of data paths while supporting a plurality of contexts. In addition to reducing multi-threading overhead, the SMT processor can significantly improve performance by executing multiple threads of instructions simultaneously or simultaneously executing instructions of multiple threads. SMT is a hyper-threading technology applied to the Intel Pentium 4 processor that is widely known to the public. The disadvantage of SMT processors is that they are too large. In general, SMT processors have a large instruction queue internally and have complex circuits such as register renaming and a reservation table. In the case of an SMT processor that can execute three instructions simultaneously, the area of the data path is about 70K gates, whereas the area of additional circuitry required to operate it exceeds 120K gates. On the other hand, like the multi-context multithreading processor, the SMT processor also has no support for interrupt handling and task synchronization, and since the number of tasks in the system exceeds the number of hardware contexts, intervention of the software operating system is required. There is a limit to reducing the head.

There are two ways to effectively support a large number of tasks: hardware contextual exchange and task scheduling hardware.

First, let's look at context exchange. Intel's Pentium processor is the most representative processor that performs the context exchange. In the Pentium processor, each thread has an allocated memory area called Task State Segment (TSS), where the context information of this thread is stored in this TSS, and a special call instruction that takes an ID indicating a specific TSS. You can exchange contexts with In the event of an interrupt, the processor register values are automatically evacuated to the TSS of the currently running thread, and automatically loads and executes the context of the handler routine corresponding to the hardware that caused the interrupt. The Pentium processor reduces the multithreading overhead by hardware handling context exchange and interrupt handling, but has the limitation that task scheduling and task synchronization still need to be done in software. Moreover, although a thread to be resumed has been determined through task scheduling, when the context of the thread is evacuated to the external memory, the processor stops executing while reading the context from the external memory. For example, if the context consists of 32 words, the processor is operating at 800 MHz, and the external memory is operating at 200 MHz, the processor stops performing for at least 128 (processor) cycles.

Since the task scheduling method must be adaptively selected according to the implementation of the operating system or the dynamic characteristics of the task, it may be necessary to process the software in a system that performs various application software such as a personal computer. In a built-in system such as a PDA or a PDA, even if a specific scheduling scheme is implemented in hardware, there is no big problem. However, hardware accelerators that perform some of the announced task scheduling schemes in hardware are not implemented as a result of reducing multithreading overhead because the core functions of the operating system are still implemented in software and only a few functions are performed through hardware accelerators. For this reason, a lot of time is spent for communicating with the processor and for context exchange, thereby halving the effect of performing the scheduling in hardware. Moreover, some are not practical because they take up too much area.

As the complexity of software continues to grow in response to recent market demands, a single embedded processor can no longer meet its performance. Because of this, more and more processors are embedded in one system. When running software on multiple processors, independent software may be executed for each processor, but rather, the software may be divided into a plurality of tasks, and each thread may be distributed over multiple processors and executed in parallel. Typically implemented as a threaded program.

When a multithreaded program is executed on a multiprocessor system, a task migration overhead occurs in addition to the multithreading overhead described above. Pre-operation overhead is an additional time delay incurred when a thread that was running on one processor is suspended and then resumed on another processor. This will be described in detail as follows.

High performance processors have an instruction cache and a data cache to prevent performance degradation due to communication latency in external memory. The first time you read an instruction or data, you have to wait a long time to get information from the external memory, but if the instruction or data is read again later, the cache can be supplied directly to improve processor performance. . When storing data, it is possible to improve the performance of the processor by storing it only in the data cache and later reflecting it to external memory. If you want to perform a task that was performed on one processor and was interrupted by another processor, the changed data may be stored in the cache of the previous processor, but not yet reflected in external memory, in which case the correct data on the new processor. Cannot be referenced. Therefore, when transferring work, the data cache flush should be performed to force the changed data to the external memory only in the data cache of the existing processor for the coherency of data. Long delays are inevitable because no other work can be done. Moreover, the data cache cannot know what thread changed the data, so it is inevitable that all the changed data must be reflected in the external memory, so the time delay is very serious. On the other hand, even for the instruction cache, even though the instruction already exists in the cache of the previous processor, the instruction must be read back from the external memory for a new processor, and a time delay occurs. Work transfer overhead refers to the additional time delays that occur when transferring work as above.

In some systems, L1 caches, which are small in memory but capable of operating at high speed, are placed on each processor. The L2 cache, a cache that uses a large amount of cache memory but is located somewhat apart from the processor between the L1 cache and external memory, employs a hierarchical structure shared by multiple processors, reducing pre-operation overhead and reducing cache memory. Its area efficiency is improving. However, there is a problem that L1 caches are still distributed for each processor and thus the overhead before operation cannot be completely eliminated.

On the other hand, if each processor has its own instruction cache and data cache, the cache memories are finely divided and distributed. In a system with dynamically allocating tasks for a particular processor, it seems reasonable to allocate an equal amount of cache memory for all processors, but it is inefficient given the different cache memory requirements for each task. do. For example, assume that tasks T _A and T _B are running that require 2 KB and 6 KB of memory on processor P _A and processor P _B with 4 KB of data cache, respectively. The memory required for both operations is 8KB in total, and the data cache memory is 8KB in total, but P _A utilizes only half of the allocated cache memory, and P _B frequently causes cache misses. , A time delay occurs. This occurs because cache memory is divided and distributed, and this effect is called a cache memory fragmentation effect.

Existing methods that give each processor its own instruction and data caches are difficult to expect high performance due to pre-operation overhead and cache memory fragmentation. An alternative is to share one instruction cache and one data cache among multiple processors, but in this case, a unique cache structure is needed to support multiple processors simultaneously.

Accordingly, the present invention provides a multi-processor system capable of minimizing the overhead associated with the process by integrating the hardware through a hardware operating system that implements interrupt handling, task synchronization, task scheduling, context exchange, and the like. to provide.

In addition, the present invention provides a multi-processor system that can use a lighter processor because the operating system is implemented in hardware, the processor does not need to provide a function for supporting a software operating system.

In addition, the present invention eliminates overhead and cache memory fragmentation before operation by introducing a shared instruction cache and a shared data cache, in which a plurality of processor cores can share one instruction cache and a data cache as an L1 cache. The present invention provides a multiprocessor system having an effect of significantly improving the performance of a processor system.

In addition, the present invention allows a plurality of processor cores to share a more efficient large area on-chip SRAM through a shared cache, and to achieve the same performance as compared to the case where the proprietary caches are distributed to each processor core Less cache memory is available, providing an area-efficient multiprocessor system.

In addition, the present invention provides a multi-processor system that can be optimally applied to a mobile multimedia system using a lightweight processor and efficient in area.

According to one aspect of the invention, a plurality of processor cores; And a hardware operating system connected to the plurality of processor cores through an operating system bus, the hardware operating system performing hardware for interrupt handling, task synchronization, task scheduling, context exchanging, and task resume operations for operating system service requests from the plurality of processor cores. A multiprocessor system is provided that includes.

The hardware operating system includes a thread control memory for storing work information; A thread manager that selects the highest priority job among the jobs registered in the waiting queue and controls semaphore access; A context memory in which contexts of created threads are stored; A context buffer in which a context of a thread to resume execution or a context of a thread in which execution is stopped is stored; A context manager that reads a context for a thread selected by the thread manager from the context memory and stores the context in the context buffer or stops execution and stores the context of a thread stored in the context buffer in the context memory; And a main controller coupled to the operating system bus and controlling the thread manager and the context manager according to the operating system service request from the processor core.

The thread control memory may include a ready queue having a first value when the task is in a standby state and a second value when the task is suspended, and a priority of the task. It may include information, semaphore access control information including semaphore status flags and semaphore values for each semaphore, and a wait queue in which jobs waiting in the semaphore are registered.

The wait queue may be a bit vector that maps one bit.

The thread control memory may include a thread descriptor and a semaphore descriptor composed of four fields.

The information for scheduling the job is stored in two fields indicating the upper and lower bits of the priority among the fields of the thread descriptor, and the information for the semaphore access control uses the semaphore descriptor among the fields of the semaphore descriptor. A flag indicating whether or not, a flag indicating the type of the semaphore, and the semaphore value may be stored in three fields.

The suspend queue may be implemented using the remaining one field of the semaphore descriptor and the remaining two fields of the thread descriptor.

If the remaining one field of the semaphore descriptor is negative, it indicates that at least one job is registered in the suspension queue, and the ID of the first job is stored in the first field of the remaining two fields of the thread descriptor. When the second field is the first value, it indicates that another job is additionally registered in the suspension queue, and when the ID of a subsequent job is stored in the first field and the second field is the second value, the job is the suspension queue. It can indicate that it is the last job registered in.

The thread control memory may be one single-port SRAM.

According to another aspect of the present invention, in a multi-processor system including a plurality of processor cores, connected to the plurality of processor cores interrupt handling, task synchronization, task scheduling, for operating system service requests from the plurality of processor cores, An operating system for performing context exchange and resume operation operations; A shared instruction cache in which instructions supporting the plurality of processor cores are stored in advance; And a shared data cache in which data supporting the plurality of processor cores is stored in advance.

The shared instruction cache may include an internal communication network and a plurality of on-chip memories, wherein words constituting one instruction block are distributed and stored in different on-chip memories, and the interleaved instructions may read the distributed stored words simultaneously. Cache memory (Interleaved Instruction Cache Memory); A tag memory for storing a part of an instruction block stored in the interleaved instruction cache memory as a tag; Comparing a part of the command according to the operating system service request with a tag stored in the tag memory, and performing tag matching to determine whether the requested command exists in the interleaved command cache memory, and performing the tag matching result. A cache controller configured to output the instruction block request signal when a specified instruction does not exist in the interleaved instruction cache memory; And a block-fill controller configured to read an instruction block from an external memory through a system bus according to the instruction block request signal and store the instruction block in the interleaved instruction cache memory.

The interleaved instruction cache memory may have a different order in which the interleaved instruction cache memory is distributed and stored in the plurality of on-chip memories with respect to different paths.

The shared instruction cache performs a tag matching when first accessing an instruction block, and when a command belonging to the instruction block is sequentially read, a tag matching skipping scheme that skips the tag matching. It is available.

The shared instruction cache may perform the tag matching when the processor core requests an instruction having a sequential address when one of the plurality of processor cores performs a branch instruction, but the instruction is stored in another instruction block. .

The shared instruction cache may further include an instruction buffer that is allocated to each of the plurality of processor cores and reads and stores the instruction from the interleaved instruction cache before the allocated processor core requests the instruction.

The instruction buffer includes a branch status signal indicating whether the allocated processor core has performed a branch instruction and a pre-fetch pressure signal indicating the number of instructions stored in the instruction buffer. The cache controller transmits an on-chip memory selection signal to the plurality of on-chip memories through the internal communication network after determining a command to be read using the branch status signal and the pre-fetch pressure signals. And output the command to be inserted into the command buffer.

The shared data cache may be a history based hierarchical tag matching scheme.

The shared data cache includes an internal communication network and a plurality of on-chip memories, wherein words constituting one data block are distributed and stored in different on-chip memories, and interleaved data capable of simultaneously reading the distributed and stored words. Cache memory (Interleaved Data Cache Memory); A tag memory for storing a part of a data block stored in the interleaved data cache memory as a tag; The tag matching is performed to compare whether the requested data exists in the interleaved data cache memory by comparing a portion of data according to the operating system service request with a tag stored in the tag memory, and the requested data is determined by the tag matching result. A cache controller for outputting the data block request signal when not in an interleaved data cache memory; And a block-fill controller configured to read a data block from an external memory through a system bus according to the data block request signal and store the data block in the interleaved data cache memory.

The shared data cache may include a history buffer that stores tags of addresses of an on-chip memory that have been accessed within a predetermined time; And a history tester comparing the tag stored in the history buffer with a requested address to determine whether the requested data exists in the interleaved data cache memory.

The cache controller may read the tag from the tag memory and perform the tag matching when the determination is not completed by the history tester.

The history buffer may store the tag by distinguishing a stack memory access from a heap memory access.

According to another aspect of the invention, in a multi-processor system comprising a plurality of processor cores, connected to the plurality of processor cores interrupt handling, task synchronization, task scheduling for operating system service requests from the plurality of processor cores A hardware operating system for performing context exchange and resume operation operations in hardware; A shared instruction cache in which instructions supporting the plurality of processor cores are stored in advance; And a shared data cache in which data supporting the plurality of processor cores is stored in advance.

Other aspects, features, and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

The multiprocessor system according to the present invention is integrated with a hardware operating system that implements a process such as interrupt handling, task synchronization, task scheduling, context exchange, and the like, thereby minimizing the overhead associated with the process. .

In addition, since the operating system is implemented in hardware, the processor does not need to provide a function for supporting a software operating system, so that a lighter processor can be used.

In addition, the introduction of shared instruction caches and shared data caches, where multiple processor cores can share a single instruction cache and data cache, significantly reduces the performance of multiprocessor systems by eliminating pre-operation overhead and cache memory fragmentation. It has an improved effect.

In addition, shared caches allow more efficient, large area-on-chip SRAMs to be shared by multiple processor cores, with less cache memory for the same performance as compared to the case where proprietary caches are distributed across each processor core. It is also effective in terms of area since it can be used.

In addition, it uses a lightweight processor and is efficient in terms of area, so it can be optimally applied to a mobile multimedia system.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, a task performed in the processor core may be a thread or a process. Hereinafter, the task performed in the processor core will be described as a thread for the convenience of understanding and explanation of the present invention. Let's do it.

1 is a schematic diagram illustrating a structure of a multiprocessor system according to an exemplary embodiment of the present invention. Multi-processor system 100, a plurality of processor cores (120a, 120b, 120c, 120d, collectively referred to as 120), hardware operating system (110), shared instruction cache 130, shared data cache 140, coprocessor 10, SDRAM 20 are shown.

A typical processor core uses an interrupt scheme to be notified of service requests or event occurrences from external devices. Here, the interrupt method means that the processor core suspends the work currently being executed and forcibly branches to the interrupt handler routine when there is an external event. In addition to external events, services such as internal errors, software interrupts, debugger traps, and page faults can be handled in the same way, which is called exception handling. Interrupt handling based on the interrupt scheme requires the processor core to have a dedicated set of registers for the interrupt mode as well as the control logic to support it internally.

In one embodiment of the present invention, such interrupt handling is directly handled by the hardware operating system 110 rather than the processor core 120. Thus, since the processor core 120 does not need to have a set of logic and registers to support interrupts, it is possible to reduce the area of the processor core itself. The processor core 120 has a smaller area than the general processor core because the register for interrupt handling is removed.

For example, the ARM9 processor from the UK ARM has a data path area of about 15K gates, an area of about 10K gates for the basic context, and an additional register area of about 15K gates for system services. As such, it occupies an area of about 40K gates in total. However, according to the exemplary embodiment of the present invention, since the system service is performed by the hardware operating system 110, the processor core 120 does not need separate support, and thus, the lightweight processor core 120 having a 30K gate level is provided. Can be used. As shown in FIG. 1, when four processor cores 120 are integrated, about 40K gates can be reduced.

Here, the multiprocessor system 100 requires a separate area for the hardware operating system 110. However, this applies to the job scheduling method and the job synchronization method using the thread control memory to be described later, the area of the hardware operating system 110 required in the multi-processor system 100 does not exceed 40K gate. That is, since the area increase for the hardware operating system 110 and the area decrease of the processor core 120 obtained by utilizing the light weight operating system are offset, the performance may be improved by minimizing the multi-threading overhead without increasing the area. Multithreading overhead includes task scheduling overhead, context switching overhead, interrupt handling overhead, and task synchronization overhead.

The processor core 120 is connected to the hardware operating system 110 through an operating system bus. The processor core 120 transmits an operating system service request to the hardware operating system 110 through the operating system bus, that is, a request for creating and destroying a thread, creating a semaphore, changing a value, and destroying the semaphore. The processor core 120 may be connected to the coprocessor 10 through a coprocessor bus to exchange data. In addition, the processor core 120 is also connected to the hardware operating system 110 and the context bus (Context Bus). The hardware operating system 110 exchanges the context of suspended threads and newly resumed threads through the context bus.

In another embodiment of the present invention, the multiprocessor system 100 includes a shared instruction cache 130 and a shared data cache 140, and the shared instruction cache 130 and the shared data cache 140. Can access the SDRAM 20 via a shared memory bus.

The cache consists of a cache controller and cache memory. Cache memory may be implemented using on-chip SRAM cells. The larger the capacity of an SRAM cell, the higher the density. For example, in a 0.18um process, a 2KB SRAM cell occupies an area of about 10 um ² per bit, whereas an 8KB SRAM cell occupies an area of 6 um ² per bit. If each of the four processor cores has a 2KB cache, the cache memory occupies about 80,000 um ^2, but if one 8KB shared cache occupies only 48,000 um ² . That is, the area occupied by the cache memory is approximately half. In general, cache memory occupies 50 to 75% of the total system area, and the area reduction obtained by utilizing the shared cache is very large.

In FIG. 1, the context bus, the operating system bus, the coprocessor bus, and the shared memory bus are shown separately, but they can be implemented as physical buses having various structures. In one embodiment, it is also possible to integrate the shared memory bus and the coprocessor bus into one physical bus, and the context bus and operating system bus into a single physical bus. In another embodiment, the operating system bus and the coprocessor bus may be integrated into one physical bus, and the shared memory bus and the context bus may be implemented as separate physical buses.

The multi-processor system according to an embodiment of the present invention can reduce the multi-threading overhead through the hardware operating system 110 provided therein. This will be described later in detail with reference to FIGS. 2 to 5.

In addition, the multi-processor system according to another embodiment of the present invention can reduce the overhead before operation and reduce the total area through the shared instruction cache 130 and the shared data cache 140 provided therein. This will be described later in detail with reference to FIGS. 6 to 10.

In addition, a multiprocessor system according to another embodiment of the present invention includes a hardware operating system 110, a shared instruction cache 130 and a shared data cache 140 to reduce the multi-threading overhead and pre-work overhead Reduce the total area.

Hereinafter, a multiprocessor system that reduces multithreading overhead through the hardware operating system 110 according to an embodiment will be described.

2 is a detailed diagram illustrating a structure of a hardware operating system, and FIG. 3 is a detailed diagram illustrating a structure of a thread control memory.

The hardware operating system 110 includes a main controller 210, a thread manager 230, a context manager 250, a context buffer 260, a thread control memory 220, and a context memory 240.

Processor core 120 includes a datapath 126, a context controller 124, and a register file 122. The datapath 126 is directly connected to the main controller 210 of the hardware operating system 110 through an operating system bus. The context controller 124 is directly connected to the context manager 250 of the hardware operating system 110 through the context bus, and the context controller 124 and the context manager 250 are running or are stopped in the processor core 120. Send and receive the context of a completed task. The register file 122 temporarily stores the context of work performed in the processor core 120.

The hardware operating system 110 is responsible for a multi-threaded program execution process consisting of five sub-steps, interrupt handling, task synchronization, task scheduling, context exchange, and task resume. Each detailed step has been described in detail above, so a detailed description thereof will be omitted.

The main controller 210 is connected to the operating system bus to receive operating system service requests issued by the processor core 120, and thus control other components such as the internal thread manager 230 and the context manager 250.

The thread control memory 220 stores one of a thread's work information, a work status, a priority, a wait queue, a semaphore status, and a combination thereof.

The thread manager 230 selects the highest priority task among the tasks registered in the waiting queue and controls semaphore access.

The context memory 240 stores the context of the generated jobs.

The context buffer 260 temporarily stores a context of a job to resume execution, or temporarily stores a context of a job where execution is stopped. The context buffer 260 may be made of on chip memory.

The context manager 250 reads the context for the task selected by the thread manager 230 from the context memory 240 and stores the context in the context buffer 260, or conversely, the context buffer 260 corresponding to the task which has been stopped. ) Is stored in the context memory 240.

The context manager 250 reads the context of the job to be resumed from the context memory 240 and stores it in the context buffer 260. When a task performed by any one processor core 120 is interrupted or when a priority of a task prepared in the context buffer 260 is higher than a priority of the task, contexts are exchanged through the context bus. This process is done in hardware without software intervention, so you can switch jobs very quickly.

In order to perform the hardware, the hardware operating system 110 stores a memory for storing contexts of threads, a memory for storing information required for scheduling a task, a memory for storing information for controlling semaphore access, and a memory for implementing a hang queue. This requires memory to implement the wait queue.

First, since the memory for storing the context (corresponding to the context memory 240) is very large, it is impossible to implement all of them as on-chip memory. On the other hand, since the remaining memories are not very large, it is possible to implement on-chip memory. In the embodiment of the present invention, the remaining memories except the context memory 240 are implemented as follows.

First, the wait queue is implemented as a bit vector that maps one bit to each thread. For example, if a thread is in a waiting state, the bit corresponding to that thread may have a first value (for example, 1) and, if this thread is suspended, it may have a second value (for example, 0). have. When a wait queue is implemented as a bit vector, each thread may be represented by only one register (corresponding to an area of six NAND gates) for each thread. In a typical embedded system, the number of threads does not exceed 128, so the area of the wait queue does not exceed 1K gates.

Job scheduling requires knowing the priority of each thread. Here, the information for job scheduling is the priority of each thread. The priority value is read for each thread registered in the waiting queue (that is, the corresponding bit is set to 1), the priority is sequentially compared, and the thread having the highest priority value is selected. According to this scheduling method, if the number of threads registered in the waiting queue is k, scheduling requires k clock cycles. If there are few threads in the wait queue, job scheduling does not take long. In particular, in a hardware processor-based multiprocessor system, job scheduling is performed in parallel with the processor core 120 and thus does not deteriorate the performance of the system. On the other hand, if there are many threads in the waiting queue, job scheduling itself can take a long time. However, scheduling time is not a problem in terms of performance because the fact that there are many threads in the wait queue is very likely that other threads already waiting are prefetched in the context buffer 260. The advantage of this scheduling method is that it requires only one comparator to compare priorities when implemented in hardware, and it is advantageous in terms of area because the priority information of threads can be stored in sequential on-chip memory (SRAM).

In order to control semaphore access, each semaphore requires a semaphore state flag indicating the semaphore's state, a semaphore value, and a suspend queue that registers threads waiting on the semaphore. Here, information for semaphore access control is a semaphore state flag and a semaphore value.

Representative services for semaphores are semaphore wait and semaphore posts.

When a thread requests a semaphore wait for a semaphore, it works as follows: The hardware operating system 110 reads the semaphore value, decreases it by one if this value is positive and immediately resumes execution of the thread. If this value is zero or negative, it immediately suspends this thread, inserts it into the semaphore's suspend queue, and assigns another thread to the processor.

When a thread requests a semaphore post for any one semaphore, it works as follows: The hardware operating system 110 reads the semaphore value, and if this value is zero or positive, increases the semaphore value by the requested amount. If this value is negative, the required number of threads are withdrawn from the suspend queue, inserted into the wait queue, and distributed to various processor cores 120 through job scheduling.

Hardware operating system 110 according to an embodiment of the present invention is the process of hardware semaphore post, semaphore value update, withdraw thread from the suspend queue, insert the thread into the wait queue, job scheduling, context exchange collectively hardware fast Is performed.

Here, information for job scheduling, information for semaphore access control, and a suspension queue for each semaphore are implemented as a thread control memory 220. The thread control memory 220 may be implemented as one on-chip SRAM. Referring to FIG. 3, the structure of the thread control memory 220 is shown. Information for job scheduling stored in the thread control memory 220 is called a thread descriptor, and information for semaphore access control is called a semaphore descriptor.

The thread descriptor 222 consists of four fields: PRIO, WCNT, N, and NEXT. PRIO is the upper bit of the priority value and WCNT is the lower bit of the priority value. When the number of bits in WCNT is NWCNT, the priority value of a thread is ((PRIO << NWCNT) | WCNT). Among the information representing the priority, PRIO is a priority value assigned to a thread by software and is not changed by the thread manager 230, and the WCNT is changed by the thread manager 230 for fair scheduling. For example, if there are n threads with the highest priority value p and a PRIO value p, their WCNT values are updated as follows: The WCNT value of the thread selected by the thread manager 230 is set to 0, and the WCNT value of the remaining threads is increased by one. The N and NEXT fields are for implementing the suspension queue 226, which will be described later.

The semaphore descriptor 224 consists of four fields: E, B, VALUE, and NEXT. E is a flag that is set to a value of 1 if the semaphore descriptor is already in use and to a value of 0 otherwise. B is a flag set to a value of 1 when the semaphore is a binary semaphore and a value of 0 when a counting semaphore is used. VALUE is a field that stores semaphore values. The method of controlling semaphore access (semaphore wait, semaphore post, etc.) by using values stored in three fields of E, B, and VALUE will be omitted.

Suspend queue 226 is implemented using the NEXT field of semaphore descriptor 224 and the N, NEXT fields of thread descriptor 222. If the VALUE of the semaphore descriptor 224 is negative, it means that one or more threads are registered in the suspension queue, and the ID of the first thread is stored in the NEXT field of the semaphore descriptor 224. If the N field of the thread descriptor 222 is 1, it means that another thread is additionally registered in the suspension queue, and the ID of the subsequent thread is stored in the NEXT field of the thread descriptor 222. If the N field is 0, this means that this thread is the last thread registered in the suspend queue.

By expressing the thread descriptor 222 and the semaphore descriptor 224 as described above, information for job scheduling, information for semaphore access control, and a suspension queue can be implemented using only one single-port SRAM. This can greatly reduce the area.

One or more coprocessors 10 may be connected to the coprocessor bus to assist in the performance of the processor core 120. The coprocessor 10 delivers three signals to the hardware operating system 110: lock, release, and processor core ID. The processor core ID signal means the number of processor cores 120 that are currently accessing the coprocessor 10, and the lock signal means that the work requested for the coprocessor 10 has not been completed yet. The signal means that the requested operation has been completed. When the lock signal is applied, the hardware operating system 110 stops the work performed by the processor core 120 indicated by the processor core ID signal, and performs a context exchange with the work waiting in the context buffer 260. Subsequently, when a release signal is applied, the stopped task is prepared again in the context buffer 260, and the context exchange is performed for a processor core in which no current task is performed or a processor core having a lower priority than the task to be resumed. do. Through the above functions, the interrupt request from the coprocessor 10, the interruption of the operation, and the resumption of the operation may be performed in hardware to improve performance.

4 is a flowchart of a multi-threaded program execution process in a software operating system, and FIG. 5 is a flowchart of a multi-threaded program execution process in a hardware operating system according to an embodiment of the present invention.

Referring to FIG. 4, the multi-threaded program execution in the software operating system is divided into seven steps from S410 to S470.

During the execution of the application task (step S400) Once an interrupt occurs (step S410), the application task that was being performed is interrupted, and each application from step S420 to step S470 is sequentially performed, and the application task is resumed (step S480).

When an interrupt occurs (step S410), an interrupt handler is performed (step S420). Then, work synchronization is performed and inserted into a waiting queue (step S430). After performing job scheduling (step S440), the context of the current thread is evacuated to external memory (step S450) or the context of the thread to be resumed is read from the external memory (step S460). Steps S450 and S460 correspond to a context exchange process, and the software operating system consumes many clock cycles during this process.

Referring to FIG. 5, execution of a multi-threaded program in a hardware operating system is divided into seven steps from S510 to S570. Each step in the hardware operating system can be completed in a very short time compared to the step in the corresponding software operating system.

Steps S510 to S550 up to immediately before the context exchange among the steps in the hardware operating system are performed regardless of the processor core. After all the contexts of the thread selected and resumed by the thread manager are read out from the external memory and stored in the context buffer, the context exchange is started in step S560. From the perspective of the processor core, the multithreading overhead is extremely small, since the context of the thread that is currently running is also evacuated to the context buffer and later stored in external memory by the hardware operating system.

As described above, each processor core in a multiprocessor system based on a hardware operating system can dedicate more computational resources to an application, resulting in better performance.

Hereinafter, a multiprocessor system that reduces overhead before operation and reduces the total area through the shared instruction cache 130 and the shared data cache 140 according to another embodiment will be described.

To run the processor core smoothly, you need an instruction cache that stores instructions that are likely to be used in the on-chip memory. A typical instruction cache that can support only one processor core stores a block of memory consisting of sequential instructions in on-chip memory and uses a portion of the instruction address as a tag to ensure that the memory block exists in the cache. Store in a separate memory. In this way, the on-chip memory storing the instruction block is called a cache memory, and the on-chip memory storing the tag is called a tag memory. The process of providing an instruction to a processor by a general instruction cache includes: (a) Tag Matching, which checks whether the requested instruction is in cache memory by comparing a portion of the instruction at the address requested by the processor core to the tag stored in the tag memory. Step (b) Instruction Blocking Loading, which reads the instruction block from the external memory and stores it in the cache memory if the requested instruction does not exist in the cache memory, and (c) the cache memory through tag matching. If it is confirmed that there exists at or the instruction block is finished loading, it consists of Instruction Reading step that reads instruction from cache memory.

When concurrently supporting instructions for a plurality of processor cores 120, a Cache Memory Conflict for accessing cache memory by a plurality of processor cores 120 and / or a Tag Matching Conflict for matching tags simultaneously ) Occurs. In order to resolve such conflicts, the multiprocessor system 100 according to another embodiment of the present invention includes a shared instruction cache 130.

6 is a detailed view illustrating a structure of a shared instruction cache, FIG. 7 is a diagram illustrating a data arrangement method of a main memory, FIG. 8 is a diagram illustrating a data arrangement method of an existing cache memory, and FIG. 9 is an embodiment of the present invention. FIG. 10 is a diagram illustrating a data arrangement method of an interleaved instruction cache memory, and FIG. 10 is a detailed diagram illustrating a structure of a shared data cache.

Referring to FIG. 6, a plurality of processor cores 120a, 120b, 120c, and 120d (hereinafter, collectively referred to as 120), a shared instruction cache 130, an instruction buffer 610, and an interleaved instruction cache memory 620, tag memories 630a, 630b (hereinafter collectively referred to as 630), cache controller 640, and block-fill controller 650 are shown.

In order to support instructions for the plurality of processor cores 120, tag matching and instruction reading must be simultaneously performed for each processor core 120. Interleaved instruction cache memory 620 is used to support such simultaneous instruction reading. The interleaved instruction cache memory 620 constitutes a cache memory using a plurality of on-chip memories 622a, 622b, 622c, 622d, and 622, and 622, and the instructions constituting one instruction block are different on-chip memory. To be distributed to

Interleaved instruction cache memory 620 includes an internal communications network 624 and one or more on-chip memories 622. The internal communication network 624 may store instructions in the selected on-chip memory 622 or store instructions stored in the selected on-chip memory 622 according to the on-chip memory selection signal from the cache controller 640. Send to.

This structure looks similar to the memory structure of a conventional set-associative cache, but differs in that one instruction block is stored in one on-chip memory. When instructions requested by the plurality of processor cores 120 are stored in different on-chip memories, instructions of different addresses may be simultaneously read and provided to the corresponding processor cores. However, if two processor PAs and PBs refer to different memories, and if they are inadvertently stored in the same on-chip memory, one processor should stop performing.

In this case, since instructions are very likely to be read sequentially, in a conventional set-associative cache memory scheme, one processor refers to all the instruction blocks and moves on to the next instruction block, or the branch instruction refers to another instruction block. It keeps crashing and slowing performance until you do. In contrast, in the interleaved instruction cache memory structure, a time delay occurs only once, and then on-chip memory access conflicts are naturally resolved. A detailed description thereof will be given below with reference to FIG. 8.

Referring to FIG. 8, an existing Set-associative cache is shown. The existing set-associative cache uses a plurality of memory cells 810, 820, 830, and 840 in parallel to simultaneously read / write data. Here, each of the memory cells 810, 820, 830, and 840 is implemented with SRAM.

However, referring to FIG. 9, in the interleaved instruction cache memory according to an exemplary embodiment of the present invention, several memory cells 910, 920, 930, and 940 are connected in parallel, such as the set-associative cache illustrated in FIG. 8. have. Here, each of the memory cells 910, 920, 930, and 940 is implemented with SRAM. However, in order to minimize the collision due to the simultaneous access of the plurality of processor cores 120, data is arranged in each of the memory cells 910, 920, 930, and 940.

The data of the main memory 700 are stored in the cache memory in blocks of N words. 7 to 9 assume that one block is composed of four words. In addition, it is assumed that the A, B, C, and D blocks of the main memory 700 are cached in Way0, Way1, Way2, and Way3, respectively.

In a typical set-associative cache structure, one SRAM is allocated to each path. This is due to the timing characteristics of the SRAM. Synchronous SRAM (SRAM) used in tag memory and cache memory implementations, when an address is applied, data is output to the next clock cycle. Thus, tag matching occurs over two cycles. In the first cycle, all tag memories are addressed, and the next cycle receives tag information from the tag memory and finds a hit path among them. If the tag matching is completed, the path where the data is stored is found, the address is applied to the cache memory, and the data is read in the next cycle, which takes a total of three clock cycles. Therefore, most caches also address all cache memory in the first cycle of tag matching, and then find out the path where the data is stored in the next cycle, and then provide the processor core with the data output from that cache memory. That is, since all paths must be read at the same time, one SRAM is allocated to each path (see FIG. 8).

However, this approach is not suitable for shared caches that support multiple processor cores. In general, caches, especially instruction caches, have a high rate of requesting data sequentially. For example, if a processor core approaches Way0 at any moment, it is very likely that the next cycle will read that data from Way0. Assuming that the first processor core and the second processor core approach Way0 at the same time, one processor core must not stall because it does not receive data. However, in the next cycle, the first processor core and the second processor core continue to collide with each other, causing a serious performance degradation.

To solve this, one embodiment of the present invention arranges data as shown in FIG. First, each word constituting the block is placed in different memory cells. And if the cache memory is composed of four memory cells (910, 920, 930, 940), that is, M0, M1, M2, M3, and four paths, that is, Way0, Way1, Way2, Way3, Way0 is configured. Words are M0, M1, M2, M3 in order, Words constituting Way1 are M1, M2, M3, M0, Words constituting Way2 are M2, M3, M0, M1, Way3 Words are placed in M3, M0, M1, M2. With this arrangement, even if one processor core is delayed because the first processor core and the second processor core collide in the first cycle, the collision is resolved in the next cycle.

In addition, the shared instruction cache 130 must support simultaneous tag matching. However, the tag memory 630 may not be implemented in the interleaved structure described above. And managing multiple tag memory copies to support simultaneous tag matching is inefficient in area.

Instructions tend to be accessed sequentially. Therefore, the shared instruction cache 130 performs tag matching only when first accessing an instruction block, and tag matching skipping skips tag matching when sequentially reading instructions belonging to the instruction block. ) Method. The tag matching skipping method can reduce the frequency of tag matching.

When the processor core 120 executes a branch instruction, the shared instruction cache 130 matches a tag only when the processor core 120 requests an instruction having a sequential address but the instruction is stored in another instruction block. Do this.

In addition, the shared instruction cache 130 may further include an instruction buffer 610 for each processor core. In the case of using the interleaved instruction cache memory 620, if a plurality of processor cores access the same on-chip memory, only one processor core can supply an instruction, and the remaining processor cores are not supplied with the instruction, and thus performance is degraded. . In addition, when the tag matching skipping method simultaneously executes branch instructions in different processor cores, tag matching may be performed on only one processor core, and the remaining processor cores may not perform tag matching, and thus execution may be stopped. Performance is degraded. The instruction buffer 610 solves these problems.

The shared instruction cache 130 reads instructions from the interleaved instruction cache memory 620 in advance and stores them in the instruction buffer 610 before each processor core 120 requests the instructions. When the processor core 120 requests an instruction but the corresponding instruction is stored in the instruction buffer 610, the processor core 120 provides the instruction. When comparing the case where the instruction buffer 610 is embedded with the case where the instruction buffer 610 is not included, the collision of the cache memory and the tag matching collision occur the same number of times. However, when the instruction buffer 610 is built, the instruction buffer 610 even though the collision occurs. In order to provide instructions to the processor core 120, the performance is improved.

The command buffer 610 may include a branch checker 612. The branch classifier 612 finds out whether the processor core 120 has executed a branch instruction. If the processor core 120 performs the branch instruction, the instruction buffer 610 is cleared and the cache controller 640 is notified through the branch status signal. Increasing the instruction buffer 610 may improve performance since more instructions may be prefetched. However, to this end, the bandwidth between the on-chip memory 622 and the instruction buffer 610 must be increased than the bandwidth between the instruction buffer 610 and the processor core 120. FIG. 6 illustrates a case in which the processor core 120 and the instruction buffer 610 are connected by a 32-bit line and the instruction buffer 610 and the on-chip memory 622 are connected by a 64-bit line. This is only an example and other implementations are possible.

When a cache memory conflict and a tag matching conflict occur, the cache controller 640 preferentially supports requests having a small number of instructions stored in the instruction buffer 610 among instruction fetch requests. To this end, the instruction buffers 610 properly encode the number of stored instructions and deliver them to the cache controller 640 via a pre-fetch pressure signal. The cache controller 640 uses the branch status signal and the pre-fetch pressure signals to determine which processor core 120 to read an instruction from, and then sends an on-chip memory selection signal for each on-chip memory 622. Accordingly, an appropriate command is read from each on-chip memory 622 and inserted into the corresponding command buffer 610. The cache controller 640 also performs tag matching, and when tag matching for multiple addresses is required, tag matching is performed first for a sequential instruction request having no instructions in the instruction buffer 610 at all. Tag matching for the request is then performed, and tag matching for other requests is performed last.

If the cache controller 640 determines that the requested instruction does not exist in the interleaved instruction cache memory 620 as a result of the tag matching, it notifies the block-fill controller 650 via the instruction block request signal. The block-fill controller 650 reads the instruction block from the external memory via the system bus and stores it in the interleaved instruction cache memory 620.

In order to smoothly operate the processor core 120, a data cache having stored therein an on-chip memory having high probability of reading or writing the data together with the instruction cache is essential. The shared data cache 140 is a data cache capable of simultaneously supporting data read or write requests of the plurality of processor cores 120. Referring to FIG. 10, a shared data cache 140, a plurality of processor cores 120, an interleaved data cache memory 1020, a cache controller 1040, a block-fill controller 1050, a history buffer 1010, History tester 1015 and tag memories 1030a, 1030b, 1030c, 1030d, hereafter referred to as 1030, are shown.

Data access can be divided into two types. One is stack memory access and the other is heap memory access.

Stack memory is used for local variables, arguments passed to sub-programs when calling procedures (or functions), and temporary memory for the compiler to evacuate register values. Stack memory has its own area for each processor core (or task performed on the processor core). Typically, about 50-70% of data accesses are stack memory accesses.

Heap memory is the area where variables or array variables that are dynamically allocated by software are placed. A software program (or a task) operates very many dynamic variables, but in a short time a few dynamic variables are often used.

That is, in the case of the stack memory, the frequency of accessing the address before and after the stack pointer of the processor core is very high, and in the case of the heap memory, the recently accessed dynamic variable is more likely to be accessed again. In consideration of this, the shared data cache 140 according to an embodiment of the present invention applies a history-based hierarchical tag matching scheme.

History-based hierarchical tag matching is as follows.

In the first step, the recently accessed tags of stack memory and heap memory are stored in the history buffer 1010. In a second step, when there is a new data access request, the history tester 1015 first compares the tag stored in the history buffer 1010 with the requested address and checks whether the data exists in the interleaved data cache memory 1020. In a third step, if the determination is not yet completed in the second step, the tag memory 1030 reads the tag and attempts tag matching. There is one history buffer 1010 for each processor core 120, and the tag matching collision is significantly reduced because a large number of data access requests are found to be cache-hit in the second stage.

The history buffer 1010 stores a plurality of tags of recently accessed addresses. In another embodiment, since the stack memory access and the heap memory access differ according to the application, the history buffer 1010 may distinguish the stack memory access from the heap memory access and store different numbers of tags. One of the methods of determining stack memory access and heap memory access among data accesses is that the data access within a range from the current stack pointer is regarded as stack memory access, and the other is considered as heap memory access. It can be implemented without a head.

Other structures of the shared data cache 140 are similar in function to the shared instruction cache 130, and thus detailed description thereof will be omitted.

Meanwhile, the structure of the shared instruction cache 130 is illustrated in FIG. 6. An example of a two-path set associative cache is shown where two tag memories are coupled to cache controller 1040. This is just one embodiment, and if the shared instruction cache 130 is a four-path set associative cache, four tag memories are cached, such as the shared data cache 140 shown in FIG. May be connected to the controller 1040.

Further, according to another embodiment of the present invention, a multiprocessor system includes both a hardware operating system, a shared instruction cache, and a shared data cache. The hardware operating system reduces multithreading overhead, while shared instruction caches and shared data caches reduce pre-operation overhead and system area.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

1 is a schematic diagram illustrating a structure of a multiprocessor system according to an embodiment of the present invention.

2 is a detailed diagram illustrating the structure of a hardware operating system.

3 is a detailed diagram illustrating a structure of a thread control memory.

4 is a flowchart of a multi-threaded program execution process in a software operating system.

5 is a flowchart illustrating a multi-threaded program execution process in a hardware operating system according to an embodiment of the present invention.

6 is a detailed diagram illustrating the structure of a shared instruction cache.

7 is a diagram illustrating a data arrangement method of a main memory.

8 is a diagram illustrating a data arrangement method of an existing cache memory.

9 is a diagram illustrating a data placement method of an interleaved instruction cache memory according to an embodiment of the present invention.

10 is a detailed diagram illustrating the structure of a shared data cache.

<Description of the symbols for the main parts of the drawings>

10: coprocessor 100: multiprocessor system

110: hardware operating system 120: processor core

122: register file 124: context controller

130: shared instruction cache 140: shared data cache

210: main controller 220: thread control memory

230: thread manager 240: context memory

250: context manager 260: context buffer

610: instruction buffer 620: interleaved instruction cache memory

630: tag memory 640: cache controller

650 block-fill controller 1010 history buffer

1020: interleaved data cache memory 1030: tag memory

1040 cache controller 1050 block-fill controller

Claims (19)

delete A plurality of processor cores; And A hardware operating system connected to the plurality of processor cores through an operating system bus, the hardware operating system performing hardware for interrupt handling, task synchronization, task scheduling, context exchanging, and task resume operations for operating system service requests from the plurality of processor cores. and, The hardware operating system, A thread control memory for storing job information which is one of a job status, priority, wait queue, semaphore status, and a combination thereof; A thread manager that selects the highest priority job among the jobs registered in the waiting queue and controls semaphore access; A context memory in which a context of a generated job is stored; A context buffer in which a context of a task to resume execution or a context of a task in which execution is stopped is stored; A context manager that reads a context for a job selected by the thread manager from the context memory and stores the context in the context buffer or stops performing and stores the context of the job stored in the context buffer in the context memory; And And a main controller coupled to the operating system bus and controlling the thread manager and the context manager in response to the operating system service request from the processor core. The method of claim 2, The thread control memory may include a ready queue having a first value when the job is in a wait state and a second value when the job is suspended, and information for job scheduling including a priority of the job. And semaphore access control information including semaphore status flags and semaphore values for each semaphore, and a wait queue for registering jobs waiting on the semaphore. The method of claim 3, The thread control memory includes a thread descriptor and a semaphore descriptor, And obtaining the information for the job scheduling, the information for the semaphore access control, and the suspension queue from the field value of the thread descriptor and the field value of the semaphore descriptor. The method of claim 4, wherein Information for scheduling the job is stored in two fields indicating the upper and lower bits of the priority of the field of the thread descriptor, The information for the semaphore access control is stored in each of the fields of the semaphore descriptor, the flag indicating whether the semaphore descriptor is used, the flag indicating the type of the semaphore, and the three fields in which the semaphore value is stored. Processor system. The method of claim 5, And the suspend queue is implemented using the remaining one field of the semaphore descriptor and the remaining two fields of the thread descriptor. The method of claim 6, If the remaining one field of the semaphore descriptor is negative, it indicates that at least one job is registered in the suspension queue, and the ID of the first job is stored in the first field of the remaining two fields of the thread descriptor. When the second field is the first value, it indicates that another job is additionally registered in the suspension queue, and an ID of a subsequent job is stored in the first field. If the second field is the second value, it indicates that the job is the last job registered in the suspension queue. delete In a multiprocessor system comprising a plurality of processor cores, An operating system connected to the plurality of processor cores to perform interrupt handling, task synchronization, task scheduling, context switching, and resume operation operations on operating system service requests from the plurality of processor cores; A shared instruction cache in which instructions supporting the plurality of processor cores are stored in advance; And And a shared data cache in which data supporting the plurality of processor cores are stored in advance, wherein the shared instruction cache includes: An interleaved instruction cache memory including an internal communication network and a plurality of on-chip memories, wherein words constituting one instruction block are distributed and stored in different on-chip memories, and the distributed words can be read simultaneously. ); A tag memory for storing a part of an instruction block stored in the interleaved instruction cache memory as a tag; Comparing a part of the command according to the operating system service request with a tag stored in the tag memory, and performing tag matching to determine whether the requested command exists in the interleaved command cache memory, and performing the tag matching result. A cache controller configured to output the instruction block request signal when a specified instruction does not exist in the interleaved instruction cache memory; And And a block-fill controller configured to read an instruction block from an external memory through a system bus according to the instruction block request signal and store the instruction block in the interleaved instruction cache memory. The method of claim 9, The interleaved instruction cache memory may have a different order in which the interleaved instruction cache memory is distributed and stored in the plurality of on-chip memories with respect to different paths. The method of claim 9, The shared instruction cache performs a tag matching when first accessing an instruction block, and when a command belonging to the instruction block is sequentially read, a tag matching skipping scheme that skips the tag matching. And a multiprocessor system. The method of claim 11, The shared instruction cache is configured to perform the tag matching when one of the plurality of processor cores executes a branch instruction, when the processor core requests an instruction having a sequential address but the instruction is stored in another instruction block. A multiprocessor system characterized by the above. The method of claim 9, The shared instruction cache may further include an instruction buffer that is allocated to each of the plurality of processor cores and that reads and stores the instruction from the interleaved instruction cache before the allocated processor core requests the instruction. Multiprocessor system. The method of claim 13, The instruction buffer includes a branch status signal indicating whether the allocated processor core has performed a branch instruction and a pre-fetch pressure signal indicating the number of instructions stored in the instruction buffer. Pass to the cache controller, The cache controller determines an instruction to be read using the branch state signal and the pre-fetch pressure signals, and then outputs an on-chip memory selection signal to the plurality of on-chip memories through the internal communication network so that the instruction is executed. Multiprocessor system characterized in that it is inserted into the buffer. The method of claim 9, The shared data cache, An interleaved data cache memory including an internal communication network and a plurality of on-chip memories, wherein words constituting one data block are distributed and stored in different on-chip memories, and the distributed stored words can be read simultaneously. ); A tag memory for storing a part of a data block stored in the interleaved data cache memory as a tag; The tag matching is performed to compare whether the requested data exists in the interleaved data cache memory by comparing a portion of data according to the operating system service request with a tag stored in the tag memory, and the requested data is determined by the tag matching result. A cache controller for outputting the data block request signal when not in an interleaved data cache memory; And And a block-fill controller for reading a data block from an external memory through a system bus according to the data block request signal and storing the data block in the interleaved data cache memory. The method of claim 15, The shared data cache, A history buffer for storing tags of addresses of on-chip memory that have been accessed within a predetermined time; And And a history tester comparing the tag stored in the history buffer with a requested address to determine whether the requested data exists in the interleaved data cache memory. The method of claim 16, And if the determination is not completed by the history tester, the cache controller reads the tag from the tag memory and performs the tag matching. The method of claim 16, And the history buffer stores the tag by distinguishing a stack memory access from a heap memory access. delete

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