KR100930377B1 - Photomask and Manufacturing Method - Google Patents

Abstract

A light absorption layer and a resist layer are sequentially formed on the transparent substrate, and the layout of the large area pattern including the relatively large area to be transferred onto the wafer is set, and the large area pattern in the layout of the large area pattern is divided into a plurality of small patterns. Insert partition space patterns that are divided into The layout of the large-area pattern into which the divisional space patterns are inserted is transferred to the resist layer by using electron beam exposure, the exposed resist layer is developed to form a resist pattern, and then the optical absorption layer exposed to the resist pattern is selectively etched and masked. A photomask manufacturing method for forming a pattern is provided.

Static phenomenon, mask defects, large area pattern, mask

Description

Photomask and manufacturing method for the same

1 is a plan view schematically illustrating a conventional photomask manufacturing method.

2 is a layout diagram schematically illustrating a photomask and a manufacturing method according to an embodiment of the present invention.

3 to 5 are cross-sectional views schematically illustrating a photomask and a manufacturing method according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a simulation result to explain a photomask and a manufacturing method according to an exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and, more particularly, to photomasks and fabrication methods used in lithography processes.

The semiconductor device is formed by implementing a circuit pattern on a wafer. The circuit pattern is transferred onto the wafer using a lithography process using a photomask, such as an exposure and development process. To this end, a process of designing a circuit pattern and implementing the designed circuit pattern on a photomask is performed first. Although the manufacturing process of the photomask may be partially modified depending on the semiconductor device, it is understood that the photomask is composed of a portion where light is absorbed, for example, a light blocking region (or a phase shift region) and a portion where light is transmitted. Can be.

The photomask is manufactured to form a shape of a circuit pattern in which a portion where light is absorbed and a portion where light is transmitted, for example, mask patterns. The formation of a mask pattern on the photomask involves an electron beam writing process for drawing a circuit designed using an electron beam (e-beam) in a resist layer.

Meanwhile, among the circuit patterns to be implemented on the wafer, a large area pattern that occupies a relatively large area may exist, and such a large area pattern may exist as an isolated pattern that is not connected to other circuit patterns around it. have. Such a large area pattern may be understood as a pattern having a relatively large area compared to, for example, a gate line or other wiring lines.

However, since a large area mask pattern including chromium (Cr) occupies a relatively large area, electrons may be relatively concentrated in the large area mask pattern during the electron beam writing process. Accordingly, in the process of selectively etching a mask layer, for example, a chromium layer after electron beam writing, an electrostatic phenomenon is induced at a portion where a large area mask pattern is formed. Accordingly, the phenomenon in which the corners or edge portions of the large-area mask pattern fall off undesirably is generated, as shown in FIG. 1.

1 is a plan view schematically illustrating a conventional photomask manufacturing method. The large area pattern 10 to be implemented on the actual wafer may have a rectangular shape, such as an outline 11 of dotted lines. However, when the edge portion 13 is removed due to the electrostatic phenomenon occurring in the mask pattern providing the shape of the large-area pattern 10, the pattern 15 actually formed on the wafer has a defective pattern in which the edge portion or the like falls off. It will be formed. Thus, this phenomenon can be understood as a mask defect element.

An object of the present invention is to present a layout of a photomask that can suppress an electrostatic phenomenon.

The technical problem to be achieved by the present invention is to provide a photomask manufacturing method that can suppress the electrostatic phenomenon.

One aspect of the present invention for the above technical problem, the step of sequentially forming a light absorption layer and a resist layer on a transparent substrate, setting a layout of a large area pattern including a relatively large area to be transferred onto the wafer, Inserting partition space patterns for dividing the large area pattern into a plurality of small patterns in the layout of the large area pattern; using electron beam exposure to layout the large area pattern into which the partition space patterns are inserted; Transferring to the resist layer, developing the exposed resist layer to form a resist pattern, and selectively etching the light absorbing layer exposed to the resist pattern to form a mask pattern Give a way.

In addition, another aspect of the present invention includes a transparent substrate and a mask pattern, wherein the mask pattern includes a large area pattern including a relatively large area formed on the transparent substrate, and the large area pattern includes a plurality of small areas. A photomask including divided space patterns that divide into patterns is presented.

The divided space patterns may be set to include empty spaces having a line shape intersecting in the large area pattern.

The division space patterns may be set to have a line width shorter than the resolution limit wavelength band of the wafer exposure process to exclude the transfer of the mask pattern onto the wafer during the wafer exposure process.

The light absorption layer may include a light blocking layer, a phase shift layer, or a halftone layer that absorbs light passing through the transparent substrate during a wafer exposure process.

The large area pattern may be set to an isolated pattern electrically disconnected from other neighboring patterns.

According to the present invention, it is possible to provide a photomask and a manufacturing method capable of suppressing the electrostatic phenomenon by modifying the layout of a large area pattern in which the electrostatic phenomenon is concentrated.

An embodiment of the present invention provides a method of suppressing or overcoming electrostatic phenomena that may occur in a large area of a relatively large area of a circuit part by an electron beam writing process during photomask fabrication.

A large area pattern that occupies a relatively large area may be understood as a larger area pattern than a wiring line such as a gate line, for example, a pattern for a capacitor in a peripheral circuit region, or a pattern such as a pad. have. The large area pattern can be understood as a pattern of considerably larger linewidth compared to the minimum CD on the design rule of the circuit pattern implemented on the wafer. This large area pattern can be designed primarily as an isolated pattern that is not electrically connected to other neighboring patterns.

In an embodiment of the present invention, a scattering space pattern is inserted into a layout of a large area pattern, thereby dividing the large area pattern into a plurality of sub-patterns. The conditions to be considered when inserting the space pattern for such division, for example, the line width of the space or the line width of the empty spaced interval, may be set depending on the exposure conditions of the exposure process, for example, the degree of resolution, etc. using a photomask. For example, the space line width is preferably set to such an extent that a real pattern is not transferred to the actual wafer by exposure. In other words, the space line width is preferably formed with a line width shorter than the wavelength band as the resolution limit during exposure.

2 is a layout diagram schematically illustrating a photomask and a manufacturing method according to an embodiment of the present invention. 3 to 5 are cross-sectional views schematically illustrating a photomask and a manufacturing method according to an embodiment of the present invention. FIG. 6 is a schematic diagram of a simulation result to explain a photomask and a manufacturing method according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the photomask and the manufacturing method according to the embodiment of the present invention design a mask layout 210 to be formed on the photomask. Specifically, the light transmission region 220 through which light is transmitted during exposure and the light absorption region 230 through which light is absorbed are set. In this case, the light absorption region 230 may be designed in a large area pattern. Subsequently, the partition space patterns 240 for dividing the large area pattern into a plurality of small patterns 231 are inserted into the layout of the light absorption region 230 designed as the large area pattern. Accordingly, the layout of the light absorption region 230 designed in a large area pattern may be understood as a set of a plurality of small patterns 231 divided by the division space patterns 240.

The divided space patterns 240 may be set to include empty spaces having a line shape intersecting in the light absorption region 230 of the large area pattern. In addition, the division space patterns 240 are set to have a line width that is excluded from being transferred onto the wafer when performing the wafer exposure process using the photomask in which the layout 210 is reflected. For example, it may be set to a scattering space pattern having a line width shorter than the resolution limit wavelength band of the wafer exposure process so that the actual pattern is not transferred onto the wafer.

When the mask layout 210 set as described above is transferred onto the actual mask substrate to form a photomask, the electron beam writing process is divided into small patterns 240 having a smaller area than the light absorption region 230 of the large area pattern. The accumulation of electrons attributable to can be relatively dispersed. Accordingly, in the subsequent patterning process, the occurrence of pattern defects or mask defects in which the edges of the mask pattern and the like fall off due to the electrostatic phenomenon can be suppressed.

Referring to FIG. 3, a light absorbing layer 330, for example, a chromium (Cr) layer, is formed on a transparent substrate 310, for example, a quartz substrate, and a resist layer 350 is formed to form an etching mask for patterning the light absorbing layer 330. To form. In this case, the light absorption layer 330 may mean a light blocking layer having a relatively high light absorption rate, such as a chromium layer, a phase shift layer, or a halftone layer, depending on the type of photomask to be formed. Accordingly, the photomask in the embodiment of the present invention may be a binary mask, a phase shift mask (PSM), or a halftone PSM.

Referring to FIG. 4, the mask layout 210 set as shown in FIG. 2 is transferred to the resist layer 350 using electron beam exposure. Accordingly, not only the first portion 352 corresponding to the light transmission region 220 but also the second portion 354 corresponding to the division space pattern 240 are exposed to the electron beam. Thereafter, the exposed resist layer 350 is developed to form a resist pattern. That is, portions of the first and second portions 352 and 354 exposed to the electron beam are selectively removed.

Referring to FIG. 5, the light absorption layer 330 exposed to the resist pattern formed by electron beam exposure and development is selectively etched to form a light absorption layer pattern, that is, a mask pattern 332. In this case, the mask pattern 332 is a pattern corresponding to the light absorption region 230 of the layout of FIG. 2, and the separation part 334 may be understood as an area corresponding to the division space pattern 240. The light absorption region 230 designed in a large area pattern is composed of mask patterns 332 divided by a plurality of spaced apart portions 334 spaced apart from each other.

As in the exemplary embodiment of the present invention, since the mask patterns 332 are formed to correspond to the smaller patterns (231 of FIG. 2) having a smaller area, it is possible to suppress the accumulation of electricity such as electrons in the electron beam exposure process. That is, since the area of the mask pattern 332 is smaller than the light absorption region 230 set to a larger area pattern, the amount of charge charged and stored in the individual mask patterns 332 is relatively reduced. Therefore, it is possible to suppress or prevent the occurrence of static electricity due to charged charges during the etching process. Accordingly, when implementing a large-area set pattern, it is possible to suppress the occurrence of unwanted defects or defects that the edges or edge portions fall off during etching.

Meanwhile, by setting the line width of the division space pattern 240 as a scattering space pattern in the layout 210 of FIG. 2, the actual division space pattern 240 may be excluded from being implemented on the wafer. This can be confirmed by the graph 610 of FIG. 6, which is a result of exposure simulation using the layout of FIG. 2 in which the division space pattern 240 is inserted into the scattering space.

Referring to FIG. 6, the intensity of light transmitted onto the actual wafer during exposure is measured to be very low overall in the portion 613 corresponding to the light absorption region 230, and corresponds to the light transmission region 220. In part 611, the overall measurement is very high. In the graph portion 615 corresponding to the portion of the divided space pattern 240, some light intensity peaks may be detected, but the intensity is very low, so that the actual pattern on the actual wafer is implemented. It is difficult to judge the intensity of the exposure. Therefore, despite the introduction of the divided space pattern 240, it can be understood that one large area pattern is implemented on the actual wafer, rather than a dense pattern of divided patterns.

According to the present invention described above, by dividing the light absorption region implemented in a large area pattern on the wafer into a plurality of divided space patterns, a mask pattern corresponding to the large area pattern is divided or grouped into small groups. Can be formed into a sieve. Accordingly, the electronic charging phenomenon that may be involved in the electron beam exposure for etching the mask pattern may be alleviated, suppressed or excluded by greatly reducing the area of the pattern to be realized. Thus, it is possible to provide a photomask capable of transferring a large area pattern having a more sophisticated edge profile onto the wafer.

As mentioned above, although this invention was demonstrated in detail through the specific Example, it is not preferable that this invention is interpreted as limited to this. Embodiments of the invention are preferably to be interpreted as being provided to those skilled in the art to more fully describe the invention. In addition, it can be understood that the present invention can be modified or improved by those skilled in the art within the technical idea of the present invention.

Claims (6)

Sequentially forming a light absorption layer and a resist layer on the transparent substrate; Setting a layout of a large area pattern including a relatively large area to be transferred onto the wafer; Inserting partition space patterns into a layout of the large area pattern, including partition space patterns for dividing the large area pattern into a plurality of small patterns, including empty spaces in the form of intersecting lines in the large area pattern; Transferring the layout of the large area pattern into which the division space patterns are inserted, to the resist layer using electron beam exposure; Developing the exposed resist layer to form a resist pattern; And And selectively etching the light absorbing layer exposed to the resist pattern to form a mask pattern. delete The method of claim 1, The partition space patterns And a line width shorter than the resolution limit wavelength band of the wafer exposure process to exclude the transfer of the mask pattern onto the wafer during the wafer exposure process. The method of claim 1, The light absorption layer is A photomask manufacturing method comprising a light blocking layer, a phase shift layer, or a halftone layer that absorbs light passing through the transparent substrate during a wafer exposure process. The method of claim 1, The large area pattern is A photomask manufacturing method comprising an isolated pattern electrically isolated from other neighboring patterns. Transparent substrates; And Dividing the large area pattern into a plurality of small patterns, including a large area pattern including a relatively large area formed on the transparent substrate, and an empty space in the form of lines intersecting within the large area pattern. A photomask comprising a mask pattern comprising partition space patterns.

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