KR100927130B1 - The apparatus of communication converting between embedded system and pc and method thereof - Google Patents

Abstract

PURPOSE: A high-speed serial communication conversion device between pc and an embedded system and a method thereof are provided to communicate with the embedded system at high speed by enabling a PCI control device to communicate with a PCI bus through a burst DMA(Direct Memory Access) mode. CONSTITUTION: A PCI board includes the followings. A PCI control device(210) receives data and transmits the received data. A first FPGA includes a local control module and a local transmission module. The local control module receives data. The local control module stores the received data as a first data. The local transmission module divides the first data. The divided second data is transmitted to a first interface(250). The first interface converts the second data into serial data.

Description

High speed serial communication converter and method between PC and embedded system {THE APPARATUS OF COMMUNICATION CONVERTING BETWEEN EMBEDDED SYSTEM AND PC AND METHOD THEREOF}

The present invention relates to a high speed serial communication conversion device and method between a PC and an embedded system, and in particular, a high speed serial communication conversion between a PC and an embedded system capable of communicating between a PC and an embedded system without a difference in work speed between the PC and the embedded system. An apparatus and method are provided.

Embedded System (Embedded System) is a computer system with special functions by embedding the software that operates the system into the hardware. Unlike personal computers (PCs), they have specific requirements and perform only predefined tasks. Examples of such embedded systems are mobile phones, PDAs and routers, and GPS navigation.

When a developer develops a program applied to such an embedded system, it is necessary to check and debug the execution without an error in the embedded system environment.

Developers who are more familiar with the PC environment than embedded systems spend a lot of time and effort debugging in these embedded systems. In order to solve this problem, the PC and the embedded system are connected to enable the debugging of the embedded system under the PC environment. This allows embedded system developers to save time and effort on development, such as debugging. However, even in this case, there is still a difference in environment between the PC and the embedded system, so there is a difference in work speed when transferring data from the PC to the embedded system, and the embedded system cannot process this at high speed and the PC is overloaded. .

The present invention is to solve the above problems, the PCI board stores the data transmitted from the PC in the form of the first data, and during transmission by transmitting M pieces of second data divided into N bit units It is an object of the present invention to provide a high speed serial communication conversion device and method between a PC and an embedded system that can be executed in an embedded system without the difference in the work speed between the PC and the embedded system.

According to another embodiment of the present invention, the PCI control device communicates with the PCI bus via Burst Direct Memory Access (DMA) mode, thereby allowing a high speed between the PC and the embedded system to communicate with the embedded system at high speed without overloading the PC. An object of the present invention is to provide a serial communication conversion device and method.

In order to achieve the above object, a high speed serial communication converter between a PC and an embedded system according to an exemplary embodiment of the present invention includes a PC, a PCI board connected to a PCI slot of the PC, and a communication board connected to the PCI board. In the high-speed serial communication converter between a PC and an embedded system comprising a, the PCI board, PCI control device for receiving data from the PC and transmits according to the PCI bus communication standard, the data from the PCI control device A local control module configured to receive and store the first data according to a storage capacity of the local transmit buffer, and divide the first data stored in the local transmit buffer into N bits and M units, and divide the second M units into M N bits. A first FPGA and a first FPGA comprising a local transmission module for transmitting data to a first interface; And a first SerDes device, which is a first SerDes device for converting and transferring second data from parallel data to serial data to interface a communication board, wherein the communication board includes: the PCI board and the second board; A second SerDes device which converts the serial data into parallel data to receive an FPGA, and receives the M second data from the second interface and stores an embedded reception buffer. An embedded reception module configured to combine and store the first data according to a capacity and an embedded control module configured to control the embedded system by transmitting the first data stored in the embedded reception buffer as third data suitable for the embedded system. An external device connecting the second FPGA and the second FPGA to the embedded system It characterized in that it comprises a connector.

A high speed serial communication converter between a PC and an embedded system according to another exemplary embodiment of the present invention may further include receiving the third data transmitted from the embedded system through the external connector to the storage capacity of an embedded transmission buffer. According to the first data, the second FPGA divides the first data stored in the embedded transmission buffer into N bits and M pieces, and divides the divided second data in M bits. And an embedded transmission module for transmitting to a second interface, wherein the first FPGA receives the M pieces of second data through the first interface and transfers the M pieces of data to the first data according to a storage capacity of a local reception buffer. And further comprising a local receiving module configured to combine and store the local control module. The first data is transmitted to the PC through the PCI control device when the first data is received from a local reception buffer.

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In a high speed serial communication conversion apparatus between a PC and an embedded system according to another embodiment of the present invention, the first interface communicates with 18 bits of data, wherein D15 to D0 bits are the second data, and D17 bits are the M N bits. Transmission information regarding data transmission, the D16 bit is characterized by consisting of the data for the first In Forst Out (FIFO) state of the local receive buffer.

A high speed serial communication converter between a PC and an embedded system according to another embodiment of the present invention may be configured such that the PCI control device communicates with the PCI bus in any one of a target single transmission mode and a burst direct memory access (DMA) mode. It is characterized by.

A high speed serial communication converter between a PC and an embedded system according to another exemplary embodiment of the present invention may include a local bus interface interfaced with a local bus that the PCI control device communicates with a CPU of the PC, and a control module that controls the PCI control device. And a PCI interface for transmitting the data through the PCI bus.

A high speed serial communication converter between a PC and an embedded system according to another embodiment of the present invention is characterized in that the third data is data corresponding to 16 bit SRAM.

The apparatus for converting a high speed serial communication between a PC and an embedded system according to another embodiment of the present invention is characterized in that the local transmit buffer and the embedded receive buffer are 64K × 16 bit high speed SRAMs.

The apparatus for converting a high speed serial communication between a PC and an embedded system according to another embodiment of the present invention is characterized in that the local reception buffer and the embedded transmission buffer are 64K × 16 bit high speed SRAM.

A high speed serial communication converter between a PC and an embedded system according to another exemplary embodiment of the present invention may further include a first display unit configured to display an operation state of the PCI board or a connection state of the PCI board and the communication board. Characterized in that it comprises a.

In the high-speed serial communication conversion device between the PC and the embedded system according to another embodiment of the present invention, the reset of the first display unit of the operation state of the PCI board is "0", the data transfer from the PCI board to the communication board (Write ) Is " 2 " and data read from the communication board to the PCI board is " 3 ".

A high speed serial communication converter between a PC and an embedded system according to another exemplary embodiment of the present invention may further include a second display unit configured to display an operation state of the communication board or a connection state of the communication board and the PCI board. Characterized in that it comprises a.

High speed serial communication converter between the PC and the embedded system according to another embodiment of the present invention, the cable is characterized in that the STP cable.

A high speed serial communication conversion method between a PC and an embedded system according to another embodiment of the present invention includes a PC, a PCI board connected to a PCI slot of the PC, and a PC configured to include a communication board connected through a cable with the PCI board. A method for converting a high speed serial communication between a system and an embedded system, the PCI board receiving data from the PC and transmitting the data in any one of a target single transmission mode and a burst direct memory access (DMA) mode. step; A second step of the PCI board storing the data as first data according to a storage capacity of a local transmit buffer of the PCI board; A third step of dividing the first data into N bit units and M units and transmitting the divided second data of M N bit units to the communication board; A fourth step of receiving, by the communication board, the M second data and combining the second data into the first data according to a storage capacity of an embedded reception buffer of the communication board; And a fifth step of controlling the embedded system by transmitting the first data as third data suitable for the embedded system.

In the high-speed serial communication conversion method between the PC and the embedded system according to another embodiment of the present invention, after the fifth step, the communication board receives the third data transmitted from the embedded system to store the embedded transmission buffer storage capacity. A sixth step of storing the data as the first data; The seventh step of dividing the first data into N bits and M units and transmitting the second data of the divided M N bits units to the PCI board; An eighth step of receiving, by the PCI board, the M pieces of second data and combining the second data into the first data according to a storage capacity of a local reception buffer of the PCI board; And the PCI board performs a ninth step of transmitting the first data to the PC.

The high speed serial communication conversion method between a PC and an embedded system according to another embodiment of the present invention may be performed by the PCI board converting the second data from parallel data to serial data in the third step. In the fourth step, the communication board converts the serial data into parallel data and receives the same.

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The high speed serial communication conversion method between a PC and an embedded system according to another exemplary embodiment of the present invention is characterized in that the third data corresponds to 16 bit SRAM.

The high speed serial communication conversion method between a PC and an embedded system according to another embodiment of the present invention is characterized in that the local transmit buffer and the embedded receive buffer are 64K × 16 bit high speed SRAMs.

The high speed serial communication conversion method between a PC and an embedded system according to another embodiment of the present invention is characterized in that the local receive buffer and the embedded transmit buffer are 64K × 16 bit high speed SRAM.

In the high speed serial communication conversion device and method between a PC and an embedded system according to an embodiment of the present invention, a PCI board stores data transmitted from a PC in a first data form, and divides the first data in units of N bits during transmission. By transmitting M second data, it provides the effect that the user can be executed in the embedded system as the user controlled from the PC without a difference in the working speed between the PC and the embedded system.

High speed serial communication conversion device and method between a PC and an embedded system according to another embodiment of the present invention, the PCI control device communicates with the PCI bus through Burst DMA (Direct Memory Access) mode, without overloading the PC at high speed Provides the effect of communicating with embedded systems.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an overall configuration diagram of a high speed serial communication converter between a PC and an embedded system according to an exemplary embodiment of the present invention.

1 and 2, a high speed serial communication converter between a PC and an embedded system according to the present invention may include a PC board 100, a PCI board 200 connected to a PCI slot of the PC 100, and the PCI board ( It may be configured to include a communication board 300 connected through the 200 and the cable 500 and the embedded system 400 connected to the communication board 300.

In more detail, as illustrated in FIG. 3, the PCI board 200 may include a PCI control device 210, a first FPGA 230, and a first interface 250.

The PCI control device 210 receives data from the PC 100 and transmits the data according to the PCI bus communication standard, that is, the PCI board 200 and the PCI inside the PC 100 using the PCI control device. It allows slots to be connected and performs 32-bit data exchange of 120Mbyte / s.

The PCI control device 210 may be configured to include a local bus interface 211, a control module 213, and a PCI interface 215.

The local bus interface 211 interfaces with a local bus that communicates with the CPU of the PC 100. The control module 213 performs a function of controlling the PCI control device 210. PCI interface 215 may transfer data over a PCI bus.

In this case, the PCI control device 210 may communicate with the PCI bus in any one of a target single mode and a burst direct memory access (DMA) mode.

In Target Single mode, data is transmitted by the CPU of the PC. The transmission speed may be 4Mbyte / sec. In this Target Single mode, the CPU performance is reduced by 100% of the CPU, so the PCI control device can be used for register setting and small amount of data exchange.

Burst Direct Memory Access (DMA) mode transfers data without CPU intervention. The transfer speed can be 132 Mbyte / sec. In this burst DMA mode, the CPU is only concerned with the register settings of the PCI control device, and the transfer is automatic.

The first FPGA 230 may include a local control module 231, a local transmission buffer 233, and a local transmission module 235.

The local control module 231 receives data from the PCI control device 210 and stores the data as first data according to a storage capacity of the local transmission buffer 233. That is, the local control module 231 stores the data transmitted from the PC through the PCI control device 210 in the local transmission buffer 233 in consideration of the FIFO state of the local transmission buffer 233 so that the FIFO does not become full. .

The local transmission buffer 233 stores the first data by the local control module 231.

The local transmission module 235 divides the first data stored in the local transmission buffer 233 into N bit units and M pieces, and transmits the divided second data in M N bit units to the first interface 250. To perform. For example, when the first data is 64 bits, the first data may be divided into four pieces of data in 16 bit units and transmitted to the first interface.

The first interface 250 performs a function of interfacing the first FPGA 230 and the communication board 300.

The communication board 300 connected through the first interface 250 may include a second interface 310, a second FPGA 330, and an external connector 350, as shown in FIG. 3. have.

The second interface 310 performs a function of interfacing the PCI board 200 and the second FPGA 330.

In this case, in particular, the first interface 250 is a first SerDes device that converts second data from parallel data to serial data and transmits the same, and the second interface 310 parallelizes serial data. It may be a second SerDes device that converts and receives (parallel) data.

In order to transfer data processed in parallel from a terminal such as a PC to an embedded system, the data must be serially converted and then converted into serial data through the first SerDes device. The second SerDes device converts the serial data back into parallel data to perform data processing at high speed.

In particular, since the SerDed device is capable of 18-bit data communication, the first interface 250 communicates with 18-bit data so that D15 to D0 bits are second data, D17 bits are transmission information regarding M N-bit data transmission, The D16 bit may consist of data for the First In Forst Out (FIFO) state of the local receive buffer.

The second FPGA 330 may further include an embedded receiving module 331, an embedded receiving buffer 333, and an embedded control module 335.

The embedded receiving module 331 receives the M second data from a second interface, combines the first data according to an embedded storage capacity, and stores the M second data in the embedded receiving buffer 333. That is, four data of 16 bit units are made into 64 bit data and stored in the embedded reception buffer 333.

The embedded reception buffer 333 performs a function of storing the first data by the embedded reception module 331.

The embedded control module 335 transmits first data stored in the embedded reception buffer 333 as third data suitable for the embedded system 400 to control the embedded system 400. More preferably, the third data may be data corresponding to 16 bit SRAM.

The external connector 350 connects the second FPGA 330 to the embedded system 400.

On the other hand, contrary to the embodiment described above, when the data is input from the embedded system 400, it may be transmitted to the PC 100 through the communication board 300 and the PCI board 200.

That is, the embedded control module 335 receives the third data transmitted from the embedded system 400 through the external connector 350 and combines and stores the first data according to the storage capacity of the embedded transmission buffer 337. To do more.

The embedded transmission buffer 337 performs a function of storing the first data by the embedded control module 335.

The embedded transmission module 339 divides the first data stored in the embedded transmission buffer 337 into N bit units and M pieces, and transmits the divided second data in M N bit units to the second interface 310. To perform. For example, when the first data is 64 bits, the first data may be divided into four pieces of data in 16 bit units and transmitted to the second interface.

The second interface 310 transmits the second data to the local receiving module 237 of the PCI board 200 through the first interface.

The local receiving module 237 receives M second data through the first interface 250 and combines and stores the M second data into first data according to a storage capacity of the local receiving buffer 239.

The local receive buffer 239 performs a function of storing the first data by the local receive module 237.

In addition, when the local control module 231 receives the first data from the local reception buffer 239, the local control module 231 may further perform a function of transmitting the first data to the PC 100 through the PCI control device 210.

Meanwhile, more preferably, the local transmit buffer 233, the local receive buffer 239, the embedded receive buffer 333, and the embedded transmit buffer 337 may be 64K × 16 bit high speed SRAMs.

In addition, the high speed serial communication conversion device between the PC and the embedded system according to an embodiment of the present invention, the PCI board 200 is the operating state of the PCI board 200 or the connection state of the PCI board 200 and the communication board 300 It may be configured to further include a first display unit for displaying.

The first display unit resets "0" during the operation state of the PCI board 200, data transfer from the PCI board 200 to the communication board (Write) "2" and data transfer from the communication board to the PCI board (Read ) May be represented by "3".

The communication board 300 may further include a second display unit displaying an operation state of the communication board 300 or a connection state between the communication board 300 and the PCI board 200.

The cable 500 connecting the PCI board 200 and the communication board 300 may be an STP cable.

5 illustrates a high speed serial communication conversion method between a PC and an embedded system according to an exemplary embodiment of the present invention.

First, a first step S10 of transmitting data transmitted from the PC 100 to the PCI board 200 is performed.

The PCI board 200 may be connected to the PCI slot of the PC 100 to receive data from the PC.

The PCI board 200 may transmit data by communicating with the PCI bus in any one of a target single mode and a burst direct memory access (DMA) mode.

Next, the PCI board 200 performs a second step S20 of storing data as first data according to a storage capacity of the local transmission buffer 233 of the PCI board 200.

That is, the PCI board 200 stores the data transmitted from the PC in the local transmission buffer 233 in consideration of the FIFO state of the local transmission buffer 233 so that the FIFO does not become full.

Next, the PCI board 200 divides the first data into N bit units and M pieces, and performs a third step S30 of transmitting the divided second data of M N bit units to the communication board 300. .

For example, when the first data is 64 bits, the first data may be divided into four pieces of data in 16 bit units and transmitted to the communication board 300.

In this case, the PCI board 200 converts the second data from parallel data to serial data and transmits the data, and the communication board 300 converts serial data into parallel data and receives the data. can do.

Next, when the communication board 300 receives the M second data as described above, the fourth step of combining and storing the first data according to the storage capacity of the embedded reception buffer 333 of the communication board 300 Perform (S40). That is, four data of 16 bit units are made into 64 bit data and stored in the embedded reception buffer 333.

Next, the communication board 300 performs a fifth step S50 of controlling the embedded system 400 by transmitting first data as third data suitable for the embedded system 400. In this case, the third data may be data corresponding to 16 bit SRAM.

On the other hand, contrary to the embodiment described above, when the data is input from the embedded system 400, it may be transmitted to the PC 100 through the communication board 300 and the PCI board 200.

More specifically, after the fifth step S50, the communication board 300 receives third data transmitted from the embedded system 400 and stores the third data as first data according to a storage capacity of the embedded transmission buffer 337. Perform step 6 (S60).

That is, the communication board 300 stores the data transmitted from the embedded system 400 in the embedded transmission buffer 337 in consideration of the FIFO state of the embedded transmission buffer 337 so that the FIFO does not become full.

Next, the communication board 300 divides the first data into N bit units and M pieces, and performs a seventh step S70 of transmitting the divided second data of M N bit units to the PCI board 200. . For example, when the first data is 64 bits, the first data may be divided into four pieces of data in 16 bit units and transmitted to the PCI board 200.

Next, the PCI board 200 receives the M second data and performs an eighth step S80 of combining and storing the M second data into first data according to the storage capacity of the local reception buffer 239 of the PCI board 200. do.

The PCI board 200 performs a ninth step S90 of transmitting the first data to the PC 100.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications, changes, etc. fall within the scope of the claims Should be seen.

1 is a block diagram showing a high speed serial communication conversion device between a PC and an embedded system according to the present invention.

2 is a block diagram showing the configuration of a PCI board and a communication board according to an embodiment of the present invention.

3 is a block diagram showing a detailed configuration of a PCI board according to an embodiment of the present invention.

4 is a block diagram showing a detailed configuration of a communication board according to an embodiment of the present invention.

5 is a flowchart illustrating a high speed serial communication conversion method between a PC and an embedded system according to an exemplary embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

100: PC 200: PCI board

210: PCI control device 211: local bus interface

213: control module 215: PCI interface

230: first FPGA 231: local control module

233: local transmission buffer 235: local transmission module

237 local receiving module 239 local receiving buffer

250: first interface 300: communication board

310: second interface 330: second FPGA

331: embedded receiving module 0333: embedded receiving buffer

337: embedded transmission buffer 339: embedded transmission module

350: external connector 400: embedded system

500: cable

Claims (20)

In the high-speed serial communication converter between the PC and the embedded system comprising a PC, a PCI board connected to the PCI slot of the PC, a communication board connected via the cable and the PCI board, The PCI board is a PCI control device that receives data from the PC and transmits according to the PCI bus communication standard, local to receive the data from the PCI control device and store the first data according to the storage capacity of the local transmission buffer A first FPGA comprising a control module and a local transmission module for dividing the first data stored in the local transmission buffer into N bit units and M units and transmitting the divided second data of M N bit units to a first interface; A first interface, which is a first SerDes device for converting and transmitting second data from parallel data to serial data to interface the first FPGA with the communication board, The communication board is a second SerDes device for receiving and converting the serial data into parallel data to interface the PCI board and the second FPGA, the second interface, the M from the second interface An embedded receiving module configured to receive second data and to combine and store the first data according to a storage capacity of an embedded receiving buffer; and to transmit the first data stored in the embedded receiving buffer as third data suitable for the embedded system. A high speed serial communication converter between a PC and an embedded system, comprising: a second FPGA including an embedded control module for controlling the embedded system; and an external connector connecting the second FPGA and the embedded system. And N is a natural number). The method of claim 1, The embedded control module is configured to receive the third data transmitted from the embedded system through the external connector, combine and store the first data according to a storage capacity of an embedded transmission buffer. The second FPGA may further include an embedded transmission module configured to divide the first data stored in the embedded transmission buffer into N bits and M units, and to transmit the divided second data in M N bit units to the second interface. Is configured to include, The first FPGA further comprises a local receiving module configured to receive the M pieces of second data through the first interface and to combine and store the first data according to a storage capacity of a local receiving buffer. The local control module is a high-speed serial communication converter between the PC and the embedded system, characterized in that for transmitting the first data from the local receiving buffer to the PC via the PCI control device. delete The method of claim 2, wherein the first interface, 18 bit data communication, D15 to D0 bits for the second data, D17 bits for transmission information regarding the transmission of the M N-bit data, and D16 bits for the First In Forst Out (FIFO) state of the local reception buffer. High speed serial communication converter between a PC and an embedded system, characterized in that consisting of data. The method of claim 1, wherein the PCI control device, A high speed serial communication converter between a PC and an embedded system, characterized in that it communicates with the PCI bus in any one of Target Single mode and Burst Direct Memory Access (DMA) mode. The method of claim 1, wherein the PCI control device, And a local bus interface for interfacing with a local bus communicating with the CPU of the PC, a control module for controlling the PCI control device, and a PCI interface for transmitting the data through the PCI bus. High speed serial communication converter between systems. The method of claim 1, wherein the third data, High-speed serial communication converter between a PC and an embedded system, characterized in that the data conforms to 16 bit SRAM. The method of claim 1, wherein the local transmit buffer and the embedded receive buffer, High speed serial communication converter between PC and embedded system, characterized by 64K x 16bit high speed SRAM. The method of claim 2, wherein the local receive buffer and the embedded transmit buffer, High speed serial communication converter between PC and embedded system, characterized by 64K x 16bit high speed SRAM. The method of claim 1, wherein the PCI board, And a first display configured to display an operation state of the PCI board or a connection state of the PCI board and the communication board. The method of claim 10, wherein the first display unit, In the operation state of the PCI board, Reset is displayed as "0", Data from the PCI board to the communication board (Write) is "2" and Data from the communication board to the PCI board (Read) is displayed as "3". High speed serial communication converter between the PC and the embedded system, characterized in that. The method of claim 1, wherein the communication board, And a second display unit configured to display an operating state of the communication board or a connection state of the communication board and the PCI board. The method of claim 1, wherein the cable, High speed serial communication converter between a PC and an embedded system, characterized in that the STP cable. In the high-speed serial communication conversion method between the PC and the embedded system comprising a PC, a PCI board connected to the PCI slot of the PC, a communication board connected via the cable and the PCI board, A first step of the PCI board receiving data from the PC and transmitting the data in any one of a target single transfer mode and a burst direct memory access (DMA) mode; A second step of the PCI board storing the data as first data according to a storage capacity of a local transmit buffer of the PCI board; A third step of the PCI board dividing the first data into N bit units and M pieces and transmitting the divided second data of M N bit units to the communication board; A fourth step in which the communication board receives the M second data and combines and stores the first data according to a storage capacity of an embedded reception buffer of the communication board; And A fifth step of controlling the embedded system by transmitting the first data to third data suitable for the embedded system by the communication board; and performing high speed serial communication conversion method between the PC and the embedded system. N is a natural number). The method of claim 14, wherein after the fifth step, A sixth step of receiving, by the communication board, the third data received from the embedded system and storing the third data as the first data according to a storage capacity of an embedded transmission buffer; A seventh step of the communication board dividing the first data into N bits and M units and transmitting the divided second M data into M PCI bits to the PCI board; An eighth step of receiving, by the PCI board, the M pieces of second data and combining the second data into the first data according to a storage capacity of a local reception buffer of the PCI board; And The PCI board performs a ninth step of transmitting the first data to the PC. High speed serial communication conversion method between a PC and an embedded system. The method of claim 14, In the third step, the PCI board converts the second data from parallel data to serial data, and transmits the same. In the fourth step, the communication board converts the serial data into parallel data and receives the high speed serial communication conversion method between the PC and the embedded system. delete The method of claim 14, wherein the third data, High speed serial communication conversion method between a PC and an embedded system, characterized in that the data conforms to 16 bit SRAM. The method of claim 14, wherein the local transmit buffer and the embedded receive buffer, High speed serial communication conversion method between PC and embedded system, characterized by 64K x 16bit high speed SRAM. The method of claim 15, wherein the local receive buffer and the embedded transmit buffer, High speed serial communication conversion method between PC and embedded system, characterized by 64K x 16bit high speed SRAM.

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