KR100925136B1 - FORMATION OF PATTERNED SILICON-ON-INSULATORSOI/SILICON-ON-NOTHINGSON COMPOSITE STRUCTURE BY POROUS Si ENGINEERING - Google Patents

Abstract

Patterned SOI / SON composite structures and methods for forming the same are provided. In an SOI / SON composite structure, the patterned SOI / SON structure is inserted between the Si overlayer and the semiconductor substrate. The method of forming the patterned SOI / SON composite structure includes a shared processing step in which the SOI and SON structures are formed together. The invention also provides a method of forming a composite structure comprising only a buried void plane, as well as a method of forming a composite structure comprising a buried conductive / SON structure.

Buried Insulation Area, Void Plane, Si Overlayer

Description

FORMATION OF PATTERNED SILICON-ON-INSULATOR (SOI) / SILICON-ON-NOTHING (SON) COMPOSITE STRUCTURE BY POROUS Si ENGINEERING}

The present invention relates to a semiconductor composite structure, and more particularly to a silicon-on-insulator (SOI) structure in which a thin silicon layer, i.e., an Si over-layer, is separated from a substrate by an insulating region. The Si overlayer relates to a semiconductor composite structure comprising a combination of silicon-on-nothing (SON) structures separated from the substrate by an expanded void plane or air gap. The present invention also relates to a method of forming the semiconductor composite structure described above.

In microelectronic integrated circuit (IC) fabrication, SOI and SON wafers are used in certain ICs where active device regions need to be separated and isolated from underlying semiconductor substrates. If a relatively small active device area in physical dimension and volume comes into contact with a very large substrate, various adverse effects on device and circuit performance are observed. For example, an increase in leakage current and junction capacity, a decrease in resistance to radiation and heat effects, an increase in short-channel influences, and an increase in susceptibility to electrical breakdown called latch-up. Adverse effects such as can be observed. All these adverse effects translate into loss of device and circuit performance and increased power consumption.

SOI and SON devices and circuits are inherently unaffected above because of the unique semiconductor material structures on which these devices and circuits are installed, and are therefore in demand.

 In SOI, a continuous layer of buried insulating layer such as oxide is formed between the Si overlayer and the semiconductor substrate. The buried insulating material electrically isolates the Si overlayer from the substrate. A proven method called bond-and-etch-back SOI (BESOI) is a thin overlayer by oxidizing the surfaces of two starting semiconductor wafers, bonding the two wafers on the oxidized surface and etching one wafer from the backside. And etched wafers to provide a smooth surface suitable for device fabrication. Since the wafer surface is oxidized to the desired depth before bonding, very good control of buried oxide formation can be maintained. Thus, the resulting buried oxide is very uniform and can have almost any desired thickness. However, the difficulty in achieving a thin and uniform Si overlayer through the trapping and etch-back process of impurities in the bonded interface is an important weakness of the prior art BESOI process.

In another proven method called SIMO (separation by ion implantation of oxygen), oxygen ions are implanted directly on the wafer surface and then implanted oxygen ions react with Si atoms during hot annealing to form a buried oxide layer. The depth, thickness and uniformity of the buried oxide layer mainly depend on the dose and energy of the injected oxygen and the subsequent annealing conditions. In general, the SIMOX process provides a uniform, high quality buried oxide and Si overlayer.

In another proven method called FIPOS (full isolation by porous oxidized silicon), the patterned Si surface is anodized in an HF-containing solution to form porous Si that completely encloses an unanodized Si island. Form. In this method, the Si islands are patterned and converted into anodizing forms prior to insertion into the solution. Porous Si oxidizes faster than bulk Si by a very increased surface area, so during thermal oxidation the porous Si completely surrounds and isolates the Si islands. This conventional method is considered a very inexpensive way of forming SOI. In general, however, it is difficult to form a thin high density thermal oxide by this conventional method. In addition, when pressure is applied by the surrounding oxidized porous Si, the Si islands may have displacement and stack defects.

In SON, an expanded void plane or air gap is formed below the Si overlayer. However, when the void plane extends over the entire diameter of the semiconductor wafer, the buried void plane is inevitably limited in the lateral dimension because the Si overlayer and the underlying semiconductor substrate are separated. Typically, buried void planes of limited size are formed at selected locations on the wafer.

In a conventional proven method called ESS (empty space in silicon), long etch-pits are formed on the wafer surface, and by annealing in a hydrogen atmosphere at elevated temperatures leading to surface movement of Si atoms Convert to a buried void plane. The area and thickness of the buried void plane and the Si overlayer thereon are determined by the number and pitch of etch pits as well as the width and depth of each of the etch pits.

In another proven method, a SiGe layer is deposited on the semiconductor wafer surface by selective epitaxial growth, a Si bridge is formed on the SiGe layer, and the SiGe layer is selectively etched leaving an air gap. In this conventional method, the entire procedure can be incorporated as part of the device fabrication process.

Since known conventional methods for producing SOI and SON composites are different and SOI includes buried oxide and SON forms voids, joining two composite structures onto a single semiconductor wafer has not been performed. For low power device isolation, the dielectric constant of typical buried oxides, such as SiO ₂ , is about 3.9, while SON composites are very good in that the dielectric constant of voids is close to 1, the lowest dielectric constant.

However, in addition to device isolation, SON can be used as a substrate for lattice-mismatched epitaxial layers such as SiGe and GaAs, while the buried isolation region, if properly patterned, provides additional functionality as a backgate dielectric. Can be done. Thus, SOI / SON composite combining not only improves microelectronic applications that use SOI and SON separately, but can also be used in many new applications that are not currently known or realized.

Summary of the Invention

The present invention provides a method of forming a patterned SOI / SON composite structure on a single semiconductor wafer by a sharing process. An important feature of the advanced sharing process is the formation of porous Si layers by electrolytic anodization in HF containing solutions. In some conventional SOI methods, porous Si is used as a sacrificial etch stop, split plane, field oxide region or full isolation oxide region. However, in the present invention, porous Si is used to form a buried insulation / void combination.

It is a primary object of the present invention to provide a semiconductor composite structure comprising a patterned SOI / SON structure. Composite structures may include single or multiple levels of SOI and SON structures. In the present invention, the patterned SOI / SON structures in a given layer are adjacent to each other in an alternating pattern of SOI and SON.

Another object of the present invention is to provide a method for producing the SOI / SON containing composite.

It is yet another object of the present invention to provide a method of making an SOI / SON containing composite comprising a processing step that is almost shared by SOI and SON structures.

Another object of the present invention is to allow the SOI / SON structural pattern to be formed in any desired shape and size without being fixed.

According to one aspect of the present invention, a semiconductor composite structure including a combination of a patterned SOI and a SON structure is provided. In particular, advanced semiconductor composite structures include semiconductor substrates; At least one layer adjacent to each other and having a patterned buried isolation region and a void plane disposed on the semiconductor substrate; And an Si over-layer having a predetermined thickness disposed on top of the one or more layers having the patterned buried isolation region and void plane.

In one embodiment of the present invention, the buried insulating region of the advanced semiconductor composite structure is replaced with a buried conductive region. In another embodiment of the present invention, the progressive semiconductor composite structure includes only the void plane. In another embodiment of the present invention, an advanced semiconductor composite structure includes a buried insulated region, a buried conductive region and a void plane.

In another aspect of the present invention, a method of forming the semiconductor composite structure described above is provided. In particular, the method includes the steps of (a) forming a layer of porous Si in the surface region of the semiconductor wafer; (b) forming an epi-Si layer on the layer of porous Si, wherein an interface exists between the epi-Si layer and the layer of porous Si; (c) selectively implanting ions into a predetermined region of the wafer to form implant regions in or near the interface; And (d) annealing the wafer at an elevated temperature that transforms the implanted region into a buried insulating region by reaction with a peripheral layer of porous Si and transforming the porous Si not implanted by pore adhesion into a buried plane of voids. Include.

In some embodiments of the present invention, multiple layers of buried insulation / void planes stacked vertically are formed, and steps (a) to (c) are repeated any number of times before performing annealing step (d).

According to the invention, a porous Si layer is formed by an electrolyte anodization treatment carried out in an HF-containing solution. In the HF anodic oxidation treatment, the porosity of the formed porous Si depends on the current and voltage used, the HF concentration and the doping type and concentration of the semiconductor wafer. The thickness of the porous Si layer depends on the time of the anodization process.

A short time annealing in hydrogen atmosphere at elevated temperature is employed, if necessary, after step (a) to remove opening pores on the surface of the porous Si layer. In another embodiment, selective hydrogen annealing is also performed after the annealing step (d).

In some embodiments, a patterned mask of silicon dioxide, silicon nitride, photoresist, or a combination thereof may be employed to selectively form implant regions in the wafer. In this embodiment, the patterned mask has a thickness sufficient to prevent ions from being implanted in the area of the structure in which the void plane is to be formed.

 In another method of the invention, the implanted ions may form a buried conductive region upon annealing. In this embodiment, metal ions are implanted and the buried conductive region comprises metal silicide.

In another embodiment of the present invention, a composite structure is provided that includes only a buried void plane. This method of the invention comprises the steps of: (i) forming a patterned mask of an HF-resistive photoresist, ie, photoresist, on the semiconductor wafer, the patterned mask having one or more openings that expose portions of the semiconductor wafer; -; (ii) forming porous Si in the surface region of the exposed portion of the semiconductor wafer; (iii) removing the patterned mask; (iv) forming epi Si on the wafer comprising porous Si; And (v) annealing the wafer at an elevated temperature that transforms the porous Si into a buried void plane.

In another method of the present invention, a semiconductor composite structure comprising side-by-side insulator / void plane structures, side-by-side conductor / void plane structures, and buried layers of void plane structures, performs a final annealing step causing the above-described deformation. Prior to repeating steps (a) to (c) and steps (i) to (iv) any number of times.

1 is a diagram (section view) illustrating an advanced patterned SOI / SON composite structure of the present invention. A single layer of patterned SOI and SON is shown.

2 is a diagram (section view) showing an advanced patterned SOI / SON composite structure of the present invention. Multiple layers of patterned SOI and SON are shown.

3A-3D are diagrams (sectional views) showing the basic processing steps of the present invention used to form the structure shown in FIG. In these figures, the processing steps up to the annealing step are included but not included.

4A to 4D are diagrams (sectional views) showing another method of the present invention.

The present invention providing a patterned SOI / SON composite structure and a method of manufacturing the structure will be described in detail with reference to the drawings accompanying the present application. In the accompanying drawings, the same reference numbers are used for the same and corresponding elements.

Due to differences in prior art process features, integration of SOI and SON onto a single semiconductor wafer is not common. It is an advantage of the present invention to arrange SOI and SON structures side by side in any desired pattern on a single semiconductor wafer in a shared manufacturing process. The term "semiconductor wafer" is used to refer to a wafer comprising semiconductor materials such as Si, SiGe, SiC, SiGeC, GaAs, GeAs, InAs and InP and III / V compound semiconductors. The term "semiconductor wafer" may also include a silicon-on-insulator substrate.

1 is a cross-sectional view of a typical patterned SOI / SON composite structure that may be prepared using one of the methods of the present invention. The patterned SOI / SON composite structure shown in FIG. 1 includes a single layer of buried planes 26 and buried planes 26 interposed between the Si overlayer 30 and the semiconductor wafer or substrate 10. The buried insulation region 26 is disposed alongside the void plane 27. Thus, advanced composite structures include layers of buried isolation regions (SOI) and void planes (SON) alternating within a single semiconductor substrate.

The thicknesses of the various layers of the advanced patterned SOI / SON composite structure may vary depending on the process conditions employed to fabricate the structure. In general, the buried isolation region and the layer of the void plane have a thickness of about 5 nm to about 1 μm, more preferably about 5 to about 200 nm. The thickness of the layer of the buried insulating region and the void plane depends on the requirements of the device, and in the present invention, it can be controlled by adjusting the dose amount of implanted ions and the vertical depth of the porous Si layer formed during the HF anodic oxidation treatment.

Si overlayer 30 has a single crystal structure, and the thickness of layer 30 generally has a thickness of about 2 nm to about 1 μm, more preferably about 2 to about 100 nm. The thickness of the Si overlayer depends on the device requirements and, in the present invention, can be controlled by Si epi deposition and Si consumption during thermal annealing. The thickness of the substrate 10 is not critical to the present invention. The layers of patterned SOI / SON structures are substantially uniform and the various SOI / SON structures are of high quality.

In some embodiments of the present invention, buried isolation region 26 is replaced with a buried conductive region. In this embodiment, a patterned buried conductive / SON composite structure is provided. This composite structure is the structure shown in FIG. 1 above or FIG. 2 below, except that the buried insulating region 26 is replaced with a buried conductive material.

2 shows a patterned SOI / SON composite structure of the present invention comprising multiple layers of buried isolation regions 26 and void planes 27, each of which can be individually patterned and differs from the top and bottom layers. Can be. The bottom layer of the structure is the substrate 10 and the top layer of the shown structure is the Si overlayer 30 '. While the present invention shows a patterned SOI / SON composite structure each comprising one or two layers of patterned buried isolation regions and void planes, the present invention is directed to forming such a plurality of patterned SOI / SON layers in a single composite structure. It may include.

In FIG. 2, the two buried SOI / SON layers 26 and 27 need not be aligned and may not be designed identically. However, for clarity, FIG. 2 shows two buried SOI / SON layers having the same design dimensions and aligned. In addition to the examples given, the present invention includes a misaligned SOI / SON layer in which each buried region has its own design dimensions.

The advanced processing steps used to fabricate the patterned SOI / SON composite structure shown in FIGS. 1 and 2 are described in detail below. First, reference is made to the structure shown in FIG. 3A. In particular, the structure shown in FIG. 3A includes a semiconductor wafer or substrate 10 having a layer of porous Si 12 in the surface area. The terms "wafer" and "substrate" are used interchangeably in this application. Semiconductor wafers are generally Si-containing semiconductor materials having any desired size. The semiconductor wafer is preferably, but not necessarily, doped with a p-type doping atom. If a boron doped p-type wafer is employed, the dopant concentration of the wafer is generally about 1E15 to about 1E19 atoms / cm 3, more preferably about 5E17 to 1E19 atoms / cm 3.

Porous Si layer 12 is a thin layer having a thickness of about 100 nm to about 2 μm, more preferably about 500 nm to 1 μm. The porosity of the porous Si layer 12 is about 5 to about 70%, preferably about 10 to about 40%. The porous Si layer is generally formed at or below the upper surface area of the semiconductor wafer 10.

The porous Si layer 12 is formed using an anodization technique performed in an HF containing solution. The term "HF containing solution" refers to a mixture of HF and electrolytes such as hydrocarbons, alcohols and water. Preferred electrolytes employed in the present invention are aggregated HF (49 wt% HF + 51 wt% H ₂ O). The anodization process is performed in an HF containing bath in which the wafer is immersed and positively biased. The bath also includes a negatively biased electrode.

HF anodic oxidation is a known technique for forming porous Si and other porous semiconductors such as, for example, Ge and GaAs. By appropriate experiments, including varying HF concentrations, current and voltage levels, doping types (n and p type) of the wafers and dopant concentrations and anodization treatment times, methods of anodizing treatment parameters suitable for a particular desired porous layer structure can be obtained. You can get it. In the present invention, any known anodizing apparatus may be employed to form the porous Si layer, so long as it is designed to allow a uniform flow of current throughout the surface area of the wafer.

According to the present invention, in order to achieve the porosity described above, the HF anodic oxidation treatment is carried out in an HF concentration of about 25 to about 50 wt% in 100% electrolyte, more preferably in an HF concentration of about 40 to about 50% in 100% electrolyte. Is performed using. Since the anodic oxidation process is driven by the current flow, the current is usually set constant at the desired density value during the anodic oxidation process. The constant current density employed during the anodic oxidation process is about 0.1 to about 20 mA / cm 2, more preferably about 1 to about 2 mA / cm 2. Depending on the type and doping density of the Si wafer, the voltage required to drive the current density during the anodic oxidation process is generally about 0.1 to about 10 volts, more preferably 0.5 to 5 volts. The anodic oxidation treatment is generally performed at about room temperature for a period of about 30 seconds to about 10 minutes, more preferably for a period of about 1 to about 5 minutes.

After the anodic oxidation treatment, the structure containing the porous Si layer can be selectively annealed in a hydrogen atmosphere at elevated temperature to substantially remove opening pores on the porous Si surface. In particular, the selective hydrogen annealing is performed at a temperature of about 800 ° C. to about 1100 ° C. for a period of about 10 minutes to about 2 hours. In particular, the selective hydrogen annealing is performed at about 850 ° C. to 900 ° C. for a period of about 30 minutes to about 1 hour. Hydrogen annealing is usually carried out using pure 100% hydrogen. However, if necessary, hydrogen may be mixed with an inert gas such as He, Ar, or Xe or a mixture thereof. The amount of hydrogen in the gas mixture is generally about 50 to about 100%. The pressure of hydrogen used during this optional pre-annealing step is generally about 10 to about 760 Torr.

Hydrogen annealing is known to induce surface movement of Si atoms to substantially remove opening surface pores. However, at elevated temperatures, the pores in the bulk coalesce into larger pores to minimize surface energy. Therefore, when a hydrogen annealing process is used in the present invention, the hydrogen annealing process should not be performed for a long time at a temperature that is too high.

Next, as shown in FIG. 3B, an epi-Si layer 14 is formed on the porous Si layer 12 using a deposition method capable of growing a low defect epi-Si layer. . Examples of suitable deposition methods that may be employed in the present invention include, but are not limited to, chemical vapor deposition (CVD), plasma assisted CVD, and molecular beam epitaxial deposition. In general, the thickness of the epi-Si layer having a single crystal structure is about 100 nm to about 1 μm, more preferably about 400 to about 600 nm. An interface 13 is present between the porous Si layer and the epi-Si layer 14.

In one embodiment of the present invention, conventional masking materials of silicon oxide, silicon nitride, photoresist or any combination thereof may be epitaxially utilizing conventional deposition processes such as low temperature CVD and spin-on coating. Can be applied to the top surface of the -Si layer 14, and then conventional lithography is used in the patterned mask 18 with one or more openings 20 exposing the bottom surface of the epi-Si layer 14. do. The resulting structure comprising a patterned mask and one or more openings is shown, for example, in FIG. 3C. In this step of the invention a square cross-sectional pattern is formed. In the case of silicon dioxide and silicon nitride, the lithography step includes depositing the photoresist, exposing the photoresist in a pattern of radiation, and developing the exposed photoresist using a conventional resist developer.

The thickness of the patterned mask can vary as long as it can prevent (ie, block) implantation of ions into the blocked area during subsequent ion implantation steps. Generally, the thickness of the mask is at least about 500 nm, more preferably from about 1 to about 3 μm.

Next, as shown in FIG. 3D, oxygen ions 22 are uniformly implanted through the opening 20 into the structure to form an oxygen implantation region 24 in and near the interface 13. In particular, the oxygen injection region is formed to be the peak concentration of the implant at and slightly below the epi-Si / porous Si interface. In the region where the patterned mask is present, the implanted oxygen ions stop within the patterned mask and do not penetrate into the underlying epi-Si layer. Conversely, implanted oxygen ions penetrate into the structure in the region where no mask is present.

Oxygen implantation may be formed using any conventional ion implantation apparatus and any conventional ion implantation conditions may be employed in the present invention. For example, oxygen ion implantation may include an oxygen ion dose of about 1E16 to about 2E18 atoms / cm 2, an implantation energy of about 50 KeV to about 10 MeV, an ion beam current density of about 0.05 to about 500 mA / cm 2, and about 480 ° C. To about 650 ° C. More preferably, the oxygen ion implantation comprises an oxygen ion dose of about 5E16 to about 2E17 atoms / cm 2, an implantation energy of about 150 to about 300 KeV, an ion beam current density of about 1.0 to about 10 mA / cm 2, and about 550 ° C. to It can be carried out using an injection temperature of about 600 ℃. Ion implantation conditions other than those described above may also be considered. After this hot injection step, room temperature injections described in US Pat. Nos. 5,930,643, 6,043,166 and 6,090,689 described herein are performed.

Oxygen ions may be implanted in a single step or multiple ion implantation steps may be employed. The injection can be a continuous injection or a pulse injection. In another embodiment of the present invention, the oxygen ions are replaced with nitrogen ions or combinations of oxygen and nitrogen ions that can form a buried insulating region in the structure when performing a subsequent high temperature annealing process. Implantation of nitrogen ions is performed using any ion implantation process including implant conditions well known to those skilled in the art.

In another embodiment of the present invention, the implanted ions are metal ions such as refractory metals having a eutectic temperature higher than about 1300 ° C. when alloyed with Mo, Ta, W and Si. These metal ions may form a buried conductive region when a subsequent high temperature annealing process is described in more detail below. In this embodiment, a layer including alternating buried conductive regions and a void plane can be formed.

After the implantation step, the patterned mask is generally removed from the surface of the structure using conventional stripping processes well known to those skilled in the art. In another embodiment, the patterned mask is not removed until after the annealing process is performed. However, in the present invention, the patterned mask is preferably removed before the annealing step.

Annealing is performed, for example, to provide the structure shown in FIG. 1. In particular, the annealing step employed at this point in the present invention is capable of transforming the injected oxygen region 24 into a buried oxide region 26 while deforming the region not containing oxygen ions into the void plane 26. High temperature annealing. The layer over regions 26 and 27 is Si overlayer 30. If ions other than oxygen are employed, buried insulating regions are used instead of buried oxide regions. When conductive ions are employed, buried conductive regions are formed instead of buried oxide regions.

In this buried oxide / void formation, porous Si is consumed and the epi-Si layer can be thinned by surface oxidation, resulting in a much thinner Si overlayer (which is much thinner than the original epi-Si layer when the surface oxide is removed). 30) is obtained. In some embodiments, although not shown, surface oxides remain on the composite structure.

According to the invention, buried insulating regions (as well as buried conductive regions) are formed by thermal interaction between implanted ions and porous Si. The void plane is formed by pore coalescence. The term "void plane" refers to a gap between the Si overlayer and the substrate in which nothing exists except air.

The high temperature annealing is performed at a temperature below about 1300 ° C. and below the Si melting point of 1415 ° C. for a period of at least about 2 hours. More preferably, the high temperature annealing step is performed at a temperature of about 1300 ° C. to about 1350 ° C. for a period of about 5 to about 10 hours. The high temperature annealing can be carried out in 100% pure oxygen, inert gas or N ₂ or inert gas and N ₂ mixed oxygen, inert gas or N ₂ or mixtures thereof, or in vacuum. If an oxygen containing mixture is employed, oxygen is generally present at a concentration of about 0.25 to about 99.75%, more preferably at a concentration of about 2 to about 25%. The remainder of the mixture up to 100% is inert gas, N ₂ , or inert gas and N ₂ .

The annealing step can be formed using a continuous heating scheme in which a single ramp-up rate and cool down rate are employed. Alternatively, the high temperature annealing step can include various rising rates, soaks and cooling rates.

During the high temperature annealing step, dopants present in the substrate 10 may diffuse from the substrate 10 into the Si overlayer 30. If the level of doping concentration of the Si overlayer 30 is too high, for a given device application, the structure shown in FIG. 1 is subsequently hydrogen annealed. Subsequent hydrogen annealing includes the same or other conditions as the selective hydrogen annealing described above. Preferred subsequent hydrogen annealing that may be employed in the present invention is an annealing of 0.25 to 3 hours in a low pressure (80 Torr or less) hydrogen atmosphere at 1100 to 1150 ° C.

In some embodiments of the present invention, the processing steps of FIGS. 3A-3D above may be repeated before performing high temperature annealing to provide the structure shown, for example, in FIG. 2.

In another embodiment of the present invention, the void planes provided above may be filled with gas, liquid or solid using processing steps well known to those skilled in the art. The gas is a gas other than air.

In another embodiment of the present invention, applying the mask and patterning the mask can be eliminated. In this example, a selective ion implantation process may be used in which ions are implanted only in a predetermined area of the structure.

In another embodiment of the present invention, the HF anodic oxidation step is replaced by a process of forming gaps or voids instead of pores.

In another method of the present invention, only a buried void plane is formed in the semiconductor wafer. This method of the invention is shown in FIGS. 4A-4D.

4A shows the structure after the patterned mask of HF-resistive photoresist 18 'is formed on the surface of the semiconductor wafer 10. The patterned photoresist is formed using the processing steps described above. As shown, the patterned photoresist 18 'has one or more openings 20 that expose portions of the semiconductor wafer.

Next, as shown in FIG. 4B, a porous Si region 12 is formed in the exposed portion of the semiconductor wafer using the HF anodization process described above, after which the patterned photoresist is removed and the porous Si is removed. Epi-Si 14 is formed on the entire structure including the porous Si region 12 while forming the interface 13 with regions (see FIG. 4C). Epi-S is formed using one of the deposition processes described above.

Thereafter, the structure shown in FIG. 4C is annealed at elevated temperature to deform the porous Si into buried plane 27 by pore coalescence. High temperature annealing includes the conditions described above. The resulting structure is shown, for example, in FIG. 4D. The void plane may be filled with gas, liquid or solid as described above. In addition, multiple layers of the void plane can be formed by repeating the processing steps shown in FIGS. 4A-4C before annealing.

In another embodiment of the invention, prior to performing the high temperature annealing, the processing steps of FIGS. 3A-3D and 4A-4C are repeated any number of times to form a semiconductor composite structure comprising buried insulating regions, conductive regions and void planes. Can provide.

If possible, the buried insulating area, the conductive area and the void plane of FIG. 2 may be connected to the surface and via each other via via holes. The via hole may be filled with an insulating material or a conductive material or may remain as a void. Methods and processing steps for forming the via holes and filling the via holes with insulating or conductive materials are apparent to those skilled in the art.

Although the present invention has been described with reference to the preferred embodiments, those skilled in the art will understand that various modifications are possible without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the above-described forms and details, and the present invention is within the spirit and scope of the accompanying drawings.

Claims (38)

Semiconductor substrates; At least one layer disposed next to each other and having a patterned buried conductive region and a void plane disposed on the semiconductor substrate; And A Si over-layer having a predetermined thickness disposed on top of the one or more layers having the patterned buried conductive region and the void plane Including, The buried conductive region comprises implanted refractory metal ions, And said Si overlayer has a single crystal structure. delete The semiconductor composite structure of claim 1, wherein the Si overlayer has a thickness of 2 nm to 1 μm. The semiconductor composite structure of claim 1, wherein the implanted refractory metal ions have a eutectic temperature higher than 1300 ° C. when alloyed with Si. delete delete delete delete delete delete delete The semiconductor composite structure of claim 1, further comprising a surface oxide disposed on the Si overlayer. The semiconductor composite structure of claim 1, wherein the implanted refractory metal ions are selected from the group consisting of Mo, Ta, and W. 3. As a method of forming a semiconductor composite structure, (a) forming a layer of porous Si in the surface region of the semiconductor wafer; (b) forming an epi-Si layer on the layer of porous Si, wherein an epi-Si layer is present between the epi-Si layer and the layer of porous Si. Forming; (c) selectively implanting ions into a predetermined region of the semiconductor wafer to form implant regions in or near the interface; And (d) the temperature at which the injection region is transformed into a buried isolation region by reaction with the periphery layer of porous Si and the non-injected porous Si is transformed into a buried plane of plane by a pore coalescene, and in an oxygen-containing environment Annealing the wafer Method for forming a semiconductor composite structure comprising a. 15. The method of claim 14, further comprising performing a hydrogen annealing step between the steps (a) and (b) to substantially remove the opening surface pores in the layer of porous Si. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete 15. The method of claim 14, further comprising repeating steps (a) through (c) any number of times before performing step (d). delete delete delete delete delete A method of forming a semiconductor composite structure including a buried silicon-on-nothing (SON) structure, (i) forming a patterned photoresist on a semiconductor wafer, wherein the patterned photoresist has one or more openings that expose portions of the semiconductor wafer; (ii) forming porous Si in the surface region of the exposed portion of the semiconductor wafer; (iii) removing the patterned photoresist; (iv) forming epi Si on the wafer comprising porous Si; And (v) annealing the wafer at an elevated temperature that transforms the porous Si into a buried void plane Method for forming a semiconductor composite structure comprising a. delete

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