KR100899526B1 - Apparatus and Method for Processing Packet using Multi-Processor - Google Patents

Abstract

A method and apparatus are disclosed for storing packets scheduled by a packet scheduler in a multiprocessor router in a plurality of queues and processing each stored packet by the processor. To this end, the multiprocessor-based packet processing method according to the present invention, the packet scheduler for distributing the input packet to each of the plurality of queues based on the session (session); And for the packets distributed to the plurality of queues, after one of the multiprocessors processes the packets of the first queue allocated to the plurality of queues, the second queue allocated to the other one of the multiprocessors. Processing the packet. Meanwhile, a multiprocessor-based packet processing apparatus includes a packet scheduler configured to distribute input packets based on a session, a plurality of queues configured to store the distributed packets, and the same number as the plurality of queues. In the case of processing the packets of the queue allocated to the individual processor comprises a plurality of processors each configured to process the packets of the queue assigned to the other processor. This ensures sequential delivery of packets belonging to a session in a multiprocessor router and maximizes the utilization of the processor.

Description

Apparatus and Method for Processing Packet using Multi-Processor

The present invention relates to an apparatus and method for processing a packet based on a multiprocessor, and more particularly, to an apparatus for distributing and storing a packet scheduled by a packet scheduler in a plurality of queues in a multiprocessor router and processing the stored packet by each processor; It is about a method.

In general, a multiprocessor router refers to a router having a plurality of packet processing processors for packet parallel processing. The plurality of processors respectively determine which port to send to by referring to the routing table for the incoming packet, and transmits the packet through the determined port, respectively. This will be described in more detail.

1 is a conceptual diagram illustrating a packet processing scheme in a general multiprocessor router.

As shown in FIG. 1, the multiprocessor router includes a packet scheduler 110 for distributing (distributing) input packets in a round-robin manner, and a plurality of queues 120a and 120b for storing the distributed packets, respectively. , ..., 120n and the packets stored in the queues 120a, 120b, ..., 120n allocated to the same number as the plurality of queues 120a, 120b, ..., 120n, respectively. It includes a plurality of processors (130a, 130b, ..., 130n) to process. Each processor 130a, 130b, ..., 130n includes a cache that stores information about the packet.

When a series of packets are input to the packet scheduler 110, the packet scheduler 110 distributes these input packets to multiple processors 130a, 130b, ..., 130n. This packet distribution policy is very important for the router's performance. Representative examples of the packet distribution policy include the round-robin method and the session-based method described above.

The round robin packet distribution policy is a policy for uniformly distributing packets to each of a plurality of processors, and may increase utilization of each processor 130a, 130b, ..., 130n. However, this approach does not guarantee sequential delivery for packets belonging to the same session. That is, when the multiprocessors 130a, 130b,..., 130n process packets received from the packet scheduler 110 through the queues 120a, 120b,. Because they can be different, packets belonging to the same session will not always be output in the order entered in the router first.

In particular, in the case of Transmission Control Protocol (TCP) sessions, guaranteeing the sequential delivery of packets is a very important factor in transmission efficiency. When a nonsequential delivery of packets occurs in a TCP session, TCP performs a series of recovery to recover them. Algorithm is performed, and thus the effective transmission efficiency of the router is lowered.

In addition, since the round robin method distributes and processes packets belonging to the same session to multiple processors, the same packet information may be duplicated and stored in each cache of the multiple processors. Accordingly, when the packet information is changed in one processor, the packet information stored in the caches of all other processors is invalidated. Therefore, since another processor must read back from the main memory in order to read the packet information in order to process the packet, there is a problem of inefficient use of the processor's cache.

Meanwhile, another packet distribution policy includes a method of distributing packets based on sessions. This means that all packets belonging to the same session are sent to the same processor for processing. In a typical case, a hash value based on a sender IP address and a receiver IP address of an input packet determines a processor to process these packets. In the session-based method, all packets belonging to the same session are processed by the same processor, thereby ensuring sequential packet delivery and efficiently using the processor cache. However, the session-based method has a problem in that the utilization of the processor is lower than that of the round robin method because the input packet is not evenly distributed to all processors.

The present invention was devised to solve the above problems, and an object of the present invention is to provide a packet processing apparatus and method for sequentially delivering packets belonging to the same session in a multiprocessor router and maximizing the utilization of each processor. To provide.

For this purpose, a multiprocessor-based packet processing method of one embodiment of the present invention comprises the steps of: (a) distributing a packet input by a packet scheduler to a plurality of queues based on a session; And (b) with respect to the packets distributed to the plurality of queues, one processor of the multiprocessor processes the packets of the first queue allocated to the first queue and then assigns to the other processor of the multiple processors. Processing a packet of two queues.

In addition, the multiprocessor-based packet processing method according to another aspect of the present invention, (a) checks the queue assigned to the one processor, if there is a processed packet and transmit the packet sequentially, if there is an unprocessed packet Processing the unprocessed packet; And (b) sequentially processing the queue allocated to the next processor when the queue does not have the unprocessed packet, and processing the unprocessed packet of the queue allocated to the next processor.

On the other hand, a multiprocessor-based packet processing apparatus of one embodiment of the present invention includes: a packet scheduler configured to distribute an input packet based on a session; A plurality of queues configured to respectively store the distributed packets; And a plurality of processors each configured to process the packets of the queues allocated to the different processors when the packets of the queues allocated to the individual processors are processed in the same number as the plurality of queues.

According to the present invention, the sequential delivery of packets belonging to the same session can be guaranteed in a multiprocessor router, and the utilization of each processor can be maximized.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings and preferred embodiments. For reference, in the following description, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention are omitted.

Prior to the detailed description, the term 'session' used in the present invention means that two devices (eg, host A and host B) having a TCP / IP networking function in the case of TCP (Trasmission Control Protocol) By using a 3-way handshaking process, a process of establishing a TCP connection, exchanging data, and releasing the connection through a termination procedure is performed. In case of User Datagram Protocol (UDP), there is no explicit session establishment / termination procedure. Therefore, when a new (ie, non-preset session) UDP packet is input, it is determined to start a new session. If no additional UDP packet is input, the session is determined to be terminated.

In such a session, a given session between two hosts A and B is divided into five parameters: host A's IP address, host A's port, host B's IP address, host B's port, and protocol (TCP or UDP). Separated by.

2 is a conceptual diagram illustrating a packet processing scheme in a multiprocessor router according to the present invention. For reference, the present invention may be implemented as a multiprocessor router or a part of a multiprocessor router.

As shown in FIG. 2, the multiprocessor-based packet processing apparatus according to the present invention includes a packet scheduler 210 for distributing (distributing) an input packet based on a session, and a plurality of queues for storing the distributed packets, respectively. 220a, 220b, ..., 220n and the same number to correspond to the plurality of queues 220a, 220b, ..., 220n. And a plurality of processors 230a, 230b, ..., 230n, each configured to process a packet. In this case, each of the processors 230a, 230b,..., 230n includes a cache for storing information about the packet.

The packet scheduler 210 distributes packets to a plurality of queues 220a, 220b, ..., 220n based on the above-described session. That is, the packet scheduler 210 causes all packets belonging to the same session to be stored in the same queues 220a, 220b, ..., 220n. To this end, the packet scheduler 210 stores the packet in a corresponding queue 220a, 220b, ..., 220n every time a packet is input. This will be described in more detail with reference to FIGS. 3 and 4.

3 is a diagram illustrating a configuration of a packet scheduler according to an embodiment of the present invention. As shown in FIG. 3, the packet scheduler 210 includes a hash function unit 211 and a modulo operation unit 212. .

The hash function unit 211 changes the input value of an arbitrary length into an output value having a fixed length. For example, when using the receiver IP address of a predetermined packet as an input value, The same value is output, but different values are output if different recipient IP addresses are input. Such a hash function 211 can be implemented by programming code.

The modulo operation unit 212 performs a modulo operation on the output value of the hash function unit 211 by the number of queues 220a, 220b, ..., 220n, and corresponds to the resultant queue 220a. , 220b, ..., 220n). For example, when the number of queues is four, the queues are distributed and stored in four queues according to the output value of the hash function unit 211. Since the output value of the hash function unit 211 outputs the same value when the receiver IP address is the same, and outputs different values when the receiver IP address is different, the modulo operation unit 212 is a packet corresponding to the same receiver IP address. Can be stored in the same queue. By doing this, packets corresponding to the same session can be sequentially delivered to the same queue.

The operation of the packet scheduler 210 configured as described above will be described. For reference, a detailed configuration or operation principle of the packet scheduler according to an embodiment of the present invention may refer to the above-described description of FIG. 3, and thus, redundant descriptions thereof will be omitted. Briefly explain.

First, when a packet is input, the hash function unit 211 uses the information of the packet as its input value (S410-S420). In this case, the packet information may include at least one of a sender IP address, a receiver IP address, a sender port number, a receiver port number, and a protocol.

Then, the modulo operation unit 212 performs a modulo operation on the output value of the hash function unit 211 by the number of queues 220a, 220b, ..., 220n, and the operation result is obtained. The input packet is stored in a designated queue (S430-S440). By doing so, the packet scheduler 210 can sequentially deliver packets belonging to the same session to the same queue.

On the other hand, when the processors 230a, 230b, ..., 230n have processed the packets of the queues 220a, 220b, ..., 220n allocated to them, the processors 230a, 230b, ..., 230n 220n) packets. To this end, the processor 230a, 230b, ..., 230n adds a completion flag field to a structure representing a packet stored in the queues 220a, 220b, ..., 220n, and when the processing for the packet is completed. The completion flag field is configured to indicate that the processing for the packet is completed. This processor is described in more detail with reference to FIGS. 5 and 6 as follows.

5 is a diagram showing the configuration of a processor according to an embodiment of the present invention, the packet processing apparatus according to the present invention is composed of a plurality of such processors.

As shown in FIG. 5, one processor 230a includes a packet checker 232, a packet transmitter 233, a packet processor 234, a completion flag processor 235, and a queue checker 236. It includes. In addition, the processor 230a includes a routing table 240 for packet processing. However, in some cases, the plurality of processors 230a, 230b,..., 230n may be implemented to share the routing table 240.

The packet inspecting unit 232 is configured to check whether there is a processed packet in the queue 220a or to check whether there is an unprocessed packet. The packet inspecting unit 232 may check a completion flag field to know a state of whether a corresponding packet has been processed. For example, the processor 230a determines that a packet exists in its queue 220a, and if it is determined that the packet processing is completed as a result of checking the completion flag field of the packet, the processor 230a determines that the packet has been processed. The packet is determined to be a packet, and the packet transmitter 233 or the packet processor 234 is operated according to the determination result. On the other hand, if the packet is present in the other queues 220b, ..., 220n, and it is indicated that the packet processing is completed as a result of checking the completion flag field of the packet, the processor 230a determines that the packet has been processed, and then The packet processor 234 inspects the packet, and if it is not displayed, determines that it is an unprocessed packet and operates the packet processor 234 to process the packet.

The packet transmitter 233 is configured to sequentially transmit the processed packets. At this time, when the packet of the queue 220a allocated to the processor 230a is completed, the packet transmitter 233 sequentially transmits the corresponding packets, but is allocated to the other processors 230b, ..., 230n. The packets of the queues 220b, ..., 220n do not operate even if they have been processed. This ensures sequential transmission of packets.

The packet processing unit 234 is configured to determine to which port to send an incoming packet with reference to the routing table 240.

When the packet processing unit 234 completes the processing of the predetermined packet, the completion flag processing unit 235 indicates that the packet is completed in the completion flag field of the corresponding packet. For example, such an indication may be indicated by writing '1' in the completion flag field described as '0'.

When the processor 230a moves to the queues 220b, ..., 220n allocated to the other processors 230b, ..., 230n, the queue checking unit 236 determines whether the queue is assigned to the queue. Check it. Through this check result, even if the processor 230a cyclically processes the packets of the queue, when the processor 230a returns to the queue allocated to itself, the processor 230a transmits the packet to the packets processed by itself or another processor 220b, ..., 220n. Through the unit 233 may be delivered to the destination.

The routing table 240 includes, for all destination information, the next router or receiver host information to go through to reach that destination. That is, the table is a table in which the band information of the destination network and the next router or receiver host address information are associated with each other, and the packet processing unit 234 is configured to select a preset route in the routing table 240.

The operation of the processor 230a configured as described above will be described. For reference, a detailed configuration or operation principle of the processor according to an exemplary embodiment of the present disclosure may refer to the description of FIG. 5 described above, and thus, redundant descriptions thereof will be omitted. Explain.

First, it is checked whether there is a packet already processed in the queue assigned to the self (S610-S620). As a result of the check, if there is a processed packet, the packets are sequentially transmitted (S630). However, if there is no processed packet, it is checked whether there is an unprocessed packet (S640).

As a result of the check in step S640, if there is an unprocessed packet, after processing the packet, the completion flag indicates that the processing is completed (S650). However, if there are no unprocessed packets, the queue allocated to another processor is checked (S660). For example, when the processor NP1 230a has processed all the packets of the queue 220a allocated thereto, the queue 220b allocated to the other processor NP2 230b is checked. At this time, when all the packets of the queue 220b allocated to this processor NP2 have been processed, the queue 220c allocated to another processor NP3 230c is checked. In the same process, when all the packets of the queue 220n allocated to the last processor NPn 230n are processed, the queue 220a allocated to the processor 220n is checked again.

Accordingly, after step S660, it is checked whether the currently moved queue is assigned to the queue (S670). As a result of the check in step S670, if the queue is not assigned to itself, the process returns to step S640 to check whether there are any unprocessed packets, and after processing the packets, mark the completion flag. Checks if there is a packet and sends the packet if there is a processed packet. This is because the other processor may have already processed the packet while the processor NP1 230a checks / queues a queue allocated to the other processor.

According to the operation of such a processor, packets belonging to one session are always guaranteed to be transmitted in the order stored in the queue. In addition, even if processors are crowded in one queue, all processors process packets evenly, thereby maximizing utilization of each processor.

5 is an exemplary diagram for describing an operation result of a processor according to an exemplary embodiment of the present invention, in which a processor includes NP1, NP2, NP3, and NP4, and a queue allocated to the processor NP1 is assigned to Q1 and processor NP2. The queue is Q2, the queue assigned to processor NP3 is Q3, the queue assigned to processor NP4 is Q4, packets d1, d2, d3 are queued to Q1, packets e1 to e16 to queue Q2, and packets f1 and f2 to queue Q3. , f3 assumes that the packet g1 is distributed to the queue Q4 by the packet scheduler.

Referring to FIG. 5, first, during the T1 time, each processor processes and transmits each packet in the order of FIG. 4. That is, the processor NP1 processes the packet d1, the processor NP2 processes the packet e1, the processor NP3 processes the packet f1, and the processor NP4 processes the packet g1.

During the T2 time, each processor processes each packet in a similar order as described above. That is, the processor NP1 processes the packet d2, the processor NP2 processes the packet e2, and the processor NP3 processes and transmits the packet f2. However, since the processor NP4 does not have a packet to process in the queue Q4 allocated thereto, another processor (for example, The queue Q1 assigned to NP1) is checked to process packet d3. In this embodiment, the queue Q1 assigned to the neighboring processor NP1 is checked, but the queue assigned to another processor NP2 or NP3 may be checked. In addition, the processing of the packets of the queue are mutually exclusive for each processor.

During time T3, processor NP2 processes packet e3 and processor NP3 processes and transmits packet f3. On the other hand, processor NP1 transmits the packet d3 processed by processor NP4 and examines the queue Q2 assigned to another processor (e.g., NP2) to process the corresponding packet (i.e., e4), and processor NP4 is assigned to processor NP1. Since there is no packet to process in the queue Q1, the queue Q2 assigned to another processor (e.g., NP2) is examined to process packet e5.

During the time T4, processor NP2 transmits packets e4 and e5 processed by processors NP1 and NP4, and processes and transmits packet e6. Processors NP1, NP3, and NP4, on the other hand, process packets e7, e8, and e9 of queue Q2 assigned to processor NP2, respectively.

During the time T5, the processor NP2 transmits the packets e7, e8 and e9 processed by the processors NP1 and NP4, and processes and transmits the packet e10. Processors NP1, NP3, and NP4, on the other hand, process packets e11, e12, and e13 of queue Q2 assigned to processor NP2, respectively.

In this manner, since all packets are processed during the T6 time, the processor NP1 according to the prior art processes the packets to be processed during the T3 time, the processor NP 2 for the T16 time, the processor NP3 for the T3 time, and the processor NP4 for the T1 time. According to the T6, all can be processed during the time.

On the other hand, the packet processing method and the operation of the processor according to the present invention can be written by a computer program. For example, codes and code segments constituting a program based on the algorithm disclosed in the above-described packet processing method and operation of a processor can be easily inferred by a computer programmer in the art. In addition, such a packet processing method and an operating program of a processor may be implemented by being stored in a computer-readable recording medium and being read and executed by a computer.

Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art to which the present invention pertains can implement the present invention in other specific forms without changing the technical spirit or essential features, The examples are to be understood in all respects as illustrative and not restrictive.

In addition, the scope of the present invention is specified by the appended claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention. Should be interpreted as

1 is a conceptual diagram illustrating a packet processing scheme in a general multiprocessor router.

2 is a conceptual diagram illustrating a packet processing scheme in a multiprocessor router according to an embodiment of the present invention.

3 is a flow chart showing the configuration of a packet scheduler according to an embodiment of the present invention.

4 is a flowchart illustrating operation of a packet scheduler according to an embodiment of the present invention.

5 is a diagram illustrating a configuration of a processor according to an embodiment of the present invention.

6 is a flowchart illustrating operation of a processor according to an embodiment of the present invention.

7 is an exemplary diagram for describing an operation result of a processor according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

210: packet scheduler

220a, 220b, ..., 220n: cue

230a, 230b, ..., 230n: processor

Claims (15)

Multiprocessor based packet processing method, (a) the packet scheduler distributing the input packet to a plurality of queues so that packets belonging to the same session are allocated to the same queue based on the session; And (b) a second packet allocated to the other one of the multiprocessors after the first one of the multiprocessors processes the packets of the first queue allocated to the plurality of queues for the packets distributed to the plurality of queues. Processing an unprocessed packet in a queue and including a processing completion flag in a corresponding structure. The method of claim 1, wherein step (a) comprises: The packet scheduler distributes the input packet to the plurality of queues by using a hash function. The method of claim 2, wherein the hash function, And at least one of a sender IP address, a receiver IP address, a sender port number, a receiver port number, and a protocol of the input packet as input values. The method of claim 2, wherein the hash function, Performing a modulo operation on the output value with the number of queues, and distributing the input packet to a queue designated by the modulo operation result. The method according to any one of claims 1 to 4, wherein step (b) comprises: (b-1) checking whether there is a processed packet in the first queue; (b-2) checking the unprocessed packet if there is no processed packet in the first queue as a result of the checking of the step (b-1); (b-3) checking the unprocessed packet in the first queue if there is no unprocessed packet in the first queue as a result of the checking of the step (b-2); And (b-4) processing the unprocessed packet of the second queue if there is an unprocessed packet in the second queue as a result of the checking in the step (b-2), and including the processing completion flag in the corresponding structure; Packet processing method characterized in that. The method of claim 5, wherein the step (b-2) And (b-1), if there is the processed packet, transmitting the packet sequentially. delete A multiprocessor based packet processing method in which packets belonging to the same session are allocated to the same queue, (a) checking a queue allocated to a first processor among multiple processors and sequentially transmitting the processed packets if there are processed packets, and processing the unprocessed packets if there are unprocessed packets; And (b) If there is no unprocessed packet in the queue assigned to the first processor, the queue allocated to the next processor is sequentially examined to process unprocessed packets of the queue assigned to the next processor, and a processing completion flag is assigned to the corresponding structure. Including the step of including the packet processing method. The method of claim 8, wherein the method is (c) the first processor sequentially checks the queue assigned to the next processor and then again checks the queue assigned to the first processor, and if there is a processed packet, transmits the processed packet, and the unprocessed packet is Processing the unprocessed packet, if any. The method of claim 9, wherein Packet processing method, characterized in that for repeating the steps (a) to (c). A multiprocessor based packet processing device, A packet scheduler for distributing input packets to a plurality of queues so that packets belonging to the same session are allocated to the same queue based on a session; A plurality of queues each storing the distributed packets; And Each processor is composed of individual processors corresponding to the plurality of queues. When all the packets of the queues allocated to the individual processors have been processed, the unprocessed packets of the queues allocated to the other processors are processed and the processing completion flag is included in the corresponding structure. Packet processing apparatus comprising a plurality of processors each configured to. delete The method of claim 11, wherein the packet scheduler, Use at least one of a sender IP address, a receiver IP address, a sender port number, a receiver port number, and a protocol of the input packet as an input value of a hash function, and modulate the number of queues with respect to an output value of the hash function. And perform an operation to distribute the input packet to a queue designated by the modulo operation result. The method of claim 11 or 13, wherein the individual processor, First checking means configured to check whether there is a processed packet in the queue assigned to the respective processor or whether there is an unprocessed packet; Packet processing means configured to refer to a routing table to determine which port to send the packet to; Transmitting means configured to sequentially transmit the processed packet; And And a display means for indicating that the processing of the packet is completed after processing the unprocessed packet if there is an unprocessed packet. The method of claim 14, wherein the individual processor, And second checking means for checking whether the plurality of queues are queues allocated to the individual processors.

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