KR100894803B1 - Semiconductor filter circuit and method - Google Patents

Abstract

The filter circuit 10 is formed on the semiconductor substrate 11 on which the trench 40 having the dielectric layer 38 pasted on the inner wall is formed. Conductive material 37 is disposed in the trench and connected to node 62 to provide a capacitance that alters the frequency response of the input signal VIN to produce a filtered signal VOUT. The electrostatic discharge device includes an inductor 74 coupled to back-to-back diodes 17 and 18 formed in the substrate to avalanche when the node voltage reaches a predetermined magnitude.

Integrated filter, static discharge device, protection circuit

Description

Semiconductor filter circuit and method

The present invention relates generally to semiconductor devices, in particular low frequency filter networks formed in semiconductor substrates.

Wireless communication devices generally operate using radio frequency (RF) signals and low frequency audio signals. For example, cellular telephones transmit RF carrier signals that operate at frequencies above 6 GHz and are modulated with audio frequency voice information. The microphone generates an audio frequency signal from speech information that is amplified and used to modulate the RF carrier signal. Most wireless communication devices are “picked up” by the microphone to prevent performance degradation of the communication device by noise effects, loop instability, or other effects that reduce the quality of the modulated audio signal. A low pass filter is used at the microphone input to suppress ambient RF carrier signals that can be detected or detected. To achieve this function, the low pass filters have an audio range, i.e., a passband of about 20 KHz or less.

At present, since it is difficult to form large component values that set the low frequency passband of the filters, the audio filters are formed of discrete passive components. However, discrete filters increase the substantial manufacturing cost of the wireless device. Integrated filters based on semiconductor technology are inexpensive but not practical because they provide adequate voltage capability but require a large die area to integrate audio frequency components.

Thus, there is a need for an integrated filter that provides high levels of frequency selectivity while maintaining low manufacturing costs.

1 is a block diagram of a wireless communication device.

2 is a schematic diagram of a filter circuit.

3 is a cross-sectional view of a filter circuit integrated on a semiconductor substrate.

3A is a plan view of the filter circuit of FIG. 3 showing an inductor.

4 is a cross-sectional view of a filter circuit in an alternative embodiment.

5 is a sectional view of a filter circuit in another alternative embodiment.

In the figures, elements with the same reference numerals have a similar function.

1 shows a wireless communication device 3 including a microphone 4, an antenna 5, an oscillator 6, a power stage 7, a modulator 8, an audio amplifier 9, and a filter 10. It is a block diagram. The communication device 3 converts the voice information received via the microphone 4 into an electrical input signal V _IN at the lead 64 of the filter 10 and transmits a power level of 2 W or more for transmission to the antenna 5. Generates an RF transmitter signal (V _XMIT ). In one embodiment, the communication device 3 is configured as a cellular telephone, for example, broadcasting a transmitter signal V _XMIT to a cellular base station.

The filter 10 is a low pass microphone line filter used to suppress RF components of the input signal V _IN from another circuit of the communication device 3, such as the audio amplifier 9. That is, the filter 10 rejects or attenuates the RF components, but passes the audio frequency components of the input signal V _IN . The audio components are generated from the voice information by the microphone 4 and the RF components are generated by incident electromagnetic waves generated by the antenna 5 at, for example, V _XMIT carrier frequency. In the case of a cellular telephone, when the microphone 4 is in close proximity to the antenna 5, the RF components can be of sufficient size to overload the audio amplifier 9 if the RF components are not attenuated or suppressed. , Signal distortion, noise, instability, or other undesirable effects on the performance of the communication device 3. Filter 10 has an output at lead 65 to produce a filtered audio output signal V _OUT . The filter 10 attenuates the RF component frequency by at least 30 dB at a frequency of 6 GHz and is designated to pass audio frequency components of V _IN . Thus, V _OUT is usually composed of no or very few audio frequency components.

The audio amplifier 9 amplifies the output signal V _OUT and generates an amplified audio signal V _AUD . Oscillator 6 generates an RF oscillator signal V _OSC at the desired carrier frequency of the transmitter signal V _XMIT . Modulator 8 modulates the V _OSC to V _AUD and coupled to the power stage (7) and generating a signal (V _MOD) to generate a modulated transmitter signal to be amplified (V _XMIT). In one embodiment, V _XMIT has an RF carrier frequency of about 6 GHz.

2 shows an electrostatic discharge comprising a resistor 24, capacitors 21-22, a clamp diode 27, and back to back diodes 17-18 and an inductor 74; ESD) is a schematic diagram of a device 20. The input signal V _IN has audio frequency components and unwanted RF components. Output 65 produces a filtered output signal V _{OUT that} operates at audio frequencies with attenuated or suppressed RF components. The filter 10 is configured to integrate on a semiconductor die to form an integrated circuit.

Diodes 17-18 of ESD device 20 include back to back zener or avalanche diodes formed as junctions in a semiconductor substrate as described below. The diodes 17-18 are referred to as back-to-back diodes because the common cathode (or alternatively common anode) arrangement of the diodes is reverse biased, either of which is independent of the polarity of V _IN . ESD device 20 dissipates electrostatic energy in the form of short term high voltage peaks that can damage sensitive system components. In one embodiment, the ESD device 20 is configured to comply with the International Electrotechnical Commision (IEC) standard IEC61000-4-2 Level 4. In one embodiment of FIG. 3, diodes 17-18 are commonly as shown to break down symmetrically when the voltage magnitude at node 66 reaches about 14V positive and / or 14V negative. Has respective cathodes connected. During a positive voltage peak, diode 17 is forward biased, diode 18 avalanches at about 13.3 volts, and during a negative voltage peak, diode 18 is forward biased and diode 17 at about 13.3 volts. Avalanche. Alternatively, ESD device 20 may include back-to-back diodes commonly connected to the anodes of the diodes rather than the cathodes of the diodes to achieve similar protection.

Inductor 74 is formed as a planar spiral inductor to have a typical value in the range of 1 nH to 5 nH. In one embodiment, inductor 74 is formed by patterning a standard metal interconnect layer.

Capacitors 21-22 are connected as shown to generate capacitances of approximately C ₂₁ = C ₂₂ = 1.0 nF, respectively, which alter the frequency response of V _IN to produce a filtered output signal V _OUT . It is formed as trench capacitors. The trench design provides capacitors 21-22 with low equivalent series resistance, and therefore high quality rate, which results in low impedance and high quality filtering at RF frequencies.

Resistor 24 is generally formed as a thin film resistor with low parasitic substrate capacitance for improved filter performance. The resistor 24 cooperates with the capacitors 21-22 to establish a characteristic frequency response for the filter 10. In one embodiment, resistor 24 is formed of doped polysilicon having a concentration selected to produce a specified resistance value in a small die area, while a high level of control is provided to maintain the resistances within a specified acceptable range. In one embodiment, the value of resistor 24 is controlled to within ± 10%. In one embodiment, resistor 24 has a temperature coefficient of resistance of about 50 Ω and near zero resistance.

The clamp diode 27 is an avalanche diode that breaks down to limit the voltage swing at the leads to prevent overloading the input stage of the amplifier 9. Thus, clamp diode 27 also provides ESD protection in lead 65. In one embodiment, clamp diode 27 is formed of a structure similar to diode 17 or diode 18, and thus has similar features, that is, a breakdown voltage of about 13.3V.

3 is formed on a semiconductor substrate 11, showing an inductor 74, a resistor 24, an ESD device 20, a clamp diode 27, and capacitors 21-22, and an integrated filter circuit. The cross section of the filter 10 comprised as shown is shown.

The base layer 30 is formed of a semiconductor material and heavily doped to function as a low resistance ground plane for the filter 10. In one embodiment, the base layer 30 has a doping concentration in the range of 10 ¹⁶ to 10 ²¹ atoms / cm ³ . For example, the base layer 30 has single crystal silicon doped to provide a p-type conductivity and a doping concentration of about 2 * 10 ²⁰ atoms / cm ³ . The low resistivity of the base layer 30 provides an effective ground plane that attenuates parasitic signals that would otherwise propagate through the base layer 30 along the parasitic signal paths to produce crosstalk and degrade filter performance.

An epitaxial layer 31 is grown on the base layer 30 and doped to have n-type conductivity. The epitaxial layer 31 forms a junction with the base layer 30 to include the diode 18 so that the doping concentration of the epitaxial layer 31 is specified for the diode 18, for example 13.3V. It is selected to provide an avalanche voltage. The epitaxial layer 31 generally has a thickness in the range between 2 μm and 10 μm. In one embodiment, epitaxial layer 31 has a thickness of about 2.5 μm and a concentration of 5 * 10 ¹⁷ atoms / cm ³ .

Layer 32 is formed over epitaxial layer 31 to have n-type conductivity. Doped region 33 is formed by introducing p-type dopants from surface 35 of substrate 11 to create a junction that functions as diode 17. The doping concentrations of the epitaxial layer 32 and the doping region 33 are selected to provide the avalanche voltage specified for the diode 17, for example 13.3V. In one embodiment, layer 32 is an epitaxial layer having a thickness of about 3 μm and a concentration of about 1 * 10 ¹⁷ atoms / cm ³ , and the doped region 33 is about 1 μm thick and about 6.0 * 10 ^19. It has a surface concentration of atoms / cm ³ . Alternatively, epitaxial layer 31 is about 5.5 μm thick and layer 32 is epitaxial layer 31 to reduce its effective concentration to set the breakdown voltage of diode 17 to a desired level. ) Is made by allowing blanket p-type diffusion. This diffusion step reduces the doping concentration of epitaxial layer 31 within a depth of less than about 3 μm.

An isolation region or sinker 12 is formed in a circle around the ESD device 20 having a depth of about 20 μm and a p-type conductivity to electrically isolate the ESD device 20 from other components. . The sinker 12 diffuses from the surface 35 to the base layer 30 through the epitaxial layers 31-32 to provide external electrical contact, which is the processing step used to form the doped region 33. By adding the doped region 36 using them. Thus, the doped region 36 has a p-type conductivity such that the sinker 12 is electrically coupled to an interconnect trace connected to the conductive line 62 through the doped region 36.

Channel stopper 34 is heavily doped to have n-type conductivity and a depth of about 3 μm. The channel stopper 34 surrounds the doped region 33 and prevents the surface from inverting to form a channel causing a conductive path from the doped region 33 to the base layer 20. The channel stopper 34 also increases the ESD robustness of the device by ensuring the loss of lateral current flow injected during the ESD event to prevent the formation of current filaments on the surface 35.

The dielectric material is disposed on the surface 35 and patterned and etched to create the dielectric region 45. In one embodiment, dielectric region 45 includes a silicon dioxide thermally augmented to a thickness of about 500 microns, followed by a deposited silicon diooxide layer about 1 micrometer thick.

The capacitor 21 is formed as a trench capacitor by etching the semiconductor substrate 11 to a depth of about 7 μm to form a plurality of trenches 40 in the sinker 12 as shown. In an alternative embodiment, trench 40 includes a single serpentine trench or some rows of each trench that extend along surface 35 and is viewed as many times as needed to produce a C ₂₁ = 1.0 nF capacitance. Intersect the view plane.

The dielectric material is formed along the inner surfaces of the trench 40 to form a dielectric liner 38. In one embodiment, the dielectric material comprises silicon nitride formed to a thickness of about 400 GPa.

Conductive material, such as doped polysilicon, is deposited and etched to form a conductive region that fills the trench 40 serving as the first electrode of the capacitor 21 with the sinker 12 serving as the second electrode. The sinker 12 is coupled to the lead 62 through a thin, heavily doped p-type contact region 36 formed of the processing steps used to form the doped region 33. Capacitor 22 is formed in a similar manner.

Clamp diode 27 is formed by the junction of base layer 30 and epitaxial layer 31 as shown and is isolated from other components by surrounding it with sinker 12. Thus, clamp diode 27 has a breakdown feature similar to the breakdown feature of diode 18 in ESD device 20.

The standard integrated circuit metal layer is deposited and etched with the interconnect traces to form bonding pads 60, 61. Inductor 74 is formed simultaneously by patterning this standard integrated circuit metal layer. Other interconnect traces are schematically represented to simplify the drawing.

Node 64 is a metal such as solder bumps or copper bumps used to mount filter 10 on a system circuit board (not shown) in a flip-chip manner. It includes a bonding structure shown as a bump. Alternatively, the bonding structure may include a wire bond or other suitable structure to provide external electrical connections and / or mechanical connections. The bonding structure has a parasitic inductance (L ₆₄ ) between about 0.05 nH and 0.1 nH, which produces an impedance or inductive reactance X ₆₄ = 2 * π * f _c * L ₆₄ with respect to the input signal (V _IN ), where f _c is the RF carrier frequency of the transmitter signal (V _XMIT ). For example, if L ₆₄ = 0.1 nH and f _c = 6.0 GHz, then X ₆₄ = 2 * π * (6.0 * 10 ⁹ ) * (0.1 * 10 ^-9 ) has a value of about 4Ω.

The output signal V _OUT is provided to node 65 via a structure similar to that of node 64. The node 65 bonding structure has a parasitic inductance L ₆₅ value similar to the value of L ₆₄ .

3A is a plan view of a portion of the filter 10 showing the inductor 74 formed around the bonding pad 60. In the embodiment of FIG. 3A, the inductor 74 is formed as a single winding that separates the boundaries of the bonding pads 60 and is spaced about 20 μm apart. Alternatively, inductor 74 may be formed as a planar spiral inductor with multiple windings. Inductor 74 generally has an inductance in the range between 1 nH and 5 nH. Inductor 74 provides a smoothing function that flattens or integrates the voltage peaks of the ESD event, thereby improving the robustness of filter 10. Inductor 74 also improves signal filtering by compensating for high frequency signal feedthrough due to parasitic inductances L ₆₄ , L ₆₅ described above.

4 is a cross-sectional view of the filter 10 in an alternative embodiment. The features described above have similar structures and operations, except that epitaxial layer 31 is about 5.5 μm thick. Layer 32 is formed as a masked region of p-type conductivity surrounding doped region 33. In this embodiment, the region 32 has the same conductivity type, but slightly more doped than the doped region 33, which breaks the diode 17 portion down against the lower surface of the layer 32 than the side surfaces. This has the effect of shifting. This adjustment ensures that diode 17 has a large effective breakdown area and low impedance to dissipate the energy generated by the ESD event, thereby providing high reliability.

5 is a cross-sectional view of the filter in another alternative embodiment in which the base layer 30 is formed as a high resistivity material. In this embodiment, the base layer 30 comprises slightly doped n-type single crystal silicon having an effective carrier concentration of 3 * 10 ¹² atoms / cm ³ and a resistivity of about 1000 ohm-cm. The high resistivity reduces the signal coupled through parasitic signal paths and improves electrical isolation between adjacent components which improves the performance of the filter.

The p-type dopants are implanted through the surface 35 and diffused into the semiconductor substrate 11 to form well regions 51 and 54. In one embodiment, well regions 51 and 54 are formed to a depth of about 15 μm. Well regions 51 and 54 are generally doped at a lower concentration than sinkers 12, but the same thermal cycle is used to diffuse well regions 51 and 54 and sinkers 21 into substrate 11. do. The low concentration of well regions 51 and 54 makes it thinner than sinkers 12.

N-type dopants are introduced into the substrate 11 through dielectric region 54 openings to form doped regions 52-53 in well region 51 and doped region 56 in well region 54. The doped regions 52-53 form junctions with the well region 51 which respectively act as back-to-back diodes 17-18 of the ESD device 20. The doping concentrations of the well region 51 and the doping regions 52-53 are adjusted to provide a predefined breakdown voltage to be a specified performance of the ESD device 20. In one embodiment, the doped regions 52-53 are each formed in a square to occupy an area of the surface 35 which is about 200 μm on one side. Since the doped regions 52 and 53 are formed in the same processing step, it is noted that avalanche breakdown voltages and other performance parameters are symmetrical with respect to the polarity of the node 64 voltage.

Similarly, doped region 56 and well region 54 form a junction comprising clamp diode 27.

In summary, the present invention provides an integrated filter circuit that achieves a specified frequency selection using integrated circuit technology to achieve small physical size and low manufacturing costs. The semiconductor substrate is formed of a trench in which a dielectric layer is attached to an inner wall. Conductive material is used to fill the trench to provide a capacitance that filters the input signal. When the static discharge voltage reaches a predetermined magnitude, back-to-back diodes are formed in the substrate to avalanche.

Claims (19)

In the integrated filter for filtering the input signal, A semiconductor substrate having a trench in which a dielectric layer is attached to an inner wall thereof; A first conductive material disposed within the trench and coupled to the node to provide a capacitance that modifies the frequency response of the input signal to produce a filtered signal; A protection circuit comprising back to back diodes formed in the semiconductor substrate to avalanche when the voltage of the node reaches a predetermined magnitude; And An inductor formed over said semiconductor substrate, said inductor coupled between said node and an input configured to receive an input signal with said integrated filter. delete delete The integrated filter of claim 1, wherein the semiconductor substrate is of a first conductivity type and comprises a base layer having a doping concentration in the range between 10 ¹⁸ and 10 ²¹ atoms / cm ³ . The method of claim 4, wherein the back-to-back diodes are: A first doped region of a second conductivity type forming a first junction with the base layer; And A second doped region of said first conductivity type, said second doped region forming said second junction with said first doped region, said second doped region coupled to said node. delete delete delete delete delete delete delete delete delete delete delete delete In a wireless communication device, A power stage for receiving a modulated signal and transmitting an output signal of the wireless communication device; A modulator for modulating a radio frequency carrier signal into an audio signal to produce the modulated signal; A microphone for converting voice information into the audio signal, the microphone for receiving a portion of the output signal; And A filter formed on the semiconductor substrate and inserted between the microphone and the power stage to attenuate radio frequency components of the output signal, The filter is: A first doped region formed on a surface of the semiconductor substrate; A second doped region formed on a surface of the semiconductor substrate, the second doped region having conductivity opposite to that of the semiconductor substrate; A trench formed in the first doped region and having sidewalls; A dielectric material positioned at at least a portion of sidewalls of the trench to adhere to an inner wall of the trench; A first conductive material disposed in the dielectric material in the trench to provide a capacitance that attenuates the radio frequency components; And And an electrostatic discharge circuit comprising back-to-back diodes formed in said second doped region to limit the magnitude of the terminal voltage of said filter to a predetermined value. In the integrated filter for filtering the input signal, Semiconductor substrates; A first doped region formed in the semiconductor substrate; A second doped region formed in the semiconductor substrate; A trench formed in said first doped region, said trench having a dielectric layer pasted on an inner wall thereof; A first conductive material disposed within the trench and coupled to the node to provide a capacitance that modifies the frequency response of the input signal to produce a filtered signal; And And a protection circuit comprising back-to-back diodes formed in the second doped region to avalanche when the voltage of the node reaches a predetermined magnitude.

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