KR100888335B1 - Semiconductor package and fabricating?method?thereof - Google Patents

Abstract

The present invention relates to a semiconductor package and a method for manufacturing the same. The technical problem to be solved is to form an input / output pad in both directions of a wafer by using a silicon through electrode, thereby improving electrical performance, reducing wafer loss, and reducing size. The present invention provides a semiconductor package and a method of manufacturing the same.

To this end, the present invention is formed on the first surface of the first silicon wafer, the first surface of the first silicon wafer, the first silicon wafer having a flat second surface as the opposite surface of the first surface, the first surface, and the first active layer, the first bond pad and the first surface. A first semiconductor die comprising a first passivation layer, a second semiconductor die formed on a second side of the first silicon wafer and comprising a second active layer, a second bond pad and a second passivation layer, a first semiconductor die and a second A semiconductor package comprising a first through electrode electrically connecting a semiconductor die and a first solder bump electrically connected to a second bond pad, and a method of manufacturing the same.

In this manner, the semiconductor package and the method of manufacturing the same according to the present invention reduce wafer loss, shorten the process for polishing the wafer, and improve the electrical performance as the wiring length for stacking the semiconductor die is shortened. In addition, it is possible to implement a relatively small and thin semiconductor package, including a semiconductor die having a bond pad formed on both sides.

Through-electrodes, semiconductor dies, bond pads, solder bumps, silicon wafers

Description

Semiconductor package and manufacturing method thereof {SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same. More specifically, by forming an input / output pad in both directions of a wafer by using a silicon through electrode, the electrical performance is improved, the loss of the wafer, and the size of the semiconductor are reduced. A package and a method of manufacturing the same.

In general, a semiconductor package includes a semiconductor die manufactured by processing a wafer to form an integrated circuit (IC) on the wafer. The semiconductor package is completed through a structure in which the semiconductor die is mounted on a substrate such as a lead frame or a printed circuit board. In addition, a wafer-level semiconductor package or the like packaged using the wafer itself as a substrate without a substrate is used.

On the other hand, the conventional semiconductor package has a problem that the integrated circuit is formed only on one side of the wafer, so that the other side of the wafer is not used. In addition, when stacking a plurality of wafers in order to implement a high-performance stacking package, there is a problem in that the wafer of more planes is lost. In addition, there is a problem that the number of processes for stacking a plurality of wafers increases by that much.

Disclosure of Invention The present invention is to solve the above-mentioned problems, and by forming a semiconductor die in both directions of the wafer by using a through electrode, a semiconductor package and a method for manufacturing the semiconductor having improved electrical performance by reducing wafer loss and shortening wiring paths The purpose is to provide.

Another object of the present invention is to provide a semiconductor package having a relatively small and thin structure and a method of manufacturing the same, by enabling input / output in both directions from one semiconductor die by using a semiconductor die having bond pads formed in both directions.

The semiconductor package of the present invention for achieving the above object A first silicon wafer having a first flat surface, a second surface that is opposite to the first surface, and a third surface connecting the first and second surfaces, the first flat surface and the first surface; A first active layer formed on the first surface of the first silicon wafer, and a plurality of first active layers formed on the first surface of the first active layer to be electrically connected to the first active layer; A first semiconductor die, a flat first surface and the first surface, the first bond pad having a first bond pad and a first passivation layer formed on a first surface of the first active layer to expose the first bond pad; A second active layer formed on the second surface of the first silicon wafer, the second active layer being perpendicular to the second surface, and formed on the first surface of the second active layer to be electrically connected to the second active layer; A plurality of second bond pads and the A second semiconductor die comprising a second passivation layer exposing a second bond pad, a first through electrode electrically connecting the first semiconductor die and the second semiconductor die, and a first electrically connected to the second bond pad Solder bumps; characterized in that comprises a. In this case, the first active layer is formed between the first epitaxial layer and the first epitaxial layer formed of a thin film grown using the first silicon wafer as a seed, and is electrically connected to the first bond pad. It can be made including one device layer. In addition, the second active layer is formed between the second epitaxial layer and the second epitaxial layer formed of a thin film grown using the first silicon wafer as a seed, and is electrically connected to the second bond pad. It may comprise a two-element layer. Here, each of the first active layer and the second active layer may have a second surface formed on the same plane as the third surface of the first silicon wafer. In this case, the first silicon wafer may be formed relatively thicker than the first active layer. In addition, the first silicon wafer may be formed relatively thicker than the second active layer. The first through electrode may be formed to electrically connect the first bond pad and the second bond pad. In addition, the present invention may further include a third semiconductor die electrically connected to the first solder bumps. The semiconductor device may further include a second silicon wafer having a first flat surface, a second surface that is flat as an opposite surface of the first surface, and a third surface that connects the first surface and the second surface to the third semiconductor. The die has a first flat surface and a second surface perpendicular to the first surface, and includes a third active layer formed on the first surface of the second silicon wafer, the third active layer being electrically connected to the third active layer. And a plurality of third bond pads formed on the first surface of the third active layer and a third passivation layer formed on the first surface of the third active layer and exposing the third bond pads. In addition, the first solder bumps may be electrically connected to the third bond pads. The present invention may further include a fourth semiconductor die formed on the second surface of the second silicon wafer and electrically connected to the third semiconductor die. Wherein the fourth semiconductor die has a first flat surface and a second surface perpendicular to the first surface, the fourth active layer being formed on the second surface of the second silicon wafer, and electrically connected to the fourth active layer. A plurality of fourth bond pads formed on the first surface of the fourth active layer to be connected to each other, and a fourth passivation layer formed on the first surface of the fourth active layer and exposing the fourth bond pads; Can be done. In this case, the method may further include a second through electrode formed to electrically connect the third bond pad and the fourth bond pad. The electronic device may further include a second solder bump electrically connected to the fourth bond pad. Wherein the third active layer is formed between the third epitaxial layer and the third epitaxial layer formed of a thin film grown using the second silicon wafer as a seed, and is electrically connected to the third bond pad. It may comprise a layer. In addition, the fourth active layer is formed between the fourth epitaxial layer and the fourth epitaxial layer made of a thin film grown using the second silicon wafer as a seed, and is electrically connected to the fourth bond pad. It can be made including four device layers. In this case, each of the third active layer and the fourth active layer may have a second surface formed on the same plane as the third surface of the second silicon wafer. In addition, the second silicon wafer may be formed relatively thicker than the third active layer. In addition, the second silicon wafer may be formed relatively thicker than the fourth active layer.

In addition, the semiconductor package according to the present invention has a flat first surface and a flat second surface as an opposite surface to the first surface, and a plurality of first conductive patterns are formed on the first surface, and a plurality of the second surfaces are formed on the first surface. A plurality of first bond pads formed on the first surface and having a second surface that is flat as a substrate on which the second conductive pattern of the substrate is formed, the first flat surface, and the opposite surface of the first surface; A first semiconductor die mounted to the substrate, a conductive wire electrically connecting the first conductive pattern and the first bond pad, the second bond pad and the first bond pad to be formed on the substrate; A first solder bump electrically connected between a first conductive pattern and an encapsulant surrounding an outer periphery of the first semiconductor die and the conductive wire of the first side of the substrate; Can be done together. In this case, the first semiconductor die may include a first passivation layer formed on the first surface of the first semiconductor die to expose the first bond pad and a second surface of the first semiconductor die to expose the second bond pad. It may further comprise a second passivation layer formed on. In addition, it may further comprise a solder ball electrically connected to the second conductive pattern. The substrate may further include conductive vias electrically connecting the first conductive pattern and the second conductive pattern. In addition, the substrate is formed on the second surface of the substrate to cover a portion of the first solder mask and the second conductive pattern formed on the first surface of the substrate to cover a portion of the first conductive pattern. A second solder mask may be further included. The semiconductor device may further include a first underfill formed between the first semiconductor die and the substrate to surround an outer circumference of the first solder bump. In this case, the method may further include a second semiconductor die electrically connected to the first semiconductor die. Wherein the second semiconductor die includes a first flat surface and a second surface that is flat to the opposite side of the first surface and is formed on the first surface of the second semiconductor die to be electrically connected to the first bond pad. And a third passivation layer formed on a first bond pad and a first surface of the second semiconductor die to expose the third bond pad. In addition, the present invention may further include a second solder bump electrically connected to the third bond pad. On the other hand, between the first semiconductor die and the second semiconductor die, may further comprise a second underfill surrounding the outer periphery of the second solder bump. In this case, the second semiconductor die may include a fourth bond pad formed on the second surface of the second semiconductor die and a fourth passivation layer formed on the second surface of the second semiconductor die to expose the fourth bond pad. It can be made to include more.

In addition, the semiconductor package according to the present invention has a flat first surface and a flat second surface as an opposite surface to the first surface, and a plurality of first conductive patterns are formed on the first surface, and a plurality of the second surfaces are formed on the first surface. A plurality of first bond pads formed on the first surface and having a second surface that is flat as a substrate on which the second conductive pattern of the substrate is formed, the first flat surface, and the opposite surface of the first surface; A first semiconductor die mounted to said substrate, a first solder bump electrically connecting said first semiconductor die and said substrate, a first flat surface and said first surface, including a plurality of second bond pads formed; And a plurality of third bond pads formed on the first side and a plurality of fourth bond pads formed on the second side, the second semiconductor die having a flat second surface as an opposite side thereof. And a second solder bump electrically connected to the second semiconductor die and a second solder bump electrically connecting the first semiconductor die and the second semiconductor die. In this case, the present invention may further include a first underfill surrounding the outer periphery of the first solder bumps between the first semiconductor die and the substrain. The semiconductor device may further include a second underfill surrounding the outer periphery of the second solder bumps between the first semiconductor die and the second semiconductor die. The first solder bumps may be electrically connected between the second bond pads and the first conductive pattern. In addition, the second solder bumps may be electrically connected between the first bond pads and the third bond pads. In addition, the substrate may further include a solder ball electrically connected to the second conductive pattern. In addition, the substrate may further include a conductive via that electrically connects the first conductive pattern and the second conductive pattern. In this case, the substrate is formed on the second surface of the substrate to cover a portion of the first solder mask and the second conductive pattern formed on the first surface of the substrate to cover a portion of the first conductive pattern. A second solder mask may be further included.

In addition, the manufacturing method according to the present invention comprises a first silicon wafer preparation step of preparing a first silicon wafer having a flat first surface and a second flat surface as an opposite surface of the first surface, the first of the first silicon wafer A first semiconductor die forming step of forming a first semiconductor die on a surface; a first silicon wafer backgrinding step of grinding a second surface of the first silicon wafer; a second on a second surface of the ground first silicon wafer A second semiconductor die forming step of forming a semiconductor die, a first through electrode forming step of forming a first through electrode electrically connecting the first semiconductor die and the second semiconductor die, and an electrical connection to the second semiconductor die And a first solder bump fusion step of fusion welding the first solder bumps. The forming of the first semiconductor die may include forming a first active layer on the first surface of the first silicon wafer, the first active layer having a flat first surface and including a first epitaxial layer and a first device layer. Forming a first bond pad to form a plurality of first bond pads formed on a first surface of the first active layer to be electrically connected to the first device layer; And forming a first passivation layer formed on the first surface of the first active layer so as to cover the first passivation layer. The forming of the second semiconductor die may include forming a second active layer on the second surface of the first silicon wafer, the second active layer having a flat first surface and including a second epitaxial layer and a second device layer. A second bond pad forming step, a second bond pad forming step of forming a plurality of second bond pads formed on a first surface of the second active layer to be electrically connected to the second device layer, and the second active layer And a second passivation layer formed on the first surface to form a second passivation layer exposing the second bond pads. Wherein after the first solder bump fusion step, the tape of the surface of the first solder bump and the surface of the second passivation layer is taped, and the first passivation layer is patterned to expose the first bond pad. The method may further include a passivation layer patterning step and a tape removing step of removing the tape. The forming of the first through electrode may be performed by filling a conductive material in a through hole penetrating between the first bond pad and the second bond pad after the forming of the second passivation layer.

As described above, according to the semiconductor package and the manufacturing method thereof according to the present invention, the first and second semiconductor dies are formed on both sides of the first silicon wafer, respectively, so that the first silicon wafer can be efficiently used without being wasted. It works. At this time, the process for polishing the first silicon wafer is shortened because the process for polishing the first silicon wafer as thin as possible can be eliminated.

In addition, the first semiconductor die and the second semiconductor die are electrically connected by the first through electrode penetrating the first silicon wafer, so that no separate wiring for stacking the semiconductor dies is required, and the wiring length is shortened. The resistance component due to the wiring is reduced. Accordingly, the electrical performance of the semiconductor package can be improved.

In addition, according to the present invention, by stacking each semiconductor package having two semiconductor dies formed on one silicon wafer with each other, a thinner and higher performance stack package can be realized.

In addition, according to the present invention has a semiconductor package structure capable of input and output in both directions through a semiconductor die having a bond pad formed on both sides. Accordingly, various types of semiconductor packages can be implemented.

In addition, by stacking semiconductor dies using bond pads formed on both surfaces, a separate stacking process is not required, and thus a relatively small and thin semiconductor package can be realized.

In addition, a plurality of semiconductor dies having bond pads formed on both surfaces thereof may be stacked through solder bumps, so that semiconductor dies of various sizes may be stacked without space constraints.

Hereinafter, a semiconductor package and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings and embodiments. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Referring to FIG. 1, a cross-sectional view of a semiconductor package according to an embodiment of the present invention is shown.

As shown in FIG. 1, a semiconductor package 1 according to an exemplary embodiment of the present invention may include a first semiconductor die 200 formed on both surfaces of a first silicon wafer 100 and a first silicon wafer 100, respectively. And a first semiconductor electrode 300 electrically connected to the second semiconductor die 300, the first through electrode 400 and the second semiconductor die 300. 1 may include a solder bump 500.

The first silicon wafer 100 is a substantially flat first surface 100a, a surface opposite to the first surface 100a, a substantially flat second surface 100b, and a first surface 100a and a second surface 100b. It includes a third surface (100c) for connecting. The first silicon wafer 100 may have a relatively thick thickness t1 compared to the thicknesses t2 and t3 of the first active layer 220 and the second active layer 320, which will be described below. This is to facilitate handling when the first epitaxial layer 220, the second epitaxial layer 320, and the like are formed on the first silicon wafer 100. The first silicon wafer 100 is obtained by thinly cutting a single crystal silicon rod (INGOT) grown using polycrystalline silicon as a raw material to smoothly polish the surface. The first silicon wafer 100 is used as a base substrate of the first semiconductor die 200 and the second semiconductor die 300 to be described below. That is, in the first silicon wafer 100, an oxidation process, a patterning process using photoresist (PR), and ion implantation are performed on each of the first and second surfaces 100a and 100b. The first semiconductor die 200 and the second semiconductor die 300 are completed by forming an integrated circuit through ion implantation, a metal wiring process, or the like.

The first semiconductor die 200 may include a first active layer 220 formed on the first silicon wafer 100, a first bond pad 240 formed on the first active layer 220, and a first passivation layer ( 260).

The first active layer 220 is formed on the first surface 100a of the first silicon wafer 100. The first active layer 220 is formed to have a first surface 220a that is substantially flat and a second surface 220b that is substantially perpendicular to the first surface 220a. The second surface 220b of the first active layer 220 may be formed on substantially the same plane as the third surface 100c of the first silicon wafer 100. The first active layer 220 may include a first epitaxial layer 221 and a first device layer 222. The first epitaxial layer 221 is formed of a thin film including at least one selected from silicon (Si) and gallium arsenide (GaAs) or equivalents thereof. The epitaxial process of growing a single crystal thin film on the first surface 100a of the first silicon wafer 100 using the first epitaxial layer 221 as a seed. It can be formed by. The epitaxy process may include liquid phase epitaxy (LPE), vapor phase epitaxy (VPE) and molecular beam epitaxy (MBE) depending on the growth method of the single crystal silicon film. In the present invention, the method of growing the first epitaxial layer 221 is not limited. A plurality of first device layers 222 are formed through a process of patterning a circuit to be formed on the first epitaxial layer 221 and depositing copper (Cu) or aluminum (Al) wiring. The ion is implanted into a required portion of the first epitaxial layer 221, and further includes an isolation layer (not shown) and an interlayer insulating layer (not shown) made of an insulating material for the first device layer 222. The active layer 220 is completed. The first active layer 220 may be an integrated circuit (IC) including an active device such as a transistor, or an integrated passive device (IPD) in which a capacitor, a resistor, and the like are integrated. It is not limited. Meanwhile, although the first epitaxial layer 221 is illustrated as being formed in one layer in the present invention, it may be formed of a plurality of layers.

The first bond pad 240 is formed on the first surface 220a of the first active layer 220. In more detail, the first bond pad 240 may be formed to be electrically connected to the first device layer 222. In addition, the first bond pad 240 is electrically connected to the second semiconductor package 300 through the first through electrode 400 to be described below. The first bond pad 240 may be made of copper (Cu) and aluminum (Al) or an equivalent thereof, but is not limited thereto. The first bond pad 240 may be formed by sputtering, vacuum deposition, or photolithography, but is not limited thereto.

The first passivation layer 260 is formed on the first surface 220a of the first active layer 220. That is, the first passivation layer 260 is formed to cover the first surface 220a of the first active layer 220, and exposes a portion of the first bond pad 240 formed on the first active layer 220. Let's do it. The first passivation layer 260 may include a side surface 260a formed on a plane substantially the same as the second surface 220b of the first active layer 220. The first passivation layer 260 covers the first surface 220a of the first active layer 220, which is the outer circumference of the first bond pad 240, thereby protecting the first active layer 220. . The first passivation layer 260 may be made of any one material selected from a common oxide film, a nitride film, a polyimide, or an equivalent thereof, but is not limited thereto. In addition, the first passivation layer 260 is deposited on the first surface 220a of the first active layer 220 by chemical vapor deposition or any method equivalent thereto, and then undergoes a chemical mechanical planarization (CMP) process. Through it can be formed in a substantially flat state. The first passivation layer 260 is formed through the patterning process after the second semiconductor die 300, the first through electrode 400, and the first solder bumps 500, which will be described below, are sequentially formed. ) Is exposed. Accordingly, the first passivation layer 260 may protect the first semiconductor die 300 from heat and external stimuli while the second semiconductor die 300 is formed.

The second semiconductor die 300 may include a second active layer 320 formed on the first silicon wafer 100, a second bond pad 340 and a second passivation layer formed on the second active layer 320. 360).

The second epitaxial layer 320 is formed on the second surface 100b of the first silicon wafer 100. The second epitaxial layer 320 is formed to have a first surface 320a that is substantially flat and a second surface 320b that is approximately perpendicular to the first surface 320a. The second surface 320b of the second active layer 320 may be formed on the same plane as the third surface 100c of the first silicon wafer 100. The second active layer 320 may include a second epitaxial layer 321 and a second device layer 322. The second epitaxial layer 321 and the second device layer 322 may be formed in substantially the same manner as the first epitaxial layer 221 and the first device layer 322 described above. The second active layer 320 may be an integrated circuit (IC) including an active device such as a transistor, or an integrated passive device (IPD) in which a capacitor, a resistor, and the like are integrated. It is not limited. Meanwhile, in the present invention, although the second epitaxial layer 321 is illustrated as being formed in one layer, the second epitaxial layer 321 may be formed in a plurality of layers.

The second bond pad 340 is formed on the first surface 320a of the second active layer 320. In more detail, the second bond pad 340 may be formed to be electrically connected to the second device layer 322. The second bond pad 340 is formed to be electrically connected to the first through electrode 400 to be described below, which is formed through the first bond pad 240. In this case, the first solder bumps 500 to be described below may be electrically connected to the second bond pads 340. The second bond pad 340 may be formed of substantially the same material and the same method as the first bond pad 240 described above, but is not limited thereto.

The second passivation layer 360 is formed on the first surface 320a of the second active layer 320. That is, the second passivation layer 360 is formed to cover the first surface 320a of the second active layer 320 and exposes a portion of the second bond pad 340 formed on the second active layer 320. Let's do it. The second passivation layer 360 may include a side surface 360a formed on a plane substantially the same as the second surface 320b of the second active layer 320. The second passivation layer 360 covers the first surface 320a of the second active layer 320, which is the outer circumference of the second bond pad 340, thereby protecting the second active layer 320. . The first passivation layer 360 may be made of substantially the same material as the first passivation layer 260 described above, but is not limited thereto. In addition, after the second passivation layer 360 is formed by any one of chemical vapor deposition or the like, the second bond pad 340 is exposed through a patterning process.

The first through electrode 400 electrically connects the first semiconductor die 200 and the second semiconductor die 300. That is, the first through electrode 400 may be formed to electrically connect the first bond pad 240 and the second bond pad 340 to each other. Due to the first through electrode 400, the first semiconductor die 200 and the second semiconductor die 300 formed on the first and second surfaces 100a and 100b of the first silicon wafer 100 may be electrically connected to each other. It becomes possible. The first through electrode 400 penetrates through the second bond pad 340, the second active layer 320, the first silicon wafer 100, the first active layer 220, and the first bond pad 240. It may be formed by filling the through hole v1 with a conductive material. The through hole v1 may be formed by a laser drill or a chemical etching method, but is not limited thereto. The first through electrode 400 may be formed of any one material selected from copper (Cu), gold (Au), silver (Ag), aluminum (Al), or an equivalent thereof, but is limited thereto. It doesn't. The first through electrode 400 may be any one selected from physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic or electroless plating, or an equivalent thereof. It may be formed, but is not limited to this in the present invention. Although not illustrated, an insulating film is filled in the inner wall of the through hole v1 so that current flows from the first through electrode 400 to the first silicon wafer 100, the first semiconductor die 200, and the second semiconductor die 300. It can be prevented from leaking.

The first solder bumps 500 may be formed to be electrically connected to the second bond pads 340. The first solder bumps 500 may be formed of tin / lead (Sn / Pb) and leadless tin (Leedless Sn) or equivalents thereof, but the material of the first solder bumps 500 is not limited thereto. The first solder bumps 500 apply flux to the second bond pads 340, and then screen-print the solder or ball-shaped solders for forming the first solder bumps 500 to the second bond pads 340. After being seated by a method such as (Screen Printing) or Ball Drop, it may be formed through a reflow and cooling process. The flux applied to the second bond pad 340 may be formed of a viscous material so that the solder for the first solder bump 500 may be well seated, and is mostly volatilized during the reflow process with a volatile material.

In the semiconductor package 1 described above, the semiconductor die 200 is formed on the first surface 100a of the first silicon wafer 100, and the second semiconductor die 300 is formed on the second surface 100b. The semiconductor dies 200 and 300 are formed on both surfaces 100a and 100b to prevent loss of the first silicon wafer 100. In addition, since it is not necessary to form the first silicon wafer 100 thinly, the process for polishing the first silicon wafer 100 is shortened.

In addition, the first semiconductor die 200 and the second semiconductor die 300 are electrically connected to each other by the first through electrode 400 formed through the first silicon wafer 100 to thereby form the first semiconductor die 200. ) And a separate wiring for connecting the second semiconductor die 300 are not required, and the wiring length can be shortened to reduce the resistance component due to the wiring. As a result, the electrical performance of the semiconductor package 1 is improved.

2, a cross-sectional view of a semiconductor package according to another embodiment of the present invention is shown.

As shown in FIG. 2, a semiconductor package 3 according to another embodiment of the present invention includes a first semiconductor package 1 and a second semiconductor package 2. Since the semiconductor package 3 of FIG. 2 is partially the same as the semiconductor package 1 of FIG. 1, the following description will focus on the differences.

The first semiconductor package 1 may include a first semiconductor die 200, a second semiconductor die 300, and a first semiconductor die formed on both surfaces of the first silicon wafer 100 and the first silicon wafer 100, respectively. And a first solder bump 500 electrically connected to the second semiconductor die 300 and the first through electrode 400 electrically connecting the 200 and the second semiconductor die 300 to each other. In this case, the first semiconductor package 1 is electrically connected to the second semiconductor package 3 through the first solder bumps 500. The first semiconductor package 1 is substantially the same as the semiconductor package 1 of FIG. 1.

The second semiconductor package 2 may include a third semiconductor die 700 and a fourth semiconductor die 800 and a third semiconductor die formed on both surfaces of the second silicon wafer 600 and the second silicon wafer 600, respectively. The second through electrode 900 electrically connecting the 700 and the fourth semiconductor die 800 to each other may include a second solder bump 1000 electrically connected to the fourth semiconductor die 800. The second semiconductor package 2 has substantially the same structure as the semiconductor package 1 of FIG. 1.

The second silicon wafer 600 is an approximately flat first surface 600a, an opposite surface of the first surface 600a, and a substantially flat second surface 600b and a first surface 600a and a second surface 600b. It includes a third surface (600c) for connecting. The second silicon wafer 600 may have a relatively thick thickness t4 compared to the thicknesses t5 and t6 of the third active layer 720 and the fourth active layer 820, which will be described below. This is to facilitate handling of the silicon wafer when the third active layer 720 and the fourth active layer 820 are formed on the second silicon wafer 600. The second silicon wafer 600 is formed in substantially the same manner as the first silicon wafer 100 described above.

The third semiconductor die 700 is formed on the first surface 600a of the second silicon wafer 600. The third semiconductor die 700 includes a third active layer 720 formed on the first surface 600a of the second silicon wafer 600 and a third bond pad 740 formed on the third active layer 720. And a third passivation layer 760.

The third active layer 720 is formed on the first surface 600a of the second silicon wafer 600, and is substantially flat with the first surface 720a and the second surface perpendicular to the first surface 720a. 720b. The second surface 720b of the third active layer 720 may be formed on substantially the same plane as the third surface 600c of the second silicon wafer 600. The third active layer 720 includes a third epitaxial layer 721 and a plurality of third device layers 722. The third active layer 720 may be grown on the first surface 600a of the second silicon wafer 600 in substantially the same manner as the first active layer 220 described above. The third device layer 722 may be formed in the same manner as the first device layer 221 described above. The third active layer 720 may be any one selected from an integrated circuit including an active element or an integrated passive element, but is not limited thereto.

The third bond pad 740 is formed on the first surface 720a of the third active layer 720. The third bond pad 740 may be formed to be electrically connected to the third device layer 722. The third bond pad 740 may be electrically connected to the first solder bumps 500 of the first semiconductor package 1 described above. Accordingly, the first semiconductor package 1 and the second semiconductor package 2 are electrically connected. In addition, the third bond pad 740 is electrically connected to the fourth bond pad 840 through the second through electrode 900 to be described below. Herein, the material and the forming method of the third bond pad 740 are the same as the first bond pad 240 described above.

The third passivation layer 760 is formed to cover the first surface 720a of the third active layer 720, and exposes a portion of the third bond pad 740 formed on the third active layer 720. . The third passivation layer 260 protects the third active layer 720 and prevents the third semiconductor die 700 from being damaged while the fourth semiconductor die 800 is described below. Since the material and the formation method of the third passivation layer 260 are substantially the same as the first passivation layer 260 described above, a detailed description thereof will be omitted.

The fourth semiconductor die 800 is formed on the second surface 600b of the second silicon wafer 600. The fourth semiconductor die 800 is the fourth active layer 820 formed on the second surface 600b of the second silicon wafer 600, and the fourth bond pad 840 formed on the fourth active layer 820. And a fourth passivation layer 860.

The fourth active layer 820 is formed on the second surface 600b of the second silicon wafer 600 and is substantially flat with a first surface 820a and a second surface that is substantially perpendicular to the first surface 820a. It is formed to have 820b. The second surface 820b of the fourth active layer 820 may be formed on substantially the same plane as the third surface 600c of the second silicon wafer 600. The fourth epitaxial layer 221 includes the fourth epitaxial layer 821 and the fourth device layer 822. In this case, the fourth device layer 822 is electrically connected to the fourth bond pad 840. The fourth active layer 820 may be any one selected from an integrated circuit including an active element or an integrated passive element, but is not limited thereto.

The fourth bond pad 840 is formed on the first surface 820a of the fourth active layer 820. The fourth bond pad 840 may be formed to be electrically connected to the fourth device layer 822. The fourth bond pad 840 is formed to be electrically connected to the second through electrode 900 to be described below. In this case, the second solder bumps 900 may be electrically connected to the fourth bond pads 840. The fourth bond pad 840 may be formed of substantially the same material and the same method as the first bond pad 240 of FIG. 1, but is not limited thereto.

The fourth passivation layer 860 is formed to cover the first surface 820a of the fourth active layer 820, and exposes a portion of the fourth bond pad 840 formed on the fourth active layer 320. . The fourth passivation layer 860 serves to protect the fourth active layer 820. The material and the forming method of the fourth passivation layer 860 are substantially the same as the second bond pads 340 of FIG. 1.

The second through electrode 900 electrically connects the third semiconductor die 700 and the fourth semiconductor die 800. That is, the second through electrode 900 may be formed to electrically connect the third bond pad 840 and the fourth bond pad 840 therebetween. The second through electrode 900 may be formed in substantially the same manner as the first through electrode 400 of FIG. 1. That is, the second through electrode 900 may include the fourth bond pad 840, the fourth active layer 820, the second silicon wafer 600, the third active layer 720, and the third bond pad 740. It may be formed by filling a conductive material in the through hole (v2) through. The method of forming the through hole v2 and the material of the through electrode 900 are the same as the first through electrode 400 of FIG. 1. Although not illustrated, an insulating film is filled in the inner wall of the through hole v2, and current flows from the second through electrode 900 to the third semiconductor die 700, the second silicon wafer 600, and the fourth semiconductor die 800. Leakage can be prevented.

The second solder bumps 1000 may be formed to be electrically connected to the fourth bond pads 240. Since the material and the forming method of the second solder bumps 1000 are substantially the same as the first solder bumps 500 of FIG. 1, detailed descriptions thereof will be omitted.

According to another embodiment of the present invention described above, the semiconductor package 3 is a semiconductor die (200, 300) on both the first side (100a, 600a) and second side (100b, 600b) of the silicon wafer (100, 600) By stacking the semiconductor packages 1 and 2 on which the 700 and 800 are formed, the thinner and higher-performance stacking packages can be implemented. In the present invention, a structure in which two semiconductor packages are stacked is exemplified, but more semiconductor packages may be stacked. In this case, as the number of stacked semiconductor packages (or semiconductor dies) increases, the loss rate of the silicon wafer is further reduced, and the number of processes for polishing the silicon wafer may be relatively reduced. Other basic operations are similar to or the same as those of the semiconductor package 1 of FIG. 1, and a detailed description thereof will be omitted.

Referring to FIG. 3, there is shown a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

As shown in FIG. 3, the semiconductor package 5 according to another embodiment of the present invention includes a substrate 1100, a first bond pad 1220, and a second bond pad 1240, and the substrate 1100. A conductive wire 1300, substrate 1100, and second bond pad 1240 electrically connecting the first semiconductor die 1200, the substrate 1100, and the first bond pad 1220 to each other. The first solder bump 1400, the first underfill 1500, the substrate 1100, the semiconductor die 1200, and the conductive wire 1300, which are formed on the outer circumference of the first solder bump 1400, are electrically connected. The encapsulant 1600 surrounding the outer circumference and the solder ball 1700 electrically connected to the substrate 1100 may be formed.

The substrate 1100 is an opposite surface of the first surface 1100a and the first surface 1100a which are substantially flat around the insulating layer 1110, and the second surface 1100b and the first surface 1100a which are substantially flat, and And a third surface 1100c approximately perpendicular to the second surface 1100b. The substrate 1100 may include a plurality of first conductive patterns 1120 and a second surface 1100b formed on the first surface 1100a around the insulating layer 1110 and the insulating layer 1110. A second conductive pattern 1130 is formed. In this case, the at least one first conductive pattern 1120 and the at least one second conductive pattern 1130 may be electrically connected through the conductive via 1140. In addition, the substrate 1100 may further include a first solder mask 1150 and a second solder mask 1160 formed to cover portions of each of the first conductive pattern 1120 and the second conductive pattern 1140. Can be. Each of the first solder mask 1150 and the second solder mask 1160 prevents the first conductive pattern 1120 and the second conductive pattern 1130 from being excessively exposed to the outside and oxidized or corroded. do. The substrate 1100 may be any one selected from a typical rigid printed circuit board, a flexible printed circuit board, a lead frame, or an equivalent thereof. It does not limit the kind in invention.

At least one of the first conductive patterns 1120 may be electrically connected to each of the first bond pads 1220 and the second bond pads 1240, which will be described below. At least one first conductive pattern 1120 is electrically connected to the first bond pad 1220 through the conductive wire 1300. At least one of the first conductive patterns 1120 that is not electrically connected to the first bond pad 1220 is electrically connected to the second bond pad 1240 through the first solder bump 1400. In this case, the solder ball 1700 for electrically transmitting an electrical signal to the second conductive pattern 1130 is electrically connected to the second conductive pattern 1130.

The first semiconductor die 1200 is mounted on the first surface 1100a of the substrate 1100. The first semiconductor die 1200 may be mounted on the second surface 1100b of the substrate 1100, but is not limited thereto. The first semiconductor die 1200 includes a first surface 1200a that is approximately flat and a second surface 1200b that is approximately flat opposite the first surface 1200a. The first surface 1200a of the first semiconductor die 1200 covers the first surface 1100a of the first semiconductor die 1200 to expose the first bond pad 1220 and the first bond pad 1220. The first passivation layer 1230 is formed. The second surface 1100b of the first semiconductor die 1200 covers the second surface 1200b of the first semiconductor die 1200 to expose the second bond pad 1240 and the second bond pad 1240. The second passivation layer 1250 is formed. The first bond pad 1220 and the second bond pad 1240 are electrically connected to the substrate 1100, respectively, and are responsible for input / output (I / O) of the first semiconductor die 1200. Although not shown, the first semiconductor die 1200 may form a through electrode (not shown) between the first bond pad 1220 and the second bond pad 1240 to electrically connect them. Although the first bond pad 1220 and the second bond pad 1220 are illustrated as being formed in one semiconductor die 1200, as shown in FIG. 1, two bond pads are formed on both surfaces of a silicon wafer (not shown). It may be a bond pad each formed (not shown) in the semiconductor dies. Meanwhile, the first and second passivation layers 1230 and 1250 are formed to protect the first and second surfaces 1200a and 1200b of the first semiconductor die 1200, respectively, and may be formed of an oxide film or a nitride film. However, the present invention is not limited thereto.

The conductive wire 1300 electrically connects the substrate 1100 and the first semiconductor die 1200. That is, the conductive wire 1300 electrically connects at least one first bond pad 1220 formed on the first semiconductor die 1200 and at least one first conductive pattern 1120 formed on the substrate 1100. . The conductive wire 1300 may be formed of a material including any one group selected from a group including copper (Cu), gold (Au), aluminum (Al), and silver (Ag), or an equivalent group thereof. have. However, the material of the conductive wire 1300 is not limited thereto in the present invention. One end of the conductive wire 1300 connected to the first bond pad 1220 through the wire bonder is ball bonded, and the other end connected to the first conductive pattern 1120 is stitch bonded. It may be formed in a manner that is, but the present invention is not limited thereto. One or more conductive wires 1300 may be formed like the first bond pads 1220, and the number of conductive wires 1300 is not limited in the present invention.

The first solder bumps 1400 electrically connect the semiconductor die 1200 and the substrate 1100. That is, the first solder bumps 1400 electrically connect the at least one second bond pad 1240 formed on the first semiconductor die 1200 and the at least one first conductive pattern 1120 formed on the substrate 1100. Connect. The first solder bumps 1400 may be formed of tin / lead (Sn / Pb) and leadless tin (Leedless Sn) or equivalents thereof, but the material of the first solder bumps 1400 is not limited thereto. The first solder bumps 1400 apply flux to the second bond pads 1240, and then screen-print the solder or ball-shaped solders for forming the first solder bumps 1400 to the second bond pads 1240. After being seated by a method such as (Screen Printing) or Ball Drop, it may be formed through a reflow and cooling process. In this case, the flux applied to the second bond pad 1240 may be formed of a viscous material so that the solder for the first solder bump 1400 may be well seated, and is mostly volatilized during the reflow process with a volatile material. .

The first underfill 1500 is formed between the substrate 1100 and the first semiconductor die 1200. In more detail, the first underfill 1500 may be formed to surround the outer circumference of the first solder bump 1400 between the substrate 1100 and the first semiconductor die 1200. The first underfill 1500 is a first solder bump 1400 and the first semiconductor die 1200 and the first solder bump 1400 and the substrate 1100 is a heat process (heat is formed after the formation of the first solder bumps) All processes) or external shocks to maintain a stable bond. The first underfill 1500 may be formed of an epoxy resin, a thermosetting resin, a polymer polymer, or an equivalent thereof, but is not limited thereto.

The encapsulant 1600 is formed to surround the outer circumference of the first semiconductor die 1200 and the conductive wire 1300 of the first surface 1100a of the substrate 1100. The encapsulant 1600 completely encapsulates the first semiconductor die 1200 and the conductive wire 1300 to protect them from damage from external impact and oxidation. The encapsulant 1600 may be any one selected from an epoxy compound that performs encapsulation through a mold, a liquid encapsulation material that performs encapsulation through a dispenser, and an equivalent thereof, but according to the present invention, the encapsulant 1600 ) Does not limit the material.

The solder ball 1700 may be formed to be electrically connected to the second conductive pattern 1130 of the substrate 1100. Through the solder ball 1700, the semiconductor package 5 may exchange electrical signals with an external device. The solder ball 1700 may be formed through substantially the same material and the same method as the first solder bump 1400 described above. In this case, the solder ball 1700 may be formed to have a relatively wide diameter as compared to the first solder bump 1400, but the present invention is not limited thereto.

According to another embodiment of the present invention described above, in the semiconductor package 5, bond pads 1220 and 1240 are formed on both the first and second surfaces 1200a and 1200b of the semiconductor die 1200. It has a structure that can input and output to. Accordingly, the semiconductor package 5 may simultaneously use the conductive wire 1300 and the first solder bump 1400 when connecting the first semiconductor die 1200 and the substrate 1100. Implementation is possible.

4, a cross-sectional view of a semiconductor package according to another embodiment of the present invention is shown.

As shown in FIG. 4, the semiconductor package 7 according to another embodiment of the present invention includes a substrate 1100, a first bond pad 1220, and a second bond pad 1240, and the substrate 1100. The conductive wire 1300, the substrate 1100, and the second bond pad 1240, which electrically connect the first semiconductor die 1200, the substrate 1100, and the first bond pad 1220 mounted thereto. A first solder bump 1400 electrically connected to each other, a first underfill 1500 formed at an outer circumference of the first solder bump 1400, and a third bond pad 1820 and connected to the first semiconductor die 1200. On the outer circumference of the second semiconductor die 1800 mounted, the second solder bump 1900 and the second solder bump 1900 electrically connecting between the first bond pad 1220 and the third bond pad 1820. The second underfill 2000, the substrate 1100, the first semiconductor die 1200, the conductive wire 1300, and the first 2 may include an encapsulant 2100 surrounding the outer circumference of the semiconductor die 1800 and a solder ball 1700 electrically connected to the substrate 1100. Since some components of the semiconductor package 7 of FIG. 4 are the same as those of the semiconductor package 5 of FIG. 3, the differences will be described below.

The second semiconductor die 1800 is mounted on the first surface 1100a of the first semiconductor die 1200. The second semiconductor die 1800 includes a first surface 1800a that is approximately flat and a second surface 1800b that is approximately flat opposite the first surface 1800a. The first surface 1800a of the second semiconductor die 1800 covers the first surface 1800a of the second semiconductor die 1800 to expose the third bond pad 1820 and the third bond pad 1820. The third passivation layer 1830 is formed. In this case, the second surface of the second semiconductor die 1800 may be exposed to expose the fourth bond pad 1840 and the fourth bond pad 1840 formed on the second surface 1800b of the second semiconductor die 1800. It may further include a fourth passivation layer 1850 covering 1800b. The third bond pad 1820 electrically connects the first semiconductor die 1200 and the second semiconductor die 1800 through the second solder bumps 1900, thereby providing input / output (I / I) of the second semiconductor die 1800. O) is in charge. The material and forming method of the second semiconductor die 1800 may be substantially the same as the first semiconductor die 1200 described above.

The second solder bumps 1900 are formed to electrically connect the first semiconductor die 1200 and the second semiconductor die 1800. In more detail, the second solder bumps 1900 may be formed between the first bond pads 1220 of the first semiconductor die 1200 and the third bond pads 1820 of the second semiconductor die 1800. have. The material and the formation method of the second solder bumps 1900 are substantially the same as the first solder bumps 1400 described above.

 The second underfill 2000 is formed to surround the outer circumference of the second solder bump 1900 between the first semiconductor die 1200 and the second semiconductor die 1200. Accordingly, the second underfill 2000 may include heat applied to the first bond pad 1220 and the second solder bumps 1900 and the third bond pad 1820 and the third bond pad 1820 in a thermal process, or Even if there is an external impact, it is possible to maintain a stable coupling. The second underfill 2000 may be made of the same material as the first underfill 1500.

The encapsulant 2000 may be made in the same manner as the encapsulant 1600 of FIG. 3. The encapsulant 2000 is formed to surround the outer periphery of the first semiconductor die 1200, the conductive wire 1300, and the second semiconductor die 1800 of the first surface 1100a of the substrate 1100. .

According to another embodiment of the present invention described above, the semiconductor package 7 is laminated to each other using bond pads formed on both sides of the first and second semiconductor dies 1200 and 1800, so that a separate lamination process is not required. . Accordingly, it is possible to implement a relatively small and thin semiconductor package 7.

5, a cross-sectional view of a semiconductor package according to another embodiment of the present invention is shown.

As shown in FIG. 5, a semiconductor package 9 according to another embodiment of the present invention has a substrate 3100, a first bond pad 3220, and a second bond pad 3240. Formed on the outer periphery of the first solder bump 3400 and the first solder bump 3400 electrically connecting the first semiconductor die 3200, the first semiconductor die 3200, and the substrate 3100. The second semiconductor die 3800 and the first semiconductor die 3, which are electrically connected to the first underfill 3500, the first solder bumps 3400, and having a third bond pad 3820 and a fourth bond pad 3840. The second solder bump 3900 and the second underfill 4000 and the substrate 3100 formed on the outer circumference of the second solder bump 3900 to electrically connect the 3200 and the second semiconductor die 3800 to each other It includes a solder ball 3700 connected to. Since the semiconductor package 9 of FIG. 5 is partially the same as the semiconductor package 7 of FIG. 4, the following description will focus on the differences.

The substrate 3100 is an opposite surface of the first surface 3100a and the first surface 3100a, which are approximately flat around the insulating layer 3110, and are substantially flat on the second surface 3100b and the first surface 3100a, and And a third surface 3100c approximately perpendicular to the second surface 3100b. In this case, a first conductive pattern 3120 is formed on the first surface 3100a and a second conductive pattern 3130 is formed on the second surface 3100b. In this case, the at least one first conductive pattern 3120 and the at least one second conductive pattern 3130 may be electrically connected through the conductive via 3140. In addition, the substrate 3100 may further include a first solder mask 1150 and a second solder mask 1160 formed to cover portions of each of the first conductive pattern 3120 and the second conductive pattern 3140. Can be. Substrate 3100 is substantially the same as substrate 3100 of FIG. 4.

The first semiconductor die 3200 has an approximately flat first face 3200a and a second face 3200b opposite the first face 3200a. The first semiconductor die 3200 includes a first bond pad 3220 formed on the first surface 3200a and a second bond pad 3240 formed on the second surface 3200b. In this case, the first bond pad 3220 and the second bond pad 3240 may be formed to be exposed from the first passivation layer 3130 and the second passivation layer 3250, respectively. At least one first bond pad 3220 may be connected to at least one second solder bump 3900 which will be described below. In addition, at least one second bond pad 3240 may be connected to at least one first solder bump 3400 to be described below. The first bond pads 3220 and the second bond pads 3240 are formed in both directions of the first semiconductor die 3200, respectively, and serve as input / output of the first semiconductor die 3200.

The first solder bumps 3400 electrically connect the substrate 3100 and the first semiconductor die 3200. The first solder bumps 3400 are substantially the same as the first solder bumps 1400 of FIG. 4.

The first underfill 3500 is formed to surround an outer circumference of the first solder bump 3400 between the substrate 3100 and the first semiconductor die 3200. The first underfill 3500 is substantially the same as the first underfill 1500 of FIG. 4.

The second semiconductor die 3800 has a first surface 3800a that is approximately flat and a second surface 3800b that is approximately flat opposite the first surface 3800a. The second semiconductor die 3800 includes a third bond pad 3820 formed on the first surface 3800a and a fourth bond pad 3840 formed on the second surface 3800b. In this case, the third bond pad 3820 and the fourth bond pad 3840 may be formed to be exposed from the third passivation layer 3830 and the fourth passivation layer 3850, respectively. The third bond pad 3820 may be electrically connected to the first bond pad 3220 through the following second solder bumps 3900. Accordingly, the first semiconductor die 3200 and the second semiconductor die 3800 may be electrically connected to each other. Although not illustrated, another semiconductor die may be mounted on the second semiconductor die 3800, but the present invention is not limited thereto. That is, solder bumps may be further formed on the fourth bond pads 3840 to be electrically connected to other semiconductor dies. In addition, although the first semiconductor die 3200 and the second semiconductor die 3800 are formed to have substantially the same size, they may be formed to have different sizes.

The second solder bumps 3900 electrically connect the first semiconductor die 3200 and the second semiconductor die 3800. The second solder bump 3900 is substantially the same as the second solder bump 1900 of FIG. 4.

The second underfill 4000 is formed to surround the outer circumference of the second solder bump 3900 among the first semiconductor die 3200 and the second semiconductor die 3800. The second underfill 4000 is substantially the same as the second underfill 2000 of FIG. 4.

The solder ball 3700 is electrically connected to the second conductive pattern 3130 of the substrate 3100. Through the solder ball 3700, the semiconductor package 9 may exchange electrical signals with an external device.

According to another embodiment of the present invention described above, the semiconductor package 9 can stack semiconductor dies of more various sizes without space constraints by stacking semiconductor dies using only solder bumps. In addition, an encapsulant for protecting the conductive wire does not have to be further formed, which reduces the process. At this time, each semiconductor die has a structure in which bi-directional input and output is possible because bond pads are formed on both surfaces. This allows for thinner, higher performance semiconductor packages.

Next, a method of manufacturing a semiconductor package according to the present invention will be described. Here, the manufacturing method will be described with reference to the semiconductor package 1 shown in FIG. 1. However, the manufacturing method of the semiconductor package may be equally applicable to the other embodiments described above.

Referring to FIG. 6, a flowchart illustrating a method of manufacturing a semiconductor package according to the present invention is illustrated, and FIGS. 7A to 7G illustrate a step-by-step manufacturing method according to the flowchart of FIG. 6.

As shown in FIG. 6, the method of manufacturing a semiconductor package according to the present invention may include preparing a first silicon wafer (S100), forming a first semiconductor die (S200), and performing a first silicon wafer backgrinding step (S300). The semiconductor die forming step (S400), the first through electrode forming step (S500), the first solder ball fusion step (S600), and the first passivation layer patterning step (S700) are performed.

As shown in FIG. 7A, the first silicon wafer preparation step S100 may include a first surface 100a that is substantially flat, a second surface 100b that is substantially flat, and a first surface that is opposite to the first surface 100a. A step of preparing a first silicon wafer 100 having a third surface 100c connecting 100a and the second surface 100b is performed. The first silicon wafer 100 may be prepared by thinly cutting a single crystal silicon rod (INGOT) grown using polycrystalline silicon as a raw material to smoothly polish the surface. Accordingly, the first surface 100a and the second surface 100b of the first silicon wafer 100 have a smooth surface for thin film deposition and pattern formation. The first silicon wafer 100 is used as a base substrate of the first semiconductor die 200 and the second semiconductor die 300 to be described below. That is, in the first silicon wafer 100, an oxidation process, a patterning process using photoresist (PR), and ion implantation are performed on each of the first and second surfaces 100a and 100b. The first semiconductor die 200 and the second semiconductor die 300 may be completed by forming an integrated circuit through ion implantation, a metal wiring process, or the like.

As shown in FIG. 7B, the first semiconductor die forming step S200 is a step of forming the first semiconductor die 200 on the first surface 100a of the first silicon wafer 100. The first semiconductor die forming step S200 may include a first active layer forming step S220, a first bond pad forming step S240, and a first passivation layer forming step S260.

In the first active layer forming step S220, the first active layer 220 is formed on the first surface 100a of the first silicon wafer 100. The first active layer 220 is formed to have a first surface 220a that is substantially flat and a second surface 220b that is substantially perpendicular to the first surface 220a. The second surface 220b of the first active layer 220 may be formed on substantially the same plane as the third surface 100c of the first silicon wafer 100. The first active layer 220 may include a first epitaxial layer 221 and a first device layer 222. The first epitaxial layer 221 is formed of a thin film including at least one selected from silicon (Si) and gallium arsenide (GaAs) or equivalents thereof. The epitaxial process of growing a single crystal thin film on the first surface 100a of the first silicon wafer 100 using the first epitaxial layer 221 as a seed. It can be formed by. The epitaxy process may include liquid phase epitaxy (LPE), vapor phase epitaxy (VPE) and molecular beam epitaxy (MBE) depending on the growth method of the single crystal silicon film. In the present invention, the method of growing the first epitaxial layer 221 is not limited. A plurality of first device layers 222 are formed through a process of patterning a circuit to be formed on the first epitaxial layer 221 and depositing copper (Cu) or aluminum (Al) wiring. The ion is implanted into a required portion of the first epitaxial layer 221, and further includes an isolation layer (not shown) and an interlayer insulating layer (not shown) made of an insulating material for the first device layer 222. The active layer 220 is completed. The first active layer 220 may be an integrated circuit (IC) including an active device such as a transistor, or an integrated passive device (IPD) in which a capacitor, a resistor, and the like are integrated. It is not limited. Meanwhile, although the first epitaxial layer 221 is illustrated as being formed in one layer in the present invention, it may be formed of a plurality of layers.

The first bond pad forming step (S240) is a step of forming a first bond pad 240 electrically connected to the first active layer 220. The first bond pad 240 is formed on the first surface 220a of the first active layer 220. In more detail, the first bond pad 240 may be formed to be electrically connected to the first device layer 222. In addition, the first bond pad 240 is electrically connected to the second semiconductor package 300 through the first through electrode 400 to be described below. The first bond pad 240 may be made of copper (Cu) and aluminum (Al) or an equivalent thereof, but is not limited thereto. The first bond pad 240 may be formed by sputtering, vacuum deposition, or photolithography, but is not limited thereto.

The first passivation layer forming step (S260) is a step of forming a first passivation layer 260 covering the first surface 220a and the first bond pad 240 of the first active layer 220. The first passivation layer 260 is formed on the first surface 220a of the first active layer 220. The first passivation layer 260 is the second surface 220b of the first active layer 220. And a side surface 260a which is formed on a plane substantially the same as that of FIG. The first passivation layer 260 may be made of any one material selected from a common oxide film, a nitride film, a polyimide, or an equivalent thereof, but is not limited thereto. The first passivation layer 260 is deposited on the first surface 220a of the first active layer 220 by any method of chemical vapor deposition or the like, and then roughly formed through a chemical mechanical planarization (CMP) process. It may be formed in a flat state. The first passivation layer 260 protects the first active layer 220 and the first bond pad 240 from being damaged during thermal processing or external damage during the second semiconductor die forming step S400. . After the second semiconductor die 300 and the first through electrode 400 are formed, the first passivation layer 260 may expose the first bond pad 240 through a patterning process.

As illustrated in FIG. 7C, the first silicon wafer backgrinding step S300 may be performed by grinding the second surface 100b of the first silicon wafer 100 by a predetermined thickness. Accordingly, the first silicon wafer 100 may have a thickness that meets the specifications of the semiconductor package 1. In this case, the second surface 100b of the first silicon wafer 100 may be smoothly polished to form an integrated circuit. The first silicon wafer 100 may have a thickness t1 that is relatively thicker than the thickness t2 of the first active layer 220. This is to facilitate handling of the first silicon wafer 100 and the like during the manufacturing process. As is well known, the grinding method can be carried out using, for example, a diamond grinder and its equivalents, which do not limit the grinding method.

As shown in FIG. 7D, the second semiconductor die forming step S400 is a step of forming the second semiconductor die 300 on the second surface 100a of the first silicon wafer 100. The die forming step S400 may include a second active layer forming step S420, a second bond pad forming step S440, and a second passivation layer forming step S460.

The second active layer forming step (S420) is a step of forming the second active layer 320 on the second surface 100b of the first silicon wafer 100. The second active layer 320 is formed to have an approximately flat first surface 320a and a second surface 320b approximately perpendicular to the first surface 320a. The second surface 320b of the second active layer 320 may be formed on substantially the same plane as the third surface 100c of the first silicon wafer 100. The second active layer 320 may include a second epitaxial layer 321 and a second device layer 322. The second epitaxial layer 321 and the second device layer 322 may be formed in substantially the same manner as the first epitaxial layer 221 and the first device layer 322 described above. The second active layer 320 may be an integrated circuit (IC) including an active device such as a transistor, or an integrated passive device (IPD) in which a capacitor, a resistor, and the like are integrated. It is not limited. Meanwhile, in the present invention, although the second epitaxial layer 321 is illustrated as being formed as one layer, the second epitaxial layer 321 may be formed as a plurality of layers.

The second bond pad forming step (S440) is a step of forming the second bond pad 340 on the first surface 320a of the second active layer 320. In this case, the second bond pad 340 may be formed to be electrically connected to the second device layer 322. The second bond pad 340 is electrically connected to the first bond pad 240 through the following first through electrode 400. In addition, the second bond pad 340 may be electrically connected to the first solder bump 500 described below. The second bond pad 340 may be formed of substantially the same material and the same method as the first bond pad 240 described above, but is not limited thereto.

The second passivation layer forming step (S460) is a step of forming the second passivation layer 360 on the first surface 320a of the second active layer 320. The second passivation layer 360 is formed to cover the first surface 320a of the second active layer 320 and exposes a portion of the second bond pad 340 formed on the second active layer 320. The second passivation layer 360 may include a side surface 360a formed on substantially the same plane as the second surface 320b of the second active layer 320. The second passivation layer 360 may be made of substantially the same material as the first passivation layer 260 described above, but is not limited thereto. The second passivation layer 360 is the second passivation layer 360 is the first surface 320a of the first bond pad 340 and the second active layer 320 during the first through electrode forming step (S500) is in progress Protect.

As shown in FIG. 7E, the forming of the first through electrode S500 may include forming a first through electrode 400 electrically connecting the first semiconductor die 200 and the second semiconductor die 300 to each other. to be. That is, the first through electrode 400 may be formed to electrically connect the first bond pad 240 and the second bond pad 340 to each other. Due to the first through electrode 400, the first semiconductor die 200 and the second semiconductor die 300 formed on each of the first and second surfaces 100a and 100b of the first silicon wafer 100 are electrically connected to each other. Can be connected. The first through electrode 400 penetrates through the second bond pad 340, the second active layer 320, the first silicon wafer 100, the first active layer 220, and the first bond pad 240. It may be formed by filling the through hole v1 with a conductive material. The through hole v1 may be formed by a laser drill or a chemical etching method, but is not limited thereto. The first through electrode 400 may be formed of any one material selected from copper (Cu), gold (Au), silver (Ag), aluminum (Al), or an equivalent thereof, but is limited thereto. It doesn't. The first through electrode 400 may be any one selected from physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic or electroless plating, or an equivalent thereof. It may be formed, but is not limited to this in the present invention. Although not illustrated, an insulating film is filled in the inner wall of the through hole v1 so that current flows from the first through electrode 400 to the first silicon wafer 100, the first semiconductor die 200, and the second semiconductor die 300. It can be prevented from leaking. When the first through electrode 400 is completed, the second passivation layer 360 is patterned to expose a portion of the second bond pad 340.

As shown in FIG. 7F, the first solder bump fusion step S600 is a step of forming a first solder bump 500 electrically connected to the second bond pad 340. The first solder bumps 500 may be formed of tin / lead (Sn / Pb) and leadless tin (Leedless Sn) or equivalents thereof, but the material of the first solder bumps 500 is not limited thereto. The first solder bumps 500 apply flux to the second bond pads 340, and then screen-print the solder or ball-shaped solders for forming the first solder bumps 500 to the second bond pads 340. After being seated by a method such as (Screen Printing), it may be formed through a reflow and cooling process. The flux applied to the second bond pad 340 may be formed of a viscous material so that the solder for the first solder bump 500 may be well seated, and is mostly volatilized during the reflow process with a volatile material.

 As shown in FIG. 7G, the first passivation layer patterning step S700 is a step of patterning the first passivation layer 260 to expose a required portion of the first bond pad 240. The first passivation layer patterning step S700 may include a taping step S720, a patterning step S740, and a tape removing step S760.

The taping step S720 is a step of attaching a tape Tp surrounding the surface 500a of the first solder bump 500 and the surface 360b of the second passivation layer 260. The tape Tp protects the second passivation layer 260 and the first solder bumps 500 from being damaged from heat, ultraviolet rays, foreign matters, etc. during the patterning of the first passivation layer 260. As the tape Tp, a UV tape or the like that can be removed without damaging the first solder bump 500 and the second passivation layer 260 may be used, but the present invention is not limited thereto. .

The patterning step S740 is a step of exposing a portion of the first bond pad 240 by patterning the first passivation layer 260. In addition, the first passivation layer 260 thickly formed to form the second semiconductor die 300 is thinly patterned according to the specifications of the semiconductor package 1. The first passivation layer 260 may be patterned using dry etching or wet etching, but is not limited thereto. Other solder bumps, semiconductor dies, and semiconductor packages may be further electrically connected to the first bond pads 240 exposed by the first passivation layer 260, but the present invention is not limited thereto.

The tape removing step S760 is a step of removing the tape Tp attached to the surfaces 260b and 500a of the second passivation layer 260 and the first solder bump 500. The tape Tp may be weakened through the stimulus, or may be removed using another tape that is stronger. For example, when the tape Tp is a uv tape, the adhesiveness of the tape Tp may be weakened by a method of irradiating ultraviolet rays to the surface of the tape Tp.

According to the manufacturing method of the semiconductor package of the present invention described above, the portion of the first silicon wafer 100 is wasted by forming the semiconductor die (200, 300) on both sides (100a, 100b) of the first silicon wafer 100 It is used efficiently without. In addition, since the first silicon wafer 100 does not need to be thinned, the process for polishing the first silicon wafer 100 is shortened.

In addition, by forming the first passivation layer 260 relatively thick in the first semiconductor die forming step S200, the first semiconductor die 200 already formed in the second semiconductor die forming step S400 is protected from being damaged. can do. The first semiconductor die 200 and the second semiconductor die 300 are electrically connected to each other by the first through electrode 400 formed through the first silicon wafer 100 to thereby be connected to the first semiconductor die 200. The separate wiring for connecting the second semiconductor die 300 is not required, and the wiring length can be shortened to reduce the resistance component due to the wiring. As a result, the electrical performance of the semiconductor package 1 is improved.

The present invention is not limited to the above-described specific preferred embodiments, and any person skilled in the art to which the present invention pertains may make various modifications without departing from the gist of the present invention as claimed in the claims. Of course, such changes are within the scope of the claims.

1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

2 is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

3 is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

4 is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

5 is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

6 is a flowchart illustrating a method of manufacturing a semiconductor package according to the present invention.

7A to 7G are diagrams illustrating a step-by-step manufacturing method according to the flowchart of FIG. 6.

<Description of Symbols for Main Parts of Drawings>

1, 3, 5, 7, 9: semiconductor package 100: first silicon wafer

200: first semiconductor die 220: first active layer

240: first bond pad 260: first passivation layer

300: second semiconductor die 320: second active layer

340: second bond pad 360: second passivation layer

400: first through electrode 500: first solder bump

Claims (43)

A first silicon wafer having a first flat surface, a second surface that is planar as an opposite surface of the first surface, and a third surface connecting the first and second surfaces; A first active layer formed on a first surface of the first silicon wafer, the first active layer having a first flat surface and a second surface perpendicular to the first surface, and the first active layer to be electrically connected to the first active layer A first semiconductor die including a plurality of first bond pads formed on a first surface of an active layer and a first passivation layer formed on a first surface of the first active layer and exposing the first bond pads; A second active layer having a first flat surface and a second surface perpendicular to the first surface, the second active layer formed on the second surface of the first silicon wafer, and the second active layer so as to be electrically connected to the second active layer; A second semiconductor die comprising a plurality of second bond pads formed on a first side of the active layer and a second passivation layer exposing the second bond pads; A first through electrode electrically connecting the first bond pad of the first semiconductor die and the second bond pad of the second semiconductor die; And, And a first solder bump electrically connected to the second bond pads. The method of claim 1, The first active layer, A first epitaxial layer made of a thin film grown using the first silicon wafer as a seed, and And a first device layer formed between the first epitaxial layer and electrically connected to the first bond pad. The method of claim 1, The second active layer, A second epitaxial layer made of a thin film grown using the first silicon wafer as a seed, and And a second device layer formed between the second epitaxial layer and electrically connected to the second bond pad. The method of claim 1, The first active layer and the second active layer are each, And the second surface is formed on the same plane as the third surface of the first silicon wafer. The method of claim 1, The first silicon wafer, The semiconductor package is formed thicker than the first active layer. The method of claim 1, The first silicon wafer, The semiconductor package is formed thicker than the second active layer. delete The method of claim 1, And a third semiconductor die electrically connected to the first solder bumps. The method of claim 8, A second silicon wafer having a first flat surface, a second surface that is flat as an opposite surface of the first surface, and a third surface connecting the first and second surfaces, The third semiconductor die, A third active layer having a first flat surface and a second surface perpendicular to the first surface, the third active layer being formed on the first surface of the second silicon wafer; A plurality of third bond pads formed on the first surface of the third active layer to be electrically connected to the third active layer; And, And a third passivation layer formed on the first surface of the third active layer and exposing the third bond pads. The method of claim 9, And the first solder bump is electrically connected to the third bond pad. The method of claim 9, And a fourth semiconductor die formed on the second surface of the second silicon wafer and electrically connected to the third semiconductor die. The method of claim 11, The fourth semiconductor die, A fourth active layer having a first flat surface and a second surface perpendicular to the first surface, and formed on a second surface of the second silicon wafer; A plurality of fourth bond pads formed on the first surface of the fourth active layer to be electrically connected to the fourth active layer; And, And a fourth passivation layer formed on the first surface of the fourth active layer and exposing the fourth bond pads. The method of claim 12, And a second through electrode formed to electrically connect the third bond pad and the fourth bond pad. The method of claim 13, And a second solder bump electrically connected to the fourth bond pad. The method of claim 9, The third active layer is, A third epitaxial layer made of a thin film grown using the second silicon wafer as a seed, and And a third device layer formed between the third epitaxial layer and electrically connected to the third bond pad. The method of claim 12, The fourth active layer, A fourth epitaxial layer made of a thin film grown using the second silicon wafer as a seed, and And a fourth device layer formed between the fourth epitaxial layer and electrically connected to the fourth bond pad. The method of claim 12, The third active layer and the fourth active layer are each, And the second surface is formed on the same plane as the third surface of the second silicon wafer. The method of claim 9, The second silicon wafer, The semiconductor package is thicker than the third active layer. The method of claim 12, The second silicon wafer, The semiconductor package is thicker than the fourth active layer. A sub surface having a flat first surface and a flat second surface as an opposite surface to the first surface, a plurality of first conductive patterns formed on the first surface, and a plurality of second conductive patterns formed on the second surface; straight; A first flat surface and a second surface that is flat as an opposite surface of the first surface, and includes a plurality of first bond pads formed on the first surface and a plurality of second bond pads formed on the second surface; A first semiconductor die mounted to the substrate; A conductive wire electrically connecting the first conductive pattern and the first bond pad; A first solder bump electrically connected between the second bond pad and the first conductive pattern; And, And an encapsulant surrounding an outer circumference of the first semiconductor die and the conductive wire among the first surfaces of the substrate. The first semiconductor die may include a first passivation layer formed on a first surface of the first semiconductor die to expose the first bond pads; And, And a second passivation layer formed on the second surface of the first semiconductor die to expose the second bond pads. delete The method of claim 20, And a solder ball electrically connected to the second conductive pattern. The method of claim 20, The substrate, And a conductive via that electrically connects the first conductive pattern and the second conductive pattern. The method of claim 23, The substrate, A first solder mask formed on the first surface of the substrate to cover a portion of the first conductive pattern, And a second solder mask formed on the second surface of the substrate to cover a portion of the second conductive pattern. The method of claim 20, And a first underfill formed between the first semiconductor die and the substrate to surround an outer circumference of the first solder bump. The method of claim 20, And a second semiconductor die electrically connected to the first semiconductor die. The method of claim 26, The second semiconductor die, A first flat surface and a second surface that is opposite to the first surface; A third bond pad formed on a first surface of the second semiconductor die and electrically connected to the first bond pad; And a third passivation layer formed on the first surface of the second semiconductor die and exposing the third bond pads. The method of claim 27, And a second solder bump electrically connected to the third bond pad. The method of claim 28, And a second underfill surrounding the outer periphery of the second solder bumps between the first semiconductor die and the second semiconductor die. The method of claim 27, The second semiconductor die, A fourth bond pad formed on a second surface of the second semiconductor die, And a fourth passivation layer formed on the second surface of the second semiconductor die to expose the fourth bond pads. A sub surface having a flat first surface and a flat second surface as an opposite surface to the first surface, a plurality of first conductive patterns formed on the first surface, and a plurality of second conductive patterns formed on the second surface; straight; A first flat surface and a second surface that is flat as an opposite surface of the first surface, and includes a plurality of first bond pads formed on the first surface and a plurality of second bond pads formed on the second surface A first semiconductor die mounted to the substrate; A first solder bump electrically connecting the first semiconductor die and the substrate; A first flat surface and a second surface that is opposite to the first surface, the second surface being flat and comprising a plurality of third bond pads formed on the first surface and a plurality of fourth bond pads formed on the second surface; A second semiconductor die electrically connected with the first semiconductor die; And, And a second solder bump electrically connecting between the first bond pad of the first semiconductor die and the third bond pad of the second semiconductor die. The method of claim 31, wherein And a first underfill surrounding the outer periphery of the first solder bumps between the first semiconductor die and the substress. The method of claim 31, wherein And a second underfill surrounding the outer periphery of the second solder bumps between the first semiconductor die and the second semiconductor die. The method of claim 31, wherein The first solder bumps, And a semiconductor package electrically connected between the second bond pad and the first conductive pattern. delete The method of claim 31, wherein The substrate, And a solder ball electrically connected to the second conductive pattern. The method of claim 31, wherein The substrate, And a conductive via that electrically connects the first conductive pattern and the second conductive pattern. The method of claim 37, wherein The substrate, A first solder mask formed on the first surface of the substrate to cover a portion of the first conductive pattern, And a second solder mask formed on the second surface of the substrate so as to cover a portion of the second conductive pattern. A first silicon wafer preparation step of preparing a first silicon wafer having a flat first surface and a second flat surface as an opposite surface to the first surface; Forming a first semiconductor die on a first surface of the first silicon wafer; A first silicon wafer backgrinding step of grinding the second side of the first silicon wafer; Forming a second semiconductor die on a second side of the ground first silicon wafer; A first through electrode forming step of forming a first through electrode electrically connecting a first bond pad formed on the first semiconductor die and a second bond pad formed on the second semiconductor die; And, And a first solder bump fusion step of fusion bonding the first solder bumps electrically connected to the second semiconductor die. The method of claim 39, The first semiconductor die forming step, Forming a first active layer on the first surface of the first silicon wafer, the first active layer having a flat first surface and including a first epitaxial layer and a first device layer; A first bond pad forming step of forming a plurality of first bond pads formed on a first surface of the first active layer to be electrically connected to the first device layer; And And a first passivation layer forming step of forming a first passivation layer formed on the first surface of the first active layer to cover the first bond pads. The method of claim 40, The second semiconductor die forming step, Forming a second active layer on the second surface of the first silicon wafer, the second active layer having a first flat surface and including a second epitaxial layer and a second device layer; A second bond pad forming step of forming a plurality of second bond pads formed on a first surface of the second active layer to be electrically connected to the second device layer; And, And a second passivation layer formed on the first surface of the second active layer to form a second passivation layer exposing the second bond pads. 42. The method of claim 41 wherein After the first solder bump fusion step, Taping the surface of the first solder bumps and the surface of the second passivation layer with tape; A first passivation layer patterning patterning the first passivation layer to expose the first bond pads; And, The tape removal step of removing the tape; Method of manufacturing a semiconductor package further comprising. 42. The method of claim 41 wherein The first through electrode forming step, After the second passivation layer forming step, And a conductive material is filled in the through hole penetrating between the first bond pad and the second bond pad.

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