KR100867546B1 - Analog to digital converter - Google Patents

Abstract

The present invention relates to an analog-to-digital converter having a high-speed conversion function to provide a high-speed conversion operation by reducing the delay time of the feedback loop in the sigma delta modulation scheme.

The present invention switches and stores an analog signal and a feedback analog signal according to a plurality of switching signals, and quantizes an integrated unit for integrating the stored analog signal, and an integrated analog signal from the integrated unit with a plurality of bits of digital signals. A quantization unit, a data weighted averaging unit for averaging the digital signal from the quantization unit according to a predetermined reference signal through a multi-step bit shifting process, and a current level of the digital signal from the data weighted averaging unit. And a DA converter converting the digital signal from the first register into a feedback analog signal by switching the digital signal from the first register according to a switching signal.

Analog to Digital Converter (ADC), Sigma-Delta Modulation

Description

Analog-to-digital converter {ANALOG TO DIGITAL CONVERTER}

1 is a block diagram showing a conventional analog-to-digital converter.

2 is a block diagram showing an analog-to-digital converter according to the present invention.

3 is a detailed configuration diagram of the integrating unit and the DA conversion unit employed in the analog-digital converter according to the present invention.

4 is a diagram showing a bit string of a data weighted averaging unit employed in an analog-digital converter according to the present invention.

5 is a graph showing signal timing of an analog to digital converter according to the present invention;

<Detailed description of the major symbols in the drawings>

100 ... Analog Digital Converter 110..Integral

111 ... first switch group 112 ... second switch group

113 ... 203 Switch group 114 ... Capacitor group

115.Integrator 120 ... Quantum

130 Data weighted averaging section 131 Shift section

131a ... the first shifter 131b ... the second shifter

131c ... 3rd shifter 132 ... Encoding

133.Adding part 134 ... Delaying part

135 ... second register section 140 ... first register section

150 ... DA converter 151 ... 4 switch group

s1 ... first switching signal s1d ... second switching signal

s2 ... third switching signal s2d ... fourth switching signal

ss1 ... second reference signal ss2 ... second reference signal

C0 ... 1st movement signal C1 ... 2nd movement signal

C2 ... Third travel signal

The present invention relates to an analog-to-digital converter having a high-speed conversion function, and more particularly, to an analog-to-digital converter having a high-speed conversion function to provide a high-speed conversion operation by reducing the delay time of the feedback loop in the sigma delta modulation.

In the field of broadband wired and wireless communication, an analog digital converter (ADC) is used to process an analog signal transmitted as a digital signal. These analog-to-digital converters employ Sigma-Delta modulation to process wideband signals.

Analog-to-digital converters employing sigma delta modulation can effectively improve the signal-to-noise ratio (SNR), but the signal-to-noise ratio is due to the nonlinearity of the internal DA converter that feeds back the output digital signal. Since the loss is increased, a data weighted averaging (DWA) circuit is employed to improve the nonlinear characteristics described above.

1 is a configuration diagram showing the configuration of a conventional analog-to-digital converter employing a data weighted averaging circuit.

Referring to FIG. 1, a conventional analog-to-digital converter includes an integrator 10 for integrating an analog signal in a predetermined voltage range and a quantizer 20 for quantizing the integrated analog signal from the integrator to a predetermined level.

The digital signal quantized from the quantization unit 20 is fed back to the integrator 10 through the DA converter 40 to feed back a portion of the digital signal to adjust the voltage level. In order to improve the nonlinear characteristics generated by the section 40, a data weighted averaging circuit 30 is employed.

The data weighted averaging circuit 30 includes a first latch unit 31, a shift unit 32, an encoder unit 33, an adder 34, and a second latch unit 35 from the quantization unit 20. Averaging the digital signal to the DA converter 40, thereby improving the non-linear characteristics of the DA converter 40.

However, the conventional analog-to-digital converter has a long feedback delay time for feeding back the digital signal from the quantizer 20 to the integrator 10 through the DA weighting circuit 30 through the data weighted averaging circuit 30. There is a problem that it is not easy to perform a high speed operation.

In order to solve the above problems, an object of the present invention is to provide an analog-to-digital converter having a high-speed conversion function to provide a high-speed conversion operation by reducing the delay time of the feedback loop in the sigma delta modulation scheme.

In order to achieve the above object, the analog-to-digital converter having a high-speed conversion function of the present invention is to switch and store the analog signal and the feedback analog signal in accordance with a plurality of switching signals, the integral unit for integrating the stored analog signal, and A quantization unit for quantizing the integrated analog signal from the integrator into a digital signal composed of a plurality of bits, a data weighted averaging unit for averaging the digital signal from the quantization unit through a multi-step bit shifting process according to a predetermined reference signal; A first register unit for converting the current level of the digital signal from the data weighted averaging unit to a preset current level according to a predetermined reference signal, and switching the digital signal from the first register unit according to a switching signal to DA converter converts feedback analog signal It is characterized by including.

In addition, the analog-to-digital converter having a high-speed conversion function of the present invention provides the integrating unit with first to third switching signals for switching the analog signal and the fed back analog signal, and the digital signal from the first register unit. A clock for providing a fourth switching signal to switch the DA and the first and second reference signals inverting the first and second switching signals to a first register unit and a data weighted averaging unit, respectively. It may further include wealth.

According to one embodiment of the invention, the first to third switch group having a plurality of switches each of the on and off switching of the analog signal in accordance with the first to third switching signal, and the first and second switch group A plurality of charging the analog signal and the fed back analog signal according to the on-switching, and discharging the charged analog signal according to the off-switching of the first and second switch groups and the on-switching of the third switch group, respectively And a capacitor group having a capacitor and an integrator for integrating the analog signal discharged from the capacitor group.

In addition, according to one embodiment of the present invention, the first register unit may perform the conversion operation after a rising section in which the first reference signal rises.

In addition, according to an embodiment of the present invention, the DA conversion unit has a fourth switch having a plurality of switches that are turned on and off according to the fourth switching signal to convert the digital signal from the first register unit into the feedback analog signal. The quantization unit may quantize the analog signal into an 8-bit digital signal.

According to an embodiment of the present invention, the data weighted averaging unit shifts each bit of the digital signal from the quantization unit, an encoding unit encoding the digital signal from the quantization into a binary digital signal, and A second register unit for transmitting first to third movement signals for controlling shifting of the shift unit according to a second reference signal, a binary digital signal of the encoding unit, and first to third movement signals of the second register unit; An adder may include an adder and a delayer configured to correct a transmission time difference between the signal from the adder and the second reference signal.

Accordingly, according to an embodiment of the present invention, the shift unit comprises: a first shifter for shifting each bit of the digital signal from the quantization by one digit according to the first shifting signal of the second register; A second shifter for shifting each bit of the digital signal from the first shifter by two digits in accordance with a negative second shift signal, and a digital shift signal from the second shifter in accordance with a third shift signal of the second register unit. It may include a third shifter for shifting each bit by four digits.

The second register unit may operate in a rising section in which the signal of the second reference signal rises.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

2 is a block diagram showing an analog-to-digital converter according to the present invention.

Referring to FIG. 2, the analog-to-digital converter 100 of the present invention includes an integrator 110, a quantizer 120, a data weighted averaging unit 130, a first register unit 140, and a DA converter 150. It includes.

First, the integrator 110 receives an analog signal and integrates the analog signal by switching the analog signal according to a switching signal. Accordingly, the integrator 110 may include a plurality of switches, a plurality of capacitors, and an integrator. A detailed configuration of the integrating unit 110 will be described later with reference to FIG. 3.

The quantization unit 120 converts the analog signal integrated from the integrator 110 into a digital signal of a predetermined level. The quantization unit 120 may quantize the integrated analog signal into a digital signal consisting of a plurality of bits. Preferably, the quantization unit 120 may quantize the integrated analog signal into a digital signal consisting of 8 bits. Accordingly, the quantization unit 120 may be a 9-level quantization unit. The digital signal may be a digital signal consisting of 8 bits, commonly referred to as a 'thermometer code'. Here, the 'thermometer code' means a digital signal that sequentially fills bit positions as the thermometer goes up.

The data weighted averiging (DWA) unit 130 receives an 8-bit digital signal from the quantizer 120 and shifts and averages each bit of the digital signal. Accordingly, the data weighted averaging unit 130 may include a shift unit 131, an encoding unit 132, a multiplication unit 133, a delay unit 134, and a second register unit 135.

The shift unit 131 may include first to third shifters 131a, 131b, and 131c for shifting each bit position of the 8-bit digital signal. Accordingly, the first shifter 131a shifts each bit of the 8-bit digital signal by one digit, and the second shifter 131b moves each bit of the 8-bit digital signal from the first shifter 131a. Are shifted by two digits, and the third shifter 131c shifts each bit of the 8-bit digital signal from the second shifter 131b by four digits.

 The second register unit 135 provides the first to third movement signals C0, C1, and C2 for controlling the first to third shifters 131a, 131b, and 131c, respectively, according to the second reference signal ss2. do. That is, the first shifter 131a moves each bit position of the 8-bit digital signal by one digit according to the first movement signal C0, and the second shifter 131b moves according to the second movement signal C1. Each bit position of the 8-bit digital signal from the first shifter 131a is shifted by two digits, and the third shifter 131c is 8 bits from the second shifter 131c according to the third shift signal C2. Each bit position of the formed digital signal is shifted by four digits.

The encoding unit 132 encodes the 8-bit digital signal from the quantization unit 120 into a binary digital signal.

The adder 133 adds the binary digital signal from the encoder 132 and the first to third moving signals from the second register unit 135.

The delay unit 134 corrects the transmission time difference between the signal added from the adder 133 and the second reference signal ss2. The delay unit 134 may be preferably composed of a plurality of inverters connected in series to correct the transmission time difference between the added signal and the second reference signal ss2, and more preferably, a single IC chip. have.

The first register unit 140 may drive a digital current averaged from the data weighted averaging unit 130 according to the first reference signal ss1 to drive the DA converter 150 and the integrator 110. The digital signal is converted into a digital signal and transmitted to the DA converter 150. Preferably, the data weighted averaging unit 130 may be composed of a plurality of inverters connected in series to convert the averaged digital signal, and more preferably may be composed of a single IC chip.

The DA converter 150 converts the digital signal from the first register unit 140 into an analog signal according to the fourth switching signal s2d. The converted analog signal is fed back to the integrator 110. Accordingly, the DA converter 150 may include a plurality of switches for switching the digital signal from the first register unit 140. A detailed configuration thereof will be described later with reference to FIG. 3.

The integrating unit 110 and the converting unit 150 operate according to the first to third switching signals s1, s1d and s2, and the fourth switching signal s2d, respectively. The register unit 135 operates according to the first reference signal ss1 and the second reference signal ss2, respectively.

Accordingly, the analog-to-digital converter 100 of the present invention includes a clock unit 160 for providing first to fourth switching signals s1, s1d, s2, and s2d and the first and second reference signals ss1 and ss2. ) May be further included.

3 is a detailed configuration diagram of the integrating unit and the DA converting unit employed in the analog-digital converter according to the present invention.

Referring to FIG. 3, the integrator 110 according to the first switching group 111 and the second switching signal s1d having a plurality of switches for switching on and off an analog signal according to the first switching signal s1. Complementary with the first and second switching groups 111 and 112 according to the second switch group 112 and the third switching signal s2 having a plurality of switches on and off switching in conjunction with the first switching group 111. It includes a third switch group 113 having a plurality of switches to switch normally.

In addition, the analog signal is charged according to the on switching of the first and second switch groups 111 and 112 and the analog signal charged according to the on switching of the third switch group 113 is added. And a capacitor group 114 having a plurality of capacitors for discharging, and further including an integrator 115 for integrating the discharged analog signal.

The integrator 115 may be a differential integrator, so that the first to third switch groups 111, 112, and 113 switch the analog signal Vin + and the analog signal Vin−, respectively.

The DA converter 150 may be configured as a fourth switch group 151 having a plurality of switches for switching the digital signal according to the fourth switching signal s2d.

4 is a diagram illustrating a bit string of a data weighted averaging unit employed in an analog-digital converter according to the present invention.

Referring to FIG. 4, the shift of the digital signal consisting of 8 bits processed by the shift unit 131 of the data weighted averaging unit 130 employed in the analog-to-digital converter 100 according to the present invention is shown.

5 is a graph showing signal timing of an analog-to-digital converter according to the present invention.

Referring to FIG. 5, the first to fourth switching signals s1, s1d, s2, and s2d of the analog-to-digital converter 100 according to the present invention, the shift unit 131, the first register unit 140 and The operation signal of the second register unit 135 may be checked.

Hereinafter, with reference to the drawings will be described in detail the operation and effect of the present invention.

2 to 5, in the analog-to-digital converter 100 according to the present invention, the integrator 110 integrates an analog signal.

More specifically, referring to FIG. 3, the first switch group 111 of the integrating unit 110 switches on the positive analog signal Vin + by switching according to the first switching signal s1.

Thereafter, the second switch group 112 is also switched on (on) like the first switch group 111. The second switch group 112 switches according to the second switching signal s1d, and the second switching signal s1d is a signal that delays the first switching signal s1.

This is because when the first switch group 111 and the second switch group 112 are turned off at the same time, a loss such as spike occurs in each switch.

The switched analog signals are respectively charged in the capacitors Cs1 to Cs8 of the capacitor group 114 (section A in FIG. 5). This is called a sampling section.

The charged analog signal is discharged according to the off switching of the first and second switch groups 111 and 112 and the on switching of the third switch group 113 (B section in FIG. 5). This time is called an integral section.

The discharged analog signal is integrated by the integrator 115.

The negative analog signal Vin- is also integrated as described above.

2 and 3, the integrated analog signals Vo and Vom are then quantized by the quantization unit 120 into digital signals having a predetermined level.

In this case, the quantization unit 120 quantizes the integrated analog signal into a digital signal according to the second switching signal s1d and the fourth switching signal s4d.

Preferably, the integrated analog signal is quantized into a 9-level digital signal. Accordingly, the digital signal may be a 8-bit digital signal.

The 8-bit digital signal is output to the outside and fed back to the data weighted averaging unit 130. More specifically, the 8-bit digital signal is fed back to the shift unit 131 and the encoding unit 132, respectively.

Next, the shift unit 131 shifts each bit position of the 8-bit digital signal according to the first to third moving signals C0, C1, and C2 from the second register unit 135.

4 and 5, first, in the shifting section of FIG. 5, the shift unit 131 shifts each bit position of the 8-bit digital signal.

Referring to FIG. 4, for example, a digital signal of '00000111' sequentially fills each bit in 1,2,3 places.

After that, when the digital signal of '00001111' is input, the digit is shifted and filled after the bit position occupied by the previous '00000111'. That is, each bit of '00001111' is sequentially filled in the fourth, fifth, sixth and seventh bit positions.

Next, when the digital signal of '00000111' is input, each bit of '00000111' is sequentially filled in the 8th, 1st, and 2nd bit positions.

Similarly, the digital signals of '00000001' and '00011111' are filled in for each bit by the above-described method.

Next, referring to FIG. 5, the shifter 131 initializes the shifters 131a, 131b, and 131c in the integration section B of the integration unit 110. At this time, the initialization fills each bit position with '1' in each of the shifters 131a, 131b, and 131c.

Thereafter, the 8-bit digital signal is converted into a binary digital signal through the encoding unit 132.

The binary digital signal is added to the first to third moving signals C0, C1, and C2 through an adder 133.

The added signal is fed back to the second register unit 135 to synchronize the transfer time of the first to third moving signals C0, C1, and C2 from the register unit 135 with the addition signal. In order to delay the added signal through the delay unit 134.

Next, the delayed signal is fed back to the second register unit 135. The second register unit 135 controls the first to third shift signals C0 and 3 to control the first to third shifters 131a, 131b, and 131c based on the delayed signal according to the second reference signal ss2. C1, C2).

At this time, the second register unit 135 performs an operation (④) after the rising section (②) of the second reference signal ss2.

Since the second reference signal ss2 is several times faster than the time of reaching the falling section by the internal capacitive element (not shown), the second register unit 135 has the second reference signal ss2. ) Can be operated after the rise, and the above operation can be performed at high speed.

Thereafter, the 8-bit digital signal shifted by the shift unit 131 is transmitted to the first register unit 140.

The first register unit 140 transfers a predetermined magnitude of current to the DA converter unit 150 to drive the fourth switch group included in the DA converter unit 150 to the 8-bit digital signal.

At this time, the first register unit 140 operates according to the first reference signal ss1, and performs an operation (③) after the first reference signal ss1 reaches the rising section ①.

Similarly to the operation of the second register unit 135, the first reference signal ss1 has several times faster time to reach the rising section than the time to reach the falling section, so that the first register unit 140 uses the first reference signal ( After ss1) rises, the above operation may be performed to perform the operation at a high speed.

Finally, the digital signal from the first register unit 140 is converted into an analog signal by the DA converter 150.

In this case, the DA converter 150 converts the digital signal from the first register unit 140 into an analog signal within the input ranges Vr + and Vr− of the analog signal.

3, the fourth switch group 151 included in the DA converter 150 performs the switching operation according to the fourth switching signal s2d. The switching operation is performed according to the logic signals sw1 to sw8 and ssw1 to ssw8 by the AND logical product of the signal s2d and the buffered digital signal.

That is, when the fourth switching signal s2d and the digital signal from the first register unit 140 are all '1', the switching is turned on and the fourth switching signal s2d and the first register unit 140 are turned on. When any one of the digital signals of '0' is switched off (off).

The fourth switch group 151 preferably has 32 switches because the digital signal is 8 bits, the analog input ranges are Vr + and Vr−, and the integrator 115 of the integrator 110 has a differential structure. Can be configured.

Accordingly, the fourth switch group 151 switches the digital signals from the first register unit 140 and transmits the digital signals to the capacitor group 114 of the integration unit 110. In this case, the third switch group 113 is switched off before the fourth switch group 151 to reduce switching losses such as spikes. The transmitted analog signal is integrated by the integrator 115 and transferred to the quantization unit 120.

Thereafter, the above-described operation is repeated to continuously convert analog signals to digital signals.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, but is defined by the claims below, and the configuration of the present invention may be modified in various ways without departing from the technical spirit of the present invention. It will be apparent to those skilled in the art that modifications and variations are possible.

As described above, according to the present invention, the feedback delay of the digital signal converted by synchronizing each operation signal of the analog digital converter, in particular, by operating the first register section and the second register section in the rising interval of the first and second reference signals. It is possible to provide a high speed conversion function by reducing the time.

Claims (9)

An integrating unit for switching and storing the analog signal and the feedback analog signal according to the plurality of switching signals, and integrating the stored analog signals; A quantizer for quantizing the integrated analog signal from the integrator into a digital signal composed of a plurality of bits; A data weighted averaging unit for averaging the digital signal from the quantization unit through a multi-step bit shifting process according to a predetermined reference signal; A first register unit for converting a current level of the digital signal from the data weighted averaging unit into a preset current level according to a predetermined reference signal; A DA converter converting the digital signal from the first register unit according to a switching signal and converting the digital signal into the feedback analog signal; And Providing the first to third switching signals for switching the analog signal and the fed back analog signal to the integrator, and for providing the fourth switching signal for switching the digital signal from the first register section to the DA conversion section. And a clock unit providing first and second reference signals inverting the first and second switching signals to a first register unit and a data weighted average unit, respectively. Analog to digital converter comprising a. delete The method of claim 1, wherein the integral part First to third switch groups having a plurality of switches to switch on and off the analog signals in accordance with the first to third switching signals; Charge the analog signal and the fed back analog signal according to on-switching of the first and second switch groups, respectively, and charge according to the off switching of the first and second switch groups and the on-switching of the third switch group, respectively. A capacitor group having a plurality of capacitors respectively discharging the analog signals; And An integrator for integrating the analog signals discharged from the capacitor group; Analog to digital converter comprising a. The method of claim 3, And the first register unit performs the conversion operation after a rising section in which the first reference signal rises. The method of claim 1, And the DA converter includes a fourth switch group having a plurality of switches configured to switch on and off according to the fourth switching signal to convert the digital signal from the first register into the feedback analog signal. converter. The method of claim 1, And the quantization unit quantizes the analog signal from the integrator into an 8-bit digital signal. The method of claim 6, wherein the data weighted averaging unit A shift unit for shifting each bit of the digital signal from the quantization unit; An encoding unit encoding the digital signal from the quantization unit into a binary digital signal; A second register unit configured to transmit first to third moving signals for controlling shifting of the shift unit according to the second reference signal; An adder for adding a binary digital signal of the encoding unit and first to third moving signals of the second register unit; And Delay unit for correcting the transmission time difference between the signal from the adder and the second reference signal Analog to digital converter comprising a. The method of claim 7, wherein the shift unit A first shifter for shifting each bit of the digital signal from the quantization by one digit according to a first moving signal of the second register unit; A second shifter for shifting each bit of the digital signal from the first shifter by two digits in accordance with a second movement signal of the second register unit; And A third shifter for shifting each bit of the digital signal from the second shifter by four digits in accordance with a third shifting signal of the second register part; Analog to digital converter comprising a. The method of claim 7, wherein And the second register unit performs the shift unit control operation after a rising section in which the second reference signal rises.

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