KR100861701B1 - Register renaming system and method based on value similarity - Google Patents

Abstract

The present invention relates to a register renaming system and method based on similarity of register values, wherein a register file is shared between instructions using a similarity of values stored in a register in a processor that performs out of order execution. The present invention relates to a register renaming system and method that can reduce the size of the circuit board and consequently increase the operating speed of the register file to improve the overall operating speed and performance of the processor. The present invention compares the source value and the result value in the execution unit to find a register having a similar value. Instead of deleting a multi-port CAM, that is, a 'value-matching cache', which has been used to search for the same value as in the prior art, By replacing and replacing a simple comparator in the execution unit, the configuration of the system becomes simpler and can be usefully applied to the next generation high performance processor.

Register, Renaming, Superscalar, Processor, Similarity-Based, Faster

Description

Register renaming system and method based on value similarity

1 is an overall configuration diagram showing a register renaming system of the present invention;

2 is a diagram showing the configuration of an execution unit having a similarity comparator in the register renaming system of the present invention;

3 is a view showing a field configuration of a modified result bus in the register renaming system of the present invention;

4 is a view showing a configuration of a command waiting queue changed according to the present invention;

5 is a view showing the configuration of a register map table modified by the present invention;

6 is a view showing an example of reducing physical register usage by sharing a physical register according to the present invention;

7 is a diagram for explaining register renaming.

<Explanation of symbols for the main parts of the drawings>

10: fetch unit 20: decoder

30: instruction wait queue 40: register map table

50: free list table 60: execution unit

62, 64: Similarity Comparator 70: Physical Register File

80: result bus

The present invention relates to a register renaming system and method, and more particularly to a register renaming technique that resolves interdependencies between source and destination operands of instructions in a processor that executes instructions in a non-sequential order.

Instructions in a computer program exchange data through logical registers (hereinafter referred to as logical registers). When a preceding instruction writes the result to a register, the subsequent instruction that needs the result reads the register and uses it as the source operand. Therefore, computer programs must be executed sequentially for correct operation. To execute commands sequentially, the trailing command always waits for all preceding commands to complete execution before executing.

As described above, in-order execution of instructions of a program in a processor of a computer system is a basic premise of program execution. Therefore, in the early processors, programs were executed sequentially, and in such a system, states of a processor including registers are written and read in the order specified in the program. In such a system, a register address in an instruction may have a one-to-one correspondence between an actual physical register (hereinafter referred to as a 'physical register'), and given a register address, a predetermined physical register may be written or You can read it.

Each instruction in a program is issued and executed as a functional unit only when there are no data dependencies, procedural dependencies, and resource conflicts. These dependencies, especially data dependencies, occur frequently during actual program execution, which limits the performance of the program.

If a preceding instruction can not be executed due to a dependency and finds and issues and executes a dependency that does not exist among the following instructions, the performance of the computer system can be improved. In systems with multiple functional units, the result of an instruction using an integer unit is faster than an instruction using a floating-point unit. Therefore, when a preceding instruction that uses the result of a floating-point operation as a source cannot be performed because of data dependencies, a later instruction that sources the result of an integer operation often does not have any dependencies. The performance of a computer system can be greatly improved if it can be executed before a preceding instruction.

The need for this out-of-order instruction issue has grown even more with the advent of superscalar processors that issue and execute multiple instructions in a single cycle. The superscalar architecture has an issue resource that can issue multiple commands simultaneously and a number of functional units that can execute these commands simultaneously. Because multiple instructions are executed at the same time, if resources cannot be issued due to data dependency, the resources that are wasted becomes very large and inefficient. For this reason, many superscalar architectures use out of order instruction issue methods to reduce resource waste and increase performance.

Out-of-order execution means that the processor processes the instructions in advance without processing them sequentially according to the program. If there are instructions that can be processed, the instructions are processed in advance, and each instruction is affected by the execution result of the preceding instruction. If the received data dependency, resource conflict in the process of processing the instruction does not occur, even the following instruction can be issued and processed by skipping the sequence. Such non-sequential execution can greatly improve the performance of the processor.

The non-sequential processor enables the execution of a subsequent instruction first even if the execution of the preceding instruction is not completed as described above when the latter instruction does not have a dependency through registers with the preceding instructions that have not yet been completed. There are three major dependencies between registers in processors that execute out of order instructions. 'Write after read (RAW)' dependency caused by a subsequent instruction reading a register value written by a preceding instruction, and 'Read after write (WAR)' dependent on a subsequent instruction writing to a register after the preceding instruction reads a specific register. Relationships, 'write after write' (WAW) dependencies that occur when preceding and following instructions write values to the same register. If one of these three dependencies is established between the preceding commands, the command can be executed only after all preceding commands with dependencies have completed. Among them, the 'write after read' dependency is indispensable in normal program flow, while the 'read after write' and 'write after write' dependency occurs during the reuse of finite resources, logical register addresses. It's a kind of false dependency. The technique developed to solve this false dependency is register renaming.

Moudgill et al. Proposed the basic structure of a register renaming system using a single physical register file, which is now widely used in superscalar processors [Moudgill et al., "Register Renaming and Dynamic Speculation: An Alternative Approach". , Proceedings of the 26th Intl., Symposium on Microarchitecture, 1993, IEEE, pp.203-213.].

Register renaming resolves false dependencies by not reusing logical register addresses by allocating a new physical register to the destination logical register of all instructions that write a result to the register (see FIG. 7). Register renaming uses a physical register file with more physical registers than the logical registers defined by the instruction set architecture. The number of physical registers is determined to be equal to the maximum number of instructions that can be accommodated simultaneously in the processor pipeline. When an instruction is fetched from memory, the decode stage of the pipeline allocates one empty physical register to the destination register for each instruction and places it in the register map table indicating which physical register the destination logical register for that instruction is allocated. Record the newly allocated physical register address. An empty physical register address can be found by looking in a free list table that indicates whether each physical register is currently in use or waiting for a new allocation request. At the same time, a search of the register map table using the source logical register address of an instruction tells which physical register the logical register is allocated to. This renaming process converts both the source and destination registers of the instruction into physical registers, while the 'write after read' dependency remains the same, but since all destination registers have been assigned to the new physical register, The 'write after write' dependency disappears. Put the converted instruction in the instruction wait queue and wait for all the preceding instructions with 'write and read' dependencies on all the source registers of the instruction to complete execution. If the above conditions are met, the instruction becomes executable regardless of the completion status of the preceding instructions, and is also sent to the execution unit to read and execute the physical register file using the source physical register address, and then specified by the destination physical register address. Record the results in place.

Instructions executed out of order are retired from the processor sequentially after all preceding instructions have completed execution, with the destination physical register of that instruction also retired. The evicted physical register is reused to rename the newly fetched trailing instruction.

An active instruction refers to an instruction that is input to an instruction waiting queue and then completes execution and is sequentially evicted. In most instruction set architectures, instructions have a maximum of one destination register, so to allocate one destination physical register to every active instruction, there must be as many physical registers as there are active instructions in the physical register file. However, the physical register file produced by the multi-port SRAM tends to be slower as the number of entries increases. Therefore, if the processor is built in the direction of increasing the number of active instructions, such as increasing the size of the instruction wait queue or increasing the pipeline speed to increase the performance of the processor, the speed due to the increase in the number of entries in the physical register file Degradation problem occurs. Register sharing technology has been developed to solve this problem.

Jourdan et al. Proposed a technique that improves Moudgill's renaming system to integrate and share multiple physical registers with the same value, thereby reducing the size of the physical register file and speeding up its operation. [Jourdan et al., "A Novel Renaming Scheme to Exploit value Temporal Locality through Physical Register Reuse and Unification ", 31st Annual ACM / IEEE International Symposium on Microarchitecture, pp. 216-225, 1998].

Register sharing technology is a technique for reducing the number of physical registers required by renaming by sharing physical registers having the same value as one physical register. The process of fetching the instruction and decoding it into the instruction wait queue is the same as the general renaming described above. Register sharing technology uses a register cache to store recently generated values as a result of the execution of instructions and the physical register address where they are stored. When an instruction completes its execution in an execution unit, the result is retrieved from the instruction cache. If the same value is found in the instruction cache, you can get the physical register address where it is stored. Since the result of the currently executed instruction is the same as the value retrieved from the register cache, the corresponding value is not written to the destination physical register of the currently executed instruction. Instead, it changes the destination physical register address of the current instruction to the physical register address retrieved from the register cache and passes the original destination physical register address and the changed destination physical register address to subsequent instructions. Subsequent instructions compare their source physical register address with the original physical register address passed in and replace their source physical register address with the modified physical register address if both addresses are equal. At the same time, the original destination physical register is evicted immediately. If the result value produced by a series of instructions is the same, the first instruction that stores the result continues to occupy the physical register allocated by the decode stage, but subsequent instructions are their destination physical registers with the physical register where the value is stored first. By changing the address, the physical register allocated at the decode stage can be immediately retired. As a result, the number of physical registers required by a processor supporting a certain number of active instructions can be reduced, and the reduction of the number of physical registers has the effect of improving the operation speed of the physical register file.

However, since more physical registers will be required in accordance with the development trend of the processor, improvement of the prior art is required to satisfy the requirements without deterioration in speed in the next generation of high performance processors. In the prior art, by integrating and sharing a plurality of physical registers having the same value, the physical register consumes less, the size of the register file is reduced, and the operation speed is increased. However, to make the operation speed faster, it is necessary to reduce the number of registers further by sharing more registers, and thus there is room for improvement in applying the prior art to the next generation high performance processor. In addition, a kind of multi-port Content Addressable Memory (CAM) called 'value-matching cache' is used to retrieve the same value and share the register with the same value ["Register Renaming to Optimize Identical Register Values", US Patent 6505293 B1 (2003.1.7)], 'value-matching cache' is a CAM with many ports, which is large in size and slow in operation. This increases the length of the pipeline, causing a decrease in performance.

Therefore, the present invention has been invented to solve the above problems, and the present invention improves the existing register renaming method which is essentially used in a superscalar and multithreaded (SMT) processor that performs out of order. The purpose is to improve the operation speed and performance by using a smaller number of physical registers than the conventional method.

In particular, by sharing several physical registers with similar values into one physical register and retiring the rest, a higher performance superscalar with higher physical register requirements is achieved by further reducing physical register requirements compared to the prior art which shares physical registers with the same value. And to improve the operating speed of a multi-threaded processor.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

In order to achieve the above object, according to the present invention, when an instruction is fetched from a fetch unit, the present invention searches the following free list table and allocates a physical register to a destination address of the instruction, and assigns the physical register address assigned to the instruction to A decoder for writing to an entry in the following register map table corresponding to the original destination address; A comparator that compares the bit strings of the result operand and the source operand after executing the instruction in an execution unit and determines that the result operand and the source operand are similar when the upper L bits of the total M bits of the two values are the same; The original destination physical register address of the current instruction, the physical register address of the source operand determined to be similar, and the lower ML bits of the result value, together with a register change valid bit that is true if the comparator determines that similarity is output. A result bus for transferring the difference value information between the result value and the source value corresponding to the register map table, the instruction waiting queue, and the free register list from the execution unit; A register map table for changing a physical register mapping of an entry that matches the contents of the result bus while maintaining the latest physical register address currently mapped for each register; An instruction waiting queue for storing a decoded instruction, a source physical register address, and an original destination physical register address while changing a source physical register address of an entry that matches the contents of the result bus; With one entry for each physical register, it indicates whether the corresponding physical register is occupied by the currently running instruction or whether it can be used for renaming a new instruction and how many instructions result in that physical register. It provides a register renaming system based on the similarity of register values, including a pre-list table consisting of a counter indicating whether to share a physical register.

Preferably, the execution unit reads a physical register file using a source physical register address, and reads a lower ML bit value of a value read from a register file in advance when the instruction of the instruction waiting queue becomes executable. The source offland may be obtained by substituting the stored difference value.

In addition, the source operand field of the instruction waiting queue may include a difference value valid bit that is true when the register change valid bit of the data field transferred through the result bus becomes true, and a result bus. It has a difference value field for storing the difference value transmitted through.

Each logical register entry of the register map table may include a difference value valid bit that is true when the register change valid bit of the data field transferred through the result bus becomes true, and a result bus. It characterized in that it has a difference value field for storing the difference value transmitted through.

When the instruction is fetched from the fetch unit, the decoder searches the free list table to find a physical register whose entry has a counter value of '0', assigns it to the destination physical register address of the corresponding instruction, and corresponds to the allocated physical register. Increment the counter value of the free list table entry to '1'; The free list table receives the information of the result bus, decrements the counter value of the physical register entry pointed to by the original destination physical register address by '1', and changes it to '0' indicating the free state of the corresponding physical register. The counter value of the entry corresponding to the source physical register address is increased to '1' indicating a state occupied by the currently operating instruction.

When the physical register is accompanied by the retirement of the instruction, the counter value of the free list table entry of the corresponding physical register is decreased by '1' to be changed to '0' indicating the free state.

Meanwhile, in the present invention, (a) when an instruction is fetched from a fetch unit, the decoder searches a free list table to allocate a physical register to a destination address of the corresponding instruction, and replaces the physical register address assigned to the instruction with the original destination address of the instruction. Writing to a register map table entry corresponding to the corresponding entry; (b) if the execution is completed after the instruction is registered in the instruction waiting queue, comparing the execution result value and the source operand value after executing the instruction in a similarity comparator of the execution unit to determine whether or not the similarity; (c) if the upper L bits of the total M bits of the two values are the same, it is determined that there is similarity, so that the execution unit is the original destination physical register address assigned in the decode step, the physical register of the source operand determined to be similar; Transferring the difference between the result value and the source value corresponding to the address and the lower ML bits of the result value to the instruction wait queue, the register map table, and the free register list through the result bus; (d) if the information is transferred to the instruction wait queue, the register map table, and the free register list via the result bus, performing a register change; providing a register renaming method based on the similarity of register values do.

Preferably, in the step (d), if the source physical register address of the following instruction registered in the instruction waiting queue and waiting and the original destination physical register address on the result bus match, the physical register of the source operand of the subsequent instruction Change the address to the physical register address of the source operand on the result bus, store the difference on the result bus in the difference value field provided in the source operand field of the instruction wait queue and make the difference valid bit true. Characterized in that.

Further, in the step (d), if a match is found by searching an entry of a register map table having a value matching the original destination physical register address on the result bus, the physical register address of the corresponding map table entry on the result bus is found. Change to the physical register address of the source operand, and store the difference value on the result bus in the difference value field provided in the map table entry and make the difference value valid bit true.

Also, in step (a), when the instruction is fetched from the fetch unit, the decoder searches the free list table to find a physical register whose entry has a counter value of '0', and assigns it to the destination physical register address of the corresponding instruction. Increment the counter value of the free list table entry corresponding to the registered physical register to '1'; In step (d), the free list table receives the information of the result bus and decrements the counter value of the physical register entry pointed to by the original destination physical register address by '1' to '0' indicating the free state of the corresponding physical register. At the same time, the counter value of the entry corresponding to the source physical register address on the result bus is increased to '1' indicating the state occupied by the currently operating instruction.

In the subsequent instruction retirement step, when the retirement of a physical register accompanying the retirement of the instruction is performed, the counter value of the free list table entry of the corresponding physical register is decremented by '1' to be changed to '0' indicating the free state. It features.

The execution unit reads a physical register file using a source physical register address and stores a lower ML bit value of a value read from a register file in advance when the instruction in the instruction waiting queue is executed and delivered. The source offland may be obtained by substituting the difference.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is an overall configuration diagram illustrating the register renaming system of the present invention.

As shown here, the register renaming system of the present invention compares the bit strings of the source operand and the result operand in the execution unit 60 so that the source operand and the result operand are similar when the upper L bits of the two values are the same. Comparators 62 and 64 for determining that there is; The original result physical register address of the current instruction (original destination physical register address), the physical register address of the source operand that is determined to be similar to the result when the comparator 62, 64 determines that similarity is output. A result bus 80 for transferring the 64-L bit value between the source value and the result value to the instruction waiting queue 30, the register map table 40, and the free list table 50; A register map table (40) capable of changing the physical register mapping of an entry that matches the contents of the result bus (80) while maintaining the latest physical register address currently mapped for each architectural register; An instruction waiting queue (30) capable of changing a source physical register address of an entry that matches the contents of the result bus (80) while retaining a decoded instruction, a source physical register address, and a result physical register address; It has one entry for each physical register and indicates whether the corresponding physical register is occupied by the currently running instruction or whether it can be used for renaming a new instruction. Several instructions return the corresponding physical register. By having a pre-list table (50) consisting of a counter indicating whether or not to share, the physical register requirements can be reduced compared to the general renaming, it is configured to increase the operation speed of the physical register file (70).

In the prior art, each execution unit 60 uses a register cache that stores up to N result values of recently executed instructions to find a physical register having the same value as the result of the instruction that is currently executed. The register cache is a type of Content Addressable Memory (CAM) that must be connected to all execution units 60 in the processor, which has the disadvantage of causing significant search latency.

In contrast, the present invention uses the comparators 62 and 64 in the execution unit 60 without using the above-described memory unit to compare the source register values of the instructions currently being executed with the execution result values. Since the source register values and result values are directly compared within the execution unit 60, all execution units 60 do not need to access a centralized history, such as one content retrieval memory, and no memory-related delay occurs. In the prior art in which a physical register having the same value is detected, the probability that the source register value and the result value are the same is extremely limited. Therefore, a centralized history memory such as a register cache is used, but the present invention detects similar values. Even when detected together, similar values can be detected with high probability. In the present invention, the case where two values are similar when the length of the register is the total M bits is defined as 'the upper L bit value of the total M bits of the two values is the same'. In this case, the lower M-L bits (when the total 64 (M = 64) bits are 64-L bits) may be the same or different. In the general instruction set, there are two source registers of instructions, so the execution unit 60 uses two comparators 62 and 64 having a length of L bits.

2 is a diagram showing the configuration of an execution unit 60 having similarity comparators 62 and 64 in the register renaming system of the present invention.

If similarity is found between the two values in execution unit 60, the destination physical register address of the instruction is changed to the source physical register address determined to be similar, and the difference (lower ML bit) between the two values is passed to the subsequent instructions. To pass. After completing this process, the original destination physical register of the instruction can be immediately retired. Changing the destination physical register address of an instruction affects subsequent instructions that use that register as a source. At this time, if the currently executing instruction that generates the result is a 'provider', and a trailing instruction that uses this result as a 'consumer', in order for the consumer to read the source operand correctly, the change of the destination physical register address of the provider instruction and The difference must be passed. Some of the consumers may already be decoded and placed in the instruction wait queue 30, and some may later be fetched and renamed. Thus, physical register change information must be passed to the instruction wait queue 30 and the register map table 40 for later renamed instructions. This information must also be communicated to the free list table 50 involved in the physical register allocation and retirement. This physical register change information is passed through the result bus 80.

In a general renaming system, the result bus 80 serves to inform the consumers that the execution of the instruction has been completed and write the result value in the physical register file 70. In the present invention, since the physical register change information must be transmitted in addition to the basic role, some additional information is inserted.

FIG. 3 is a view showing the field configuration of the modified result bus 80 in the register renaming system of the present invention (hereinafter, reference numerals of each component refer to FIGS. 1 and 2). As shown therein, the information transferred from the execution unit 60 to the instruction waiting queue 30, the register map table 40 and the free list table 50 via the result bus 80, i.e., data on the result bus. It includes the valid bits, the original physical register address, the register change valid bit, the new physical register address, and the difference value (lower ML bit value).

The valid bit indicates that the information carried on the result bus 80 is valid. If the valid bit is 'false', the data on that result bus 80 is ignored. The original physical register address is also present in the general renaming system, indicating that the execution of an instruction that uses that physical register as the destination physical register is complete. The register change valid bit is activated when the result of the provider instruction is determined to be similar to one of the source values of the provider instruction by the comparators 62 and 64 of the execution unit 60 driving the corresponding result bus 80 ( set). That is, the original physical register must be retired immediately, and all consumer instructions that use this physical register as a source must receive the difference and the new physical register address passed through an additional field of the result bus 80 and use it as the source operand. .

4 is a view showing the configuration of the instruction waiting queue 30 changed according to the present invention (hereinafter, reference numerals of each component refer to FIGS. 1 and 2). Subsequent instructions waiting in the instruction wait queue 30 have a source physical register address, and each instruction compares its source physical register address with the physical register address of the result bus 80 and, if the two addresses are the same, Recognize that the source operand is available. These instructions become consumer instructions that use that physical register as a source. If all the source operands of the instruction are marked as available through this process, the instruction becomes executable. This process is described as waking up the waiting source register. When the register change valid bit is enabled, the source register is awakened and the corresponding source register is changed to a new physical register address on the result bus 80, and the difference value on the result bus 80 is changed to the source of the instruction wait queue 30. It is stored in the difference value auxiliary field provided in the operand field and activates the difference value valid bit. When the instruction having the changed source operand field is made executable and passed to the execution unit 60, the execution unit 60 reads the physical register file 70 using the source physical register address and register file 70. The source ML operand is obtained by substituting the low ML bit of the value read from) with the previously stored difference value.

The consumer instruction may be in the instruction wait queue 30 when the provider instruction produces a result in the execution unit 60 and may be fetched later and renamed after the next cycle. The newly fetched instruction retrieves the register map table 40 at the decode stage and converts the source logical register address into a source physical register address. Thus, the register map table 40 must also be updated using information from the result bus 80 in order for the consumer instructions to be renamed later to correctly receive the changed physical register address in response to the detection of the similarity of the provider instructions.

5 is a view showing the configuration of the register map table 40 modified according to the present invention (reference numerals of each component refer to FIGS. 1 and 2). The general register map table 40 is a table showing which physical registers are mapped to each logical register, and has one physical register address for each entry corresponding to each logical register. Subsequent consumer instructions also have a status bit indicating whether the physical register is currently available. This status bit is updated via the result bus 80 as well as the available bits in the instruction wait queue 30. In the present invention, since the physical register address changed by the similarity detection is transferred to the new physical register address field and the difference value field of the result bus 80, the difference value field must also be added to the register map table 40. According to the contents of the result bus 80, the status bit of the register map table 40 is updated, and if the register change valid bit of the result bus 80 is enabled, the physical register address of the map table is converted into the result bus ( Change to the new physical register address of 80), store the difference value of the result bus 80 in the difference value field, and enable the difference value valid bit.

In the prior art, the free list table 50 has one entry for each physical register, and the program may be used for renaming subsequent instructions because the physical register is allocated or not assigned as the destination address of the instruction. Indicates if it is free. Thus, the free list table 50 is composed of one bit of information per entry. However, in the present invention, since a single physical register can be shared and used as a destination address of several instructions, the free list table 50 must keep track of how many instructions the corresponding physical register is allocated. Therefore, the free list table 50 in the present invention is composed of one counter entry per one physical register. The counter is incremented when the physical register is assigned to the destination address of the instruction at the decode stage and when similarity is found and shared in the execution unit 60. In other words, the free list table 50 entry corresponding to the new physical register address of the result bus 80 is incremented. The physical register is also evicted together when the instructions which have completed execution are sequentially evicted, and the free list table 50 entry corresponding to the evicted physical register is decremented. Also, when similarity is found in the execution unit 60 and the original destination physical register is retired, the corresponding entry counter value of the free list table 50 is decremented. That is, the free list table 50 corresponding to the original physical register address of the result bus 80 is decremented by one if the register change valid bit is valid. If the counter value of the free list table 50 is 0, the corresponding physical register is free and may be used for renaming a newly fetched instruction.

Hereinafter, the renaming process according to the present invention will be described in more detail.

The component operates in the following process. When the instruction is fetched from the fetch unit 10, the renaming is performed at the decode stage of the pipeline. In the renaming process, the decoder (renaming unit) 20 allocates a physical register to a destination address of an instruction, searches the free list table 50 to find a physical register having a value of '0', Used as the destination address. The value of the free list table 50 entry corresponding to the physical register assigned to the instruction is increased to '1', and the physical register address assigned to the instruction is recorded in the map table entry corresponding to the instruction's original architectural destination address. do. The renamed command is registered in the command wait queue 30 and waits for execution. After the execution is completed, the similarity detection step is performed. Upon completion of the execution of the instruction, execution unit 60 compares the execution result value with the source operand value using similarity comparators 62 and 64. If the comparison finds similarity, the original destination physical register address assigned to the result bus 80 in the decode step, the physical register address of the source operand (new physical register address) detected as having a similar value, and the lower ML of the result value. The difference value corresponding to the bit is loaded on the result bus 80 and the register change valid bit is turned on and then transmitted. When the information is loaded on the result bus 80 and arrives at the instruction waiting queue 30, the register map table 40, and the free list label, a register change step is performed. The instructions registered in the instruction wait queue 30 compare the physical destination address of their source operand with the original destination register address of the resulting bus 80. If the comparison result matches, the corresponding source operand is changed to a new physical register address, and the difference value of the result bus 80 is stored in the difference value field provided in the source operand field of the instruction wait queue 30. Register map table 40 retrieves a map table entry having a value that matches the original destination physical register address of result bus 80. If a match is found, the entry is changed to a new physical register address, and the difference value field of the result bus 80 is stored in the difference value field provided in the map table entry. The free list table 50 receives the information of the result bus 80, and decrements the free list entry value of the physical register pointed to by the original destination physical register address by '1', and this value becomes '0' as a result. The physical register is in a free state that can be used for renaming subsequent instructions. In addition, the entry value corresponding to the new physical register address is incremented by '1' to indicate that another instruction has been added to use that register as the destination address. The register change step described above is performed in parallel with a writeback pipeline step of writing a result value to an actual physical register. As a result of the register change step, one additional instruction is mapped to the new physical register, while the original physical register is freed, thereby increasing the number of physical registers available for renaming in the processor. Subsequent retirement of the instruction is performed in the same manner as a general register renaming technique, and when retiring a physical register accompanying the retirement of the instruction, the value of the free list table 50 entry of the corresponding physical register is decreased by '1'.

Hereinafter, an example of a renaming process according to the present invention will be described.

6 is a view illustrating an example of reducing physical register usage by sharing a physical register according to the present invention. The first instruction, i.e. instruction i, loaded hexadecimal 0x0000000012345600 into the physical register P41. The next command i + 1 adds hexadecimal 0x0a to P41. The original instruction i + 1 assumes that P15 is allocated to the destination physical register at the decode stage. The result of executing the command is 0x000000001234560a in hexadecimal. Comparing this value with the source register value P41, we can see that the lower 8 bits are different but the upper 56 bits are the same. In other words, the execution result of this instruction is the same as the value held in the source physical register P41. Thus, this result does not need to be stored in a separate destination physical register P15. Instead, change the destination physical register number of command i + 1 to P41, and send the difference between the two values, 0x0a, through the result bus 80 to subsequent commands. The result bus 80 contains P15 as the original destination physical register number, P41 as the new destination physical register number, and 0x0a as the difference value so that the instruction wait queue 30, register map table 40, and free list table ( 50). The trailing command i + 2 is in the command wait queue 30 and is a consumer using the result generated by the command i + 1, that is, P15 as the source physical register. When the above-described data is loaded on the result bus 80 and reaches the command wait queue 30, the command wait queue 30 receives the source physical register number of the instruction i + 2 and the original destination physical register number of the result bus 80. Compare The comparison confirms that it is equal to one of the source physical registers of the instruction i + 2. Therefore, as the corresponding source physical register is switched to the available state, the source physical register number is changed to P41, and the difference value 0x0a is stored in the difference value field of the instruction wait queue 30. Since the physical register address change operation for a subsequent consumer instruction is complete, the original destination physical register of instruction i + 1 is immediately retired. If instruction i + 2 also produces a value similar to that of the source physical register, P59, the original destination physical register of instruction i + 2, is also evicted after the above process. As a result, the decode stage allocated a total of three physical registers, one for each of the three instructions, but depending on the result of the instruction, the three instructions share one physical register and the other two immediately retire, so that only one physical register is valid. Command execution is possible.

As described above, according to the register renaming system and method based on the similarity of register values according to the present invention, by using less physical registers in a processor performing out of order than conventional renaming method This improves register renaming efficiency and speeds up the operation of physical register files, improving the speed and performance of the entire processor.

Renaming requires a physical register file with many entries. In the present invention, the number of entries in the register file can be reduced by allowing the physical registers to be shared among instructions using similarity of values stored in the registers. In particular, by integrating and sharing registers with similar (lower 8 bits different) values, more registers can be shared, resulting in a reduction in the number of physical registers resulting in increased operation speed. By reducing the register file size of high-performance processors, faster operation is possible and higher clock frequencies can be used to improve performance.

In addition, the present invention compares the source value and the result value in the execution unit to find a register having a similar value. Instead of deleting a multi-port CAM, that is, a 'value-matching cache' used to search for the same value as in the prior art, The configuration can be made simpler by attaching and replacing a simple comparator in the execution unit.

The technique of the present invention is a technique that can reduce the additional hardware and further improve the effect compared to the prior art, it can be usefully applied to the superscalar and SMT processor that uses register renaming for performing out of order instructions. As more and more physical registers will be required according to the development trend of the processor, the technique of the present invention may be usefully applied to the next generation high performance processor.

Claims (12)

When an instruction is fetched from the fetch unit, the following free list table is searched to assign a physical register to the destination address of the instruction, and the physical register address assigned to the instruction corresponds to the entry in the following register map table corresponding to the instruction's original destination address. A decoder to write to; A comparator that compares the bit strings of the result operand and the source operand after executing the instruction in an execution unit and determines that the result operand and the source operand are similar when the upper L bits of the total M bits of the two values are the same; The original destination physical register address of the current instruction, the physical register address of the source operand determined to be similar, and the lower ML bits of the result value, together with a register change valid bit that is true if the comparator determines that similarity is output. A result bus for transferring the difference value information between the result value and the source value corresponding to the register map table, the instruction waiting queue, and the free register list from the execution unit; A register map table for changing a physical register mapping of an entry that matches the contents of the result bus while maintaining the latest physical register address currently mapped for each register; An instruction waiting queue for storing a decoded instruction, a source physical register address, and an original destination physical register address while changing a source physical register address of an entry that matches the contents of the result bus; It consists of one counter entry per one physical register, and the counter value of the counter entry indicates whether the corresponding physical register is occupied by a currently running instruction or can be used for renaming a new instruction. A free list table configured to indicate how many instructions share the corresponding physical register with the resulting physical register; A register renaming system based on the similarity of register values, including. The method according to claim 1, The execution unit reads a physical register file using a source physical register address when the instruction in the instruction waiting queue becomes executable and delivers the difference, and stores the lower ML bit value of the value read from the register file in advance. A register renaming system based on the similarity of register values characterized in that a source offland is obtained by substituting a value. The method according to claim 1, The source operand field of the instruction wait queue may include a difference value valid bit that is true when the register change valid bit of the data field transferred through the result bus becomes true and a result bus. A register renaming system based on the similarity of register values, characterized by having a difference value field storing the passed difference value. The method according to claim 1, Each logical register entry of the register map table may include a difference value valid bit that is true when the register change valid bit of the data field transferred through the result bus becomes true, and a result bus. A register renaming system based on the similarity of register values, characterized by having a difference value field for storing the difference passed through. The method according to claim 1, When the instruction is fetched from the fetch unit, the decoder searches the free list table to find a physical register whose entry has a counter value of '0', assigns it to the destination physical register address of the corresponding instruction, and at the same time, the free register corresponding to the allocated physical register. Increment the counter value of the list table entry to '1'; The free list table receives the information of the result bus, decrements the counter value of the physical register entry pointed to by the original destination physical register address by '1', and changes it to '0' indicating the free state of the corresponding physical register. A register renaming system based on the similarity of register values, wherein a counter value of an entry corresponding to a source physical register address is incremented to '1' indicating a state occupied by an instruction in operation. The method according to claim 5, In the retirement of a physical register accompanied by the retirement of the instruction, the counter value of the free list table entry of the corresponding physical register is decreased by '1' and changed to '0' indicating a free state. Based register renaming system. (a) When an instruction is fetched from the fetch unit, the decoder retrieves the free list table, allocates a physical register to the destination address of the instruction, and maps the physical register address assigned to the instruction to the register destination table of the instruction's original destination address. Writing to an entry; (b) if the execution is completed after the instruction is registered in the instruction waiting queue, comparing the execution result value and the source operand value after executing the instruction in a similarity comparator of the execution unit to determine whether or not the similarity; (c) if the upper L bits of the total M bits of the two values are the same, it is determined that there is similarity, so that the execution unit is the original destination physical register address assigned in the decode step, the physical of the source operand determined to be similar. Transferring a difference value between a result value and a source value corresponding to the register address and the lower ML bits of the result value to the instruction waiting queue, the register map table, and the free register list through the result bus; (d) if the information is transferred to an instruction waiting queue, a register map table, or a free register list through the result bus, performing a register change; Register renaming method based on the similarity of register values, including. The method according to claim 7, In step (d), if the source physical register address of the subsequent instructions registered in the instruction waiting queue and the original destination physical register address on the result bus match, the physical register address of the source operand of the subsequent instruction is determined as the result. Change to the physical register address of the source operand on the bus, and store the difference value on the result bus in the difference value field provided in the source operand field of the instruction wait queue, and at the same time, make the difference valid bit true. Register renaming method based on similarity of register values The method according to claim 7, In step (d), if a match is found by searching an entry of a register map table having a value that matches the original destination physical register address on the result bus, the physical register address of the corresponding map table entry is the source on the result bus. Based on the similarity of the register values, changing to the physical register address of the operand and storing the difference value on the result bus in the difference value field provided in the map table entry while making the difference valid bit true. Register renaming method. The method according to claim 7, In the step (a), when the instruction is fetched from the fetch unit, the decoder searches the free list table to find a physical register whose entry has a counter value of '0', and assigns it to the destination physical register address of the corresponding instruction. Increment the counter value of the free list table entry corresponding to the physical register to '1'; In step (d), the free list table receives the information of the result bus and decrements the counter value of the physical register entry pointed to by the original destination physical register address by '1' to '0' indicating the free state of the corresponding physical register. The register value based on the similarity of register values, wherein the counter value of the entry corresponding to the source physical register address on the result bus is incremented to '1' which indicates the state occupied by the currently running instruction. Naming method. The method according to claim 10, In the subsequent instruction retirement step, upon retirement of the physical register accompanied by the retirement of the instruction, the counter value of the free list table entry of the corresponding physical register is decreased by '1' to be changed to '0' indicating the free state. Register renaming method based on similarity of register values. The method according to claim 7, The execution unit reads a physical register file using a source physical register address when the instruction in the instruction waiting queue becomes executable and delivers the difference, and stores the lower ML bit value of the value read from the register file in advance. A register renaming method based on similarity of register values, wherein the source offland is obtained by substituting the values.

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