KR100857826B1 - Power network circuit adopting zigzag power gating and semiconductor device including the same - Google Patents

Abstract

A power network circuit adopting zigzag power gating and a semiconductor device including the same are provided to be used easily in implementing semi-custom scheme on the basis of a conventional standard cell as having low power consumption. At least one pair of first rails(1000) comprises a power supply voltage line(1200) supplying a power supply voltage and a virtual base voltage line(1300) connected to a base voltage line of another rail pair through a first power gating circuit(1100). At least one pair of second rails(2000) comprises a virtual power supply voltage line(2200) connected to a power supply voltage line of another adjacent rail pair through a second power gating circuit(2100) and a base voltage line(2300) supplying a base voltage. The first power gating circuit is a NMOS(N-channel Metal -Oxide Semiconductor) transistor switching the connection of the base voltage line and the virtual base voltage line of the adjacent rail pair, in response to an inversion signal of a sleep mode control signal.

Description

Power network circuit using zigzag power gating and semiconductor device including the same {POWER NETWORK CIRCUIT ADOPTING ZIGZAG POWER GATING AND SEMICONDUCTOR DEVICE INCLUDING THE SAME}

1 is a diagram illustrating a circuit to which a conventional power gating is applied.

2 is a diagram illustrating a circuit to which conventional zigzag power gating is applied.

3 illustrates a power network and a semiconductor device including the same according to an embodiment of the present invention.

4 is a diagram illustrating a D-type flip-flop which is one of storage devices disposed in a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating n-well separation between a D-type flip-flop and other cells when a D-type flip-flop is disposed on a second rail pair in a semiconductor device according to an exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating that n-well separation between a D-type flip-flop and other cells is not required when the D-type flip-flop is disposed only on a first rail pair in a semiconductor device according to an exemplary embodiment of the present invention.

7 is a diagram for describing an arrangement of logic elements connected to a D flip-flop.

<Explanation of symbols for the main parts of the drawings>

SLEEP: Sleep mode control signal

/ SLEEP: Invert signal of sleep mode control signal

VDD: Power Supply Voltage

VDDV: Virtual Power Supply Voltage

VSS: Base voltage

VSSV: Virtual Base Voltage

F / F: Flip-flop

The present invention relates to a power supply of a semiconductor device, and more particularly, to a power network to which zigzag power gating is applied, a semiconductor device including the power network, a method of designing the power network, and a method of designing a semiconductor device including the power network. It is about.

Modern electronics are being developed to meet smaller market demands, smaller sizes, longer operating times, larger capacities and more functionality. In particular, portable electronic products are required to reduce power and miniaturization. Therefore, the semiconductor devices used in such products are similarly low in power and miniaturized.

As the manufacturing process becomes finer and the power supply voltage becomes lower, semiconductor devices can be miniaturized. However, leakage current increases in the standby mode, and the operation speed cannot be increased in the normal operation mode. To solve this problem, power gating technology has been proposed. The power gating technology connects a metal oxide semiconductor (MOS) transistor having a relatively high threshold voltage in series between a power supply voltage (or a base voltage) and a logic circuit, in an active mode (power on mode). The MOS transistor is turned on to supply a power supply voltage (or base voltage) to a logic circuit having a relatively low threshold voltage, thereby improving the operation speed of the logic circuit, and turning off the MOS transistor in a sleep mode (power down mode). It is a technology that reduces the leakage current (leakage current, sub-threshold current) of the logic circuit by cutting off the logic circuit from the supply voltage (or base voltage). Power gating technology is particularly useful for reducing the power consumption of large scale integration (LSI) chips for portable devices, which are much longer in standby mode than in normal operating mode. The power network using this power gating technology can effectively suppress leakage current in standby mode and improve the operation speed of logic circuits by flowing an appropriate level of current in normal operation mode.

1 is a diagram illustrating a circuit to which a conventional power gating is applied.

Referring to FIG. 1, a circuit to which power gating is applied includes a logic circuit, an N-channel metal-oxide semiconductor (NMOS) transistor (MN1), a line supplied with a power supply voltage (VDD), a virtual base voltage (VSSV) line, and a base voltage. And a line to which VSS is supplied. The power source applied to the power gating circuit is a power supply voltage VDD and a base voltage VSS, and the virtual base voltage VSSV is a power applied through the NMOS transistor. The logic elements of the logic circuit are implemented using MOS transistors having a low threshold voltage to obtain fast operation even at a low power supply voltage (for example, about 1V). In general, as the threshold voltage of the MOS transistor decreases, the drain current increases, so that a logic circuit using a transistor having a low threshold voltage can switch at a higher speed. On the other hand, however, when the threshold voltage of the MOS transistor is lowered, the leakage current rapidly increases at a low power supply voltage (for example, about 1V), and thus a means for blocking the leakage current in the standby mode is required. Therefore, in order to control the leakage current, the current switch MN1 having a high threshold voltage is used.

The NMOS transistor used as the current switch is controlled in response to the inversion signal / SLEEP of the sleep mode control signal. In the normal operation mode, the NMOS transistor is turned on and the virtual base voltage is connected to the base voltage to operate the circuit. In contrast, in the standby mode, the NMOS transistor is turned off to reduce leakage current. Therefore, if the semiconductor device is designed by applying power gating, power consumption of the semiconductor device in the standby mode can be greatly reduced. The NMOS transistor has a high resistance value at turn-off because the threshold voltage is high and the size of the transistor is smaller than the sum of all transistors in the circuit. Therefore, at turn-off, the virtual base voltage rises slowly, finally reaching a power supply voltage. This means that in the circuit all capacitors, including the parasitic capacitors of the transistors, are charged. The charged charges must be discharged when the NMOS transistor is turned on for the operation of the circuit. When the charged charges are fully discharged and the virtual ground voltage approaches the ground voltage, the circuit can accept a new input and operate, so the transition rate of the existing power gating circuit to the active mode is slow. In order to overcome this slow switching speed of power gating, a zigzag power gating technique has been proposed.

2 is a diagram illustrating a circuit to which conventional zigzag power gating is applied.

Referring to FIG. 2, a P-channel metal-oxide semiconductor (PMOS) transistor MP1, an N-channel metal-oxide semiconductor (NMOS) transistor MN1, a line 20 to which a power voltage is supplied, A virtual power voltage line 40, a virtual ground voltage line 60, and a line 80 to which a ground voltage is supplied. A power source applied to the zigzag power gating circuit is a power supply voltage VDD and a base voltage VSS, and a virtual power supply voltage VDDV and a virtual base voltage VSSV are applied through the PMOS transistor and the NMOS transistor, respectively. Power. The sleep vector SLEEP VECTOR and the transistors are controlled in response to a sleep mode control signal SLEEP or an inversion signal / SLEEP of the sleep mode control signal. In the normal operation mode, input data (INPUTS) is applied to the logic circuit 10 to operate. In contrast, in the standby mode, a predetermined sleep vector SLEEP VECTOR is applied to the logic circuit 10, and the PMOS transistor and the NMOS transistor are turned off to reduce the leakage current.

The logic elements 11, 13, and 15 of the logic circuit 10 are connected to the virtual power supply voltage line 40 and the virtual base voltage line 60, respectively, and operate by receiving the virtual power supply voltage and the virtual base voltage. . The kind of power supply voltage and the ground voltage are determined by the sleep vector applied to the logic circuit in the standby mode. For example, referring to the inverter 11 of the logic circuit 10, in FIG. 2, the inverter 11 has an output of 0 due to a sleep vector (if 1) input when in the standby mode. The inverter 11 is connected to the drain (virtual power supply voltage line 40) of the PMOS transistor. Since the leakage current of the inverter 11 is generated by a PMOS transistor (not shown) constituting the inverter by an input value, the leakage current can be effectively reduced by turning off the PMOS transistor in the standby mode. At the same time, since the NMOS transistor (not shown) constituting the inverter 11 is directly connected to the line 80 to which the base voltage is supplied, the output value is maintained even when the PMOS transistor and the NMOS transistor are turned off in the standby mode. . Therefore, power networks with zigzag power gating can maintain their output in standby mode, so unlike power gating, the transition from standby mode to normal operation mode is faster.

As shown in FIG. 2, each of the logic elements 11, 13, and 15 may have different voltages (virtual power supply voltage VDDV and base voltage VSS or power supply voltage VDD and virtual base voltage VSSV) according to output values. Is connected to. Therefore, in the case of using a standard cell, it is not easy to implement a power network in a conventional semi-custom design method due to the problem of shorting between adjacent cells, and thus a full-custom design. It has been implemented only in a way. However, the full custom design method is inefficient for implementing a Very Large Scale Integration (VLSI) circuit, and thus requires a power network with zigzag power gating that can be implemented through a standard cell-based semi-custom design method.

In order to solve the above problems, an object of the present invention is to provide a power network and a power network design method to which zigzag power gating is applied so as to reduce power consumption and to facilitate the implementation of a semi-custom method based on a general standard cell. do.

Another object of the present invention is to provide a semiconductor device and a semiconductor device design method including the power network.

Furthermore, an object of the present invention is to provide a semiconductor device and a semiconductor device design method for arranging logic elements and D-type flip-flops so that the area and the wiring length are minimized.

In order to achieve the above object, a power network according to an embodiment of the present invention includes at least one first rail pair and at least one second rail pair.

The at least one first rail pair includes a power supply voltage line for supplying a power supply voltage and a virtual base voltage line connected via a first power gating circuit and a base voltage line of another rail pair in close proximity. The at least one second rail pair includes a supply voltage line of another rail pair in close proximity, a virtual supply voltage line connected through a second power gating circuit, and a ground voltage line supplying a ground voltage.

The first power gating circuit (NMOS) transistor for switching the connection of the base voltage line and the virtual base voltage line of the other adjacent rail pair in response to the inversion signal of the sleep mode control signal. Can be.

The second power gating circuit may be a P-channel metal-oxide semiconductor (PMOS) transistor configured to switch a connection between the power supply voltage line of the adjacent another rail pair and the virtual power supply voltage line in response to the sleep mode control signal. have.

In order to achieve the above object, a power network design method according to an embodiment of the present invention includes disposing at least one first rail pair consisting of a power supply voltage line and a virtual base voltage line for supplying a power supply voltage, a virtual power supply voltage line, and Arranging at least one second rail pair of base voltage lines for supplying a base voltage, and connecting base voltage lines of another rail pair adjacent to the virtual base voltage line to an N-channel metal-oxide semiconductor (NMOS) transistor And connecting a power supply voltage line of another rail pair adjacent to the virtual power supply voltage line to a P-channel metal-oxide semiconductor (PMOS) transistor.

In order to achieve the above object, a semiconductor device according to an exemplary embodiment includes a plurality of rows of standard cells, one or more first rail pairs, and one or more second rail pairs.

The one or more first rail pairs are respectively formed on top of one or more first rows of the plurality of rows, the power supply voltage line supplying a power voltage and the base voltage line and the first power gating circuit of another adjacent rail pair. It includes a virtual base voltage line connected through.

The one or more second rail pairs are respectively formed on an upper part of the second row except the one or more first rows among the plurality of rows, and are connected through power supply voltage lines of another adjacent rail pair through a second power gating circuit. And a base voltage line for supplying the supply voltage line and the base voltage.

The first power gating circuit is formed in one of the standard cells, and the NMOS switching the connection between the base voltage line and the virtual base voltage line of the other pair of rails in close proximity in response to the inversion signal of the sleep mode control signal ( N-channel metal-oxide semiconductor) transistor.

The second power gating circuit is formed in one of the standard cells, and in response to the sleep mode control signal, a PMOS (P-) for switching the connection between the power supply voltage line of the other pair of rails and the virtual power supply voltage line. channel metal-oxide semiconductor) transistor.

In order to minimize the area of the semiconductor device, a D-type flip-flop may be disposed only in the one or more first rows.

In order to minimize wiring of the semiconductor device, a logic device connected to the D flip-flop may be disposed in the one or more first rows, and receive a sleep vector according to an output value of the logic device.

The number of the one or more first rows and the one or more second rows may be adjusted in proportion to the area of the standard cells in which the D-type flip-flop and the logic element are disposed.

In accordance with an aspect of the present invention, a method of designing a semiconductor device includes determining a sleep vector and arranging the logic devices in a plurality of rows according to output values of the logic devices determined by the sleep vector. Disposing one or more pairs of first rails each comprising a power supply voltage line and a virtual base voltage line supplying a power supply voltage to an upper portion of the one or more first rows in which a logic element having an output of 1 is disposed among the plurality of rows; And arranging one or more second pairs of rails each including a virtual power supply line and a base voltage line supplying a base voltage to a second row except the first row among the plurality of rows. The base voltage lines of the other rail pair close to each other to the N-channel metal-oxide semiconductor (NMOS) transistor. And connecting each power supply voltage line of another rail pair adjacent to the virtual power supply voltage line to a P-channel metal-oxide semiconductor (PMOS) transistor.

The method may further include disposing a D-type flip-flop only in the one or more first rows in order to minimize the area of the semiconductor device.

The method may further include disposing a logic device connected to the D flip-flop in the one or more first rows to minimize the wiring of the semiconductor device.

And adjusting the number of the at least one first row and the at least one second row in proportion to the area of the D-type flip-flop and the standard cells in which the logic element is disposed.

Therefore, a power device using power gating and a power network design method may be applied to design a semiconductor device based on a standard cell with low power consumption. In addition, semiconductor devices can be designed to minimize area and wiring length.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. .

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

3 illustrates a power network and a semiconductor device including the same according to an embodiment of the present invention.

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Referring to FIG. 3, a semiconductor device includes a standard cell, a first rail pair, and a second rail pair. The power network to which zigzag power gating is applied includes a first rail pair 1000 and a second rail pair 2000. The first rail pair 1000 and the second rail pair 2000 may be one or more.
The first rail pair 1000 includes a power supply voltage line 1200 and a virtual base voltage line 1300. The power supply voltage line 1200 is a line for supplying a power supply voltage VDD, and the virtual base voltage line 1300 is a line connected to the base voltage line of another adjacent rail pair through the first power gating circuit 1100. to be.
The second rail pair 2000 includes a virtual power supply voltage line 2200 and a base voltage line 2000. The virtual power supply voltage line 2200 is a line connected to the power supply voltage line of another adjacent rail pair through the second power gating circuit 2100, and the base voltage line 2300 is a base for supplying a base voltage VSS. Low voltage line.
The first power gating circuit 1100 may include an N-channel metal-oxide semiconductor (NMOS) transistor. The second power gating circuit 2100 may include a P-channel metal-oxide semiconductor (PMOS) transistor.
The first power gating circuit 1100 electrically connects or disconnects the connection between the virtual base voltage line 1300 and the base voltage line 2300 for supplying a base voltage in response to an inversion signal of a sleep mode control signal. It acts as a switch. The virtual power supply voltage line 2200 of the second rail pair 2000 is connected to the power supply voltage line 1200 supplying the power supply voltage of the first rail pair 1000 by a second power gating circuit 2100. Supply virtual power supply voltage.
The second power gating circuit 2100 serves as a current switch for electrically connecting or disconnecting the connection between the virtual power supply voltage line 2200 and the power supply voltage line 1200 in response to a sleep mode control signal.
The plurality of first rail pairs and the second rail pairs may be regularly repeated. However, as will be described below, the plurality of first rail pairs and the second rail pair may be irregularly repeated once every two to three rows as necessary when designing a semiconductor.

The power network can be implemented based on an existing standard cell because one rail pair includes one pair of power supply voltage line and virtual base voltage line or one pair of virtual power supply voltage line and base voltage line.
Each cell indicated by the rectangle in FIG. 3 represents one standard cell. The power network sets the threshold voltages of the MOS transistors of the first power gating circuit 1100 and the second power gating circuit 2100 to be relatively high, and turns on the MOS transistors in a normal operation mode to supply a power supply voltage (or a base voltage). Is supplied to a logic circuit (not shown) with a relatively low threshold voltage, thereby improving the operation speed of the logic circuit.In the standby mode, the MOS transistor is turned off to cut off the power supply voltage (or base voltage) supplied to the logic circuit. Can reduce the leakage current. Therefore, the semiconductor device to which the power network of the present invention is applied is effective in reducing power consumption by suppressing leakage current in the standby mode while improving the operation speed in the normal operation mode.

In addition, if the power network of the present invention is used, the semiconductor device may be designed in a semi-custom manner based on an existing standard cell. This saves cost, time, and designer effort compared to conventionally custom designing semiconductor devices due to short cell-to-cell problems.

In addition, the plurality of first rail pairs and the second rail pairs may be arranged regularly or by adjusting the number of rows as necessary, and there is an advantage in that logic elements or storage devices may be freely arranged. For example, if logic elements 11, 13, and 15 as shown in FIG. 2 are arranged in a semiconductor device according to an embodiment of the present invention, the inverter 11 may have a virtual power supply voltage VDDV and a base voltage ( VSS) should be supplied, so it would be suitable to be placed on the second rail pair. It would likewise be appropriate that the NAND gate 13 is arranged in the first rail pair and the NOR gate 15 in the second rail pair. Since the semiconductor device has a plurality of first rail pairs and second rail pairs, and these rows are regularly arranged, the logic elements can be arranged relatively freely.

4 is a diagram illustrating a D-type flip-flop which is one of storage devices disposed in a semiconductor device according to an embodiment of the present invention.

In the semiconductor device to which the power network of the present invention is applied, a part of the storage device in the standby mode is required to store 0 or 1 data and thus is connected to the power supply voltage VDD and the base voltage VSS. In addition, portions of the storage device not related to data retention are connected to the second power gating circuit or the first power gating circuit to reduce leakage current.

3 and 4, as an example of a storage device included in a semiconductor device, a D-type flip-flop includes a master latch and a slave latch. The master latch includes a first inverter 100, a second inverter 200, and a third inverter 300. The first inverter 100 and the second inverter 200 are connected in series, and the third inverter 300 is connected to the second inverter 200 in a feedback form.
The flip-flop of FIG. 4 is a D-type flip-flop when 0 is input to the input terminal D in the standby mode, and the flip-flops of the first inverter 100 and the third inverter 300 of the master latch (MASTER LATCH). The gate terminals are connected to the power supply voltage line and the virtual base voltage line, and the gate terminal of the second inverter 200 is connected to the virtual power supply voltage line and the base voltage line.
Lines connected to the gate terminal are connected to a power supply voltage VDD, a base voltage VSS, a virtual power supply voltage VDDV, and a virtual base voltage VSSV passing through the first rail pair and the second rail pair of FIG. 3. Corresponding. Therefore, the master latch (MASTER LATCH) irrespective of data retention is connected to the second power gating circuit 2100 or the first power gating circuit 1100 in the standby mode, thereby reducing the leakage current.

In another embodiment, in the case of a D-type flip-flop in which 1 is input to the input terminal D in a standby mode, power lines connected to inverters become a master latch connected to the power lines. In this case, power terminals of the first inverter 100 and the third inverter 300 of the master latch are connected to the virtual power supply line and the base voltage line, and the gate terminal of the second inverter 200. Is connected to the supply voltage line and the virtual ground voltage line.

The slave latch holding the received data includes a fourth inverter 400, a fifth inverter 500, and a sixth inverter 600. The fourth inverter 400 and the fifth inverter 500 are connected in series, and the sixth inverter 600 is connected to the fourth inverter 400 by feedback. Gate terminals of the fourth inverter 400, the fifth inverter 500, and the sixth inverter 600 are all connected to a power supply line and a base voltage line.

In order for the slave latch of FIG. 4 to hold data, the clock must be kept at a logic low value, that is, a value of 0 (CLK = 0). In the power network of the present invention, the D-type flip-flop, which is a storage device, requires four types of powers consisting of a power supply voltage (VDD), a base voltage (VSS), a virtual power supply voltage (VDDV), and a virtual base voltage (VSSV). do. However, since the conventional D-type flip-flop of the standard cell type has only a power supply voltage VDD and a ground voltage VSS terminal, the present invention proposes a power connection of a storage device through wiring.

FIG. 5 is a diagram illustrating n-well separation between a D-type flip-flop and other cells when a D-type flip-flop is disposed on a second rail pair in a semiconductor device according to an exemplary embodiment of the present invention.

Using the power network of the present invention, as illustrated in FIG. 3, the D-type flip-flop converts the close power supply voltage VDD, the base voltage VSS, the virtual power supply voltage VDDV, and the virtual base voltage VSSV through wiring. Can be supplied. Therefore, the D flip-flop can be freely disposed.
The n-wells of the standard cells arranged in the second rail pair are connected to the virtual power supply voltage VDDV. The virtual power supply voltage VDDV has a voltage lower than the power supply voltage VDD in the standby mode. Therefore, if the D-type flip-flop is disposed on the second rail pair, the body (n-well) of the PMOS transistors constituting the D-type flip-flop is connected to the virtual power supply voltage VDDV, and thus the body voltage lower than the source voltage VDD. The threshold voltage of the PMOS transistor in the D flip-flop is reduced. Therefore, the leakage current may be increased in the slave latch.
Therefore, in order to prevent an increase in leakage current of the D-type flip-flop disposed on the second rail pair, the n-well must be connected to the power supply voltage VDD, so that the n-well of the cell in which the D-type flip-flop is disposed as shown in FIG. Must be separated from the n-wells of neighboring cells. 'A', 'B', and 'C' in FIG. 5 represent a space for n-well separation between a cell in which a D-type flip-flop disposed on a second rail pair and a neighboring cell are increased, thereby increasing the area of a semiconductor device. Let's do it. Therefore, if the D-type flip-flop is disposed only in the first rail pair, the area of the semiconductor device may be reduced.

FIG. 6 illustrates that n-well separation between a D-type flip-flop and other cells is not required when the D-type flip-flop is disposed only on a first rail pair in a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 6, the D-type flip-flop may be disposed only on the first rail pair to reduce the space wasted for n-well separation between cells as shown in FIG. 5. In the semiconductor device using the power network of the present invention, when the D flip-flop is disposed only on the first rail pair, the total number of first rail pairs and the second rail pair may be determined in consideration of the area of the standard cells including the D flip-flop. I can adjust it.

7 is a diagram for describing an arrangement of logic elements connected to a D flip-flop.

As shown in FIG. 6, when the D flip-flop is disposed only on the first rail pair, the area of the semiconductor device may be reduced, but the length of the wiring connected to the D flip-flop may be increased. Therefore, in FIG. 7, as the logic elements connected to the input terminal and the output terminal of the D flip-flop are disposed in the standard cells of the second rail pair, the wiring length increases. Since the arrangement of the standard cells including the logic elements is determined by the output value of the slip vector, in order to minimize the increase in the wiring length, the logic elements connected to the D-type flip-flop are arranged on the first rail pair as much as possible. Set the slip vector to match the output. This can minimize the wiring of the semiconductor device.

As described above, a power network and a power network design method using zigzag power gating according to an embodiment of the present invention can reduce power consumption.

In addition, since the semiconductor device and the semiconductor device design method including the power network to which zigzag power gating is applied according to an embodiment of the present invention can be implemented using a standard cell, the semiconductor device can be designed in a semi-custom manner and power consumption can be reduced. .

Furthermore, in the semiconductor device and the semiconductor device design method including the power network to which the zigzag power gating is applied according to an embodiment of the present invention, the logic element and the D-type flip-flop may be disposed to minimize the area and the wiring length of the semiconductor device.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (14)

At least one first rail pair consisting of a supply line voltage supplying a supply voltage line and a virtual base voltage line connected via a first power gating circuit to a base voltage line of another rail pair in proximity; And A power network circuit comprising one or more second rail pairs comprising a virtual power supply line and a base voltage line for supplying a base voltage to a power supply line of another rail pair in close proximity via a second power gating circuit. The method of claim 1, The first power gating circuit (NMOS) transistor for switching the connection of the base voltage line and the virtual base voltage line of the other adjacent rail pair in response to the inversion signal of the sleep mode control signal. The power network circuit characterized by the above-mentioned. The method of claim 1, The second power gating circuit is a P-channel metal-oxide semiconductor (PMOS) transistor that switches a connection between the power supply voltage line and the virtual power supply voltage line of another adjacent rail pair in response to a sleep mode control signal. Power network circuit. Arranging at least one first rail pair consisting of a power supply voltage line and a virtual base voltage line for supplying a power supply voltage; Disposing at least one second rail pair consisting of a virtual power supply line and a base voltage line for supplying a base voltage; Connecting base voltage lines of another rail pair adjacent to the virtual base voltage line to an N-channel metal-oxide semiconductor (NMOS) transistor; And And connecting a power supply voltage line of another rail pair adjacent to the virtual power supply voltage line with a P-channel metal-oxide semiconductor (PMOS) transistor. Standard cells constituting a plurality of rows; And a virtual base voltage line formed on top of one or more first rows of the plurality of rows, the power supply voltage line supplying a power supply voltage, and the base voltage line of another pair of rails adjacent to each other and a virtual base voltage line connected through a first power gating circuit. One or more first rail pairs; And A virtual power supply voltage line and a base voltage which are formed on an upper portion of the second row except for the one or more first rows among the plurality of rows, and are connected through power supply voltage lines of another adjacent rail pair and a second power gating circuit; And at least one second rail pair of base voltage lines. The method of claim 5, wherein The first power gating circuit is formed in one of the standard cells, and the NMOS switching the connection between the base voltage line and the virtual base voltage line of the other pair of rails in close proximity in response to the inversion signal of the sleep mode control signal ( An N-channel metal-oxide semiconductor transistor. The method of claim 5, wherein The second power gating circuit is formed in one of the standard cells, and PMOS (P-channel) for switching the connection between the power supply line and the virtual power supply line of the other rail pair in close proximity in response to a sleep mode control signal A metal device comprising a metal-oxide semiconductor transistor. The method of claim 5, wherein And a D-type flip-flop is disposed only in the one or more first rows in order to minimize the area of the semiconductor device. The method of claim 8, In order to minimize the wiring of the semiconductor device, a logic element connected to the D-type flip-flop is disposed in the at least one first row, the semiconductor device, characterized in that receives a sleep vector according to the output value of the logic element. The method of claim 9, And adjusting the number of the at least one first row and the at least one second row in proportion to the area of the standard cells in which the D-type flip-flop and the logic element are disposed. Determining a slip vector; Arranging the logic elements in a plurality of rows according to output values of the logic elements determined by the sleep vector; Disposing one or more first pairs of rails each including a power supply voltage line and a virtual base voltage line supplying a power supply voltage to an upper portion of the one or more first rows in which a logic element having an output of 1 is disposed among the plurality of rows; Arranging at least one pair of second rails each including a virtual power supply line and a base voltage line supplying a base voltage line to an upper portion of the second row except the at least one first row among the plurality of rows; Connecting base voltage lines of another rail pair adjacent to the virtual base voltage line to N-channel metal-oxide semiconductor (NMOS) transistors, respectively; And Connecting power supply voltage lines of other rail pairs adjacent to the virtual power supply voltage lines to P-channel metal-oxide semiconductor (PMOS) transistors, respectively. The method of claim 11, Disposing a D-type flip-flop only in the at least one first row to minimize the area of the semiconductor device. The method of claim 12, And arranging logic elements connected to the D flip-flop in the one or more first rows to minimize wiring of the semiconductor device. The method of claim 13, And adjusting the number of the at least one first row and the at least one second row in proportion to the area of the D-type flip-flop and the standard cells in which the logic element is disposed.

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