KR100857446B1 - Apparatus for setting operation mode in dll circuit - Google Patents

Abstract

An apparatus for setting an operation mode in a DLL(Delay Locked Loop) circuit is provided to perform normal operation even in a clock state change due to external jitter or PVT(Process, Voltage, and Temperature). An apparatus for setting an operation mode in a DLL circuit includes a reset unit(10), a power supply unit(20), first and second control units(30,40), and a latch unit(50). The reset unit controls a potential of a first node in response to a reset signal. The power supply unit supplies power to a second node in response to a lock completion signal and a first pulse signal. The first control unit generates a latch coarse signal by latching a coarse delay signal in response to a second pulse signal and controls a potential of the second node in response to the first pulse signal and the latch coarse signal. The second control unit controls the potential of the first node in response to the first pulse signal, the latch coarse signal, and a fine delay signal. The latch unit latches the potential of the first node and outputs the lock completion signal.

Description

Apparatus for Setting Operation Mode in DLL Circuit}

1 is a block diagram showing the configuration of an operation mode setting apparatus of a DLL circuit according to an embodiment of the present invention;

FIG. 2 is a circuit diagram showing the detailed configuration of the operation mode setting device shown in FIG. 1;

3 is a timing diagram illustrating an operation of an operation mode setting apparatus of a DLL circuit according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10: reset unit 20: power supply unit

30: first control unit 40: second control unit

50: latch portion

The present invention relates to an operation mode setting device of a DLL (Delay Locked Loop) circuit, and more particularly to an operation mode setting device of a DLL circuit for reducing the possibility of malfunction.

Typically, DLL circuits are used to provide an internal clock that is time-phased relative to a reference clock obtained by converting an external clock. The DLL circuit is used to solve the problem that the internal clock utilized in the semiconductor integrated circuit is delayed through the clock buffer and the transmission line, thereby causing a phase difference with the external clock, thereby increasing the output data access time. The DLL circuit performs a function of controlling the phase of the internal clock to be a predetermined time ahead of the external clock in order to increase the effective data output interval.

The DLL circuit according to the related art generates a feedback clock by including a replica delay modeling a delay amount present in a path in which an internal reference clock is transmitted to the outside of the semiconductor integrated circuit. Thereafter, the phases of the reference clock and the feedback clock are compared to generate a signal according to the result. The delay line gives a predetermined delay time to the reference clock to synchronize the phase of the feedback clock.

In this case, a coarse locking mode, a fine locking mode, or the like may be used as a method of fixing a clock that gives a delay time to the reference clock. The coarse fixed mode is a method of providing a delay time in units of a plurality of unit delay units provided in the delay line, and the fine fixed mode finely delays a clock using a phase mixer without utilizing the unit delay unit. This is how you do it. In order to perform such an operation, the DLL circuit includes an operation mode setting device. The operation mode setting device receives a course delay signal and a fine delay signal from a phase comparison device comparing a phase of a reference clock and a feedback clock, and fixes the course. The operation of the delay line is controlled by outputting a fixed completion signal for indicating the end timing of the mode.

In practice, there is a case where the clock timing of the clock input to the DLL circuit is not constant due to various factors such as external jitter. In addition, the phase of the reference clock and the feedback clock inside the DLL circuit may be out of phase due to a change in PVT (Process, Voltage, Temperature). When such a malfunction occurs, the coarse delay signal and the fine delay signal generated from the phase comparison device also change their level transition timing. Since the operation mode setting device generates the fixed completion signal under the control of the coarse delay signal and the fine delay signal, the enable timing of the fixed completion signal is also changed when the above malfunction occurs.

The fixed completion signal should be enabled when the phase difference between the reference clock and the feedback clock input to the phase comparison device is narrowed within a predetermined range. However, if the above-described malfunction causes the enable timing of the fixed completion signal to be faster than during normal operation, the DLL circuit enters the fine fixed mode at too early timing. If the enable timing of the fixed completion signal becomes slower than during normal operation, the DLL circuit will perform a coarse fixed mode operation for a too long time. This malfunction increases the time required for the delay lock operation of the clock and causes a duty ratio mismatch of the clock and a failure in the data output operation.

As such, the operation mode setting device according to the related art is designed without considering a situation where the DLL circuit is affected by external jitter or PVT. Therefore, the failure prevention could be ensured only under the assumption that the clock and power voltage input to the DLL circuit are always normal. However, in practice, the DLL circuit is provided in an environment in which various failure factors exist, and the conventional operation mode setting device lacks adaptability to malfunctions caused by such failure factors.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a device for setting an operation mode of a DLL circuit capable of performing normal operation even when a clock state changes due to external jitter or PVT. have.

Another object of the present invention is to provide an operation mode setting device of a DLL circuit which improves the stability of the enable timing of the fixed completion signal.

According to an aspect of the present invention, there is provided an apparatus for setting an operation mode of a DLL circuit, the reset unit controlling a potential of a first node in response to a reset signal; A power supply unit supplying power to the second node in response to the fixed completion signal and the first pulse signal; A first controller configured to generate a latch course signal by latching a coarse delay signal in response to a second pulse signal, and controlling a potential of the second node in response to the first pulse signal and the latch course signal; A second control unit controlling a potential of the first node in response to the first pulse signal, the latch course signal, and a fine delay signal; And a latch unit configured to latch a potential formed at the first node and output the fixed completion signal.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a block diagram showing a configuration of an operation mode setting apparatus of a DLL circuit according to an exemplary embodiment of the present invention.

As shown, the operation mode setting device includes a reset unit 10 for controlling the potential of the first node N1 in response to a reset signal rst, a fixed completion signal lock, and a first pulse signal pls1. In response to the power supply unit 20 for supplying power to the second node (N2), in response to the second pulse signal (pls2) by latching the coarse delay signal (crsdl) to generate the latch course signal (latcrs), The first control unit 30, the first pulse signal pls1, and the second control unit controlling the potential of the second node N2 in response to the latch course signal latcrs and the first pulse signal pls1. In response to a pulse signal pls2, the latch course signal latcrs, and a fine delay signal findl, the second control unit 40 and the first node N1 for controlling the potential of the first node N1. And a latch unit 50 for latching the potential to be formed and outputting the fixed completion signal lock.

The first pulse signal pls1 and the second pulse signal pls2 are signals generated inside the DLL circuit, and generally have a pulse width corresponding to one period of the internal clock, and a predetermined period of the internal clock, for example, For example, it is implemented as a toggle every 15 cycles. Here, the second pulse signal pls2 has a toggle timing that precedes the first pulse signal pls1. In addition, the reset signal rst may be implemented as a low enable signal.

As described above, the first controller 30 generates the latch course signal latcrs by latching the coarse delay signal crsdl. The second controller 40 latches the latch course signal latcrs once again and latches the fine delay signal findl once to control the potential of the first node N1. However, the fine delay signal findl is not latched, and the latch of the latch course signal latcrs may be controlled to control the potential of the first node N1. A more detailed description thereof will be made with reference to FIG. 2.

FIG. 2 is a circuit diagram showing the detailed configuration of the operation mode setting device shown in FIG.

As shown in the drawing, the reset unit 10 includes a first terminal in which the reset signal rst is input, an external supply power VDD is applied to a source terminal, and a drain terminal is connected to the first node N1. One transistor TR1 is included.

The power supply unit 20 has a second transistor TR2 to which the fixed completion signal lock is input to a gate terminal and the external supply power VDD is applied to a source terminal, and the first pulse signal to a gate terminal. pls1 is input, the source terminal is connected to the drain terminal of the second transistor TR2, and the drain terminal comprises a third transistor TR3 connected to the second node N2.

In addition, the first control unit 30 latches the coarse delay signal crsdl in response to the second pulse signal pls2 to generate the latch coarse signal latcrs. The latch pulse signal latcrs is input to the fourth transistor TR4 and the drain terminal thereof is connected to the second node N2, and the first pulse signal pls1 is input to the gate terminal thereof, and the drain terminal thereof is the second transistor. And a fifth transistor TR5 connected to the source terminal of the fourth transistor TR4 and whose source terminal is grounded.

The second controller 40 latches an output signal of the first inverter IV1 in response to the first inverter IV1 receiving the latch course signal latcrs and the first pulse signal pls1. A second flip-flop FF2, an output signal of the second flip-flop FF2 is input to a gate terminal, a drain terminal is connected to the first node N1, and a source terminal is connected to the second node N2. The third transistor TR6, the third flip-flop FF3 latching the fine delay signal findl in response to the second pulse signal pls2, and an output of the third flip-flop FF3 at a gate terminal thereof. And a seventh transistor TR7 to which a signal is input, a drain terminal is connected to the first node N1, and a source terminal is connected to the second node N2.

Lastly, the latch unit 50 receives a signal formed at the first node N1 and a latch structure with the second inverter IV2 and the second inverter IV2 that output the lock completion signal lock. It includes a third inverter (IV3) to form a.

When the operation of the DLL circuit starts, the reset signal rst is enabled and the reset unit 10 sets the potential of the first node N1 to a high level.

At this time, the lock completion signal lock has a low level potential. As mentioned above, the first pulse signal pls1 is a signal that toggles once every predetermined period of the internal clock. The power supply unit 20 supplies a high level potential to the second node N2 at a timing when the first pulse signal pls1 does not toggle when the fixed completion signal lock is disabled.

The first controller 30 generates the latch course signal latcrs by latching the coarse delay signal crsdl using the first flip-flop FF1, and generates the gate of the fourth transistor TR4. Supply to the stage. Therefore, even when the coarse delay signal crsdl experiences an unstable level transition, the first control unit 30 uses the coarse delay signal crsdl only for the toggle timing of the second pulse signal pls2 and uses the fourth transistor. By controlling the TR4, it is possible to prevent the second node N2 from sinking to the ground power supply VSS level at an undesired timing.

In addition, the second controller 40 latches the fine delay signal findl using the third flip-flop FF3 and supplies it to the gate terminal of the seventh transistor TR7. Accordingly, the second controller 40 controls the seventh transistor TR7 by using the fine delay signal findl only at the toggle timing of the second pulse signal pls2.

As described above, the operation mode setting device of the DLL circuit of the present invention changes the clock timing of the clock due to external jitter or PVT of the DLL circuit, and prevents the coarse delay signal crsdl or the fine delay signal from being unstable. Even if it is experienced, malfunction can be prevented by setting the potentials of the first node N1 and the second node N2 only at the toggle timing of the second pulse signal pls2. Here, although both the first flip-flop FF1 and the third flip-flop FF3 are provided, the present invention may be implemented even with only the first flip-flop FF1.

That is, in the operation mode setting apparatus of the DLL circuit of the present invention, when the latch course signal latcrs generated by the first controller 30 is at a high level, the first pulse signal pls1 is applied. Toggling causes the second node N2 to sink to a low level. When the output signal of the second flip-flop FF2 or the output signal of the third flip-flop FF3 of the second controller 40 is at a high level, the first node N1 and the second node ( N2) is switched so that the potential of the first node N1 is at a low level.

Thereafter, the latch unit 50 inverts the potential of the first node N1 to generate the lock completion signal lock, and continuously outputs the lock. Since the timing at which the first node N1 becomes a low level is stabilized by the operations of the first control unit 30 and the second control unit 40, the enable timing of the fixed completion signal lock is also stabilized. .

3 is a timing diagram illustrating an operation of an operation mode setting apparatus of a DLL circuit according to an exemplary embodiment of the present invention.

In the drawing, the coarse delay signal crsdl, the fine delay signal findl, the first pulse signal pls1, the second pulse signal pls2, the latch course signal latcrs, and the second flip-flop. The output signal of FF2, the waveform of the output signal of the third flip-flop FF3, the potential of the first node N1, and the waveform of the fixed completion signal lock are shown.

The dotted lines shown in the coarse delay signal crsdl and the fine delay signal findl represent a case in which a malfunction occurs in an enable timing due to a state change of a clock. It can be seen that the first pulse signal pls1 toggles later than the second pulse signal pls2. As shown in the figure, the output signal of the second flip-flop FF2 may shift its level only when the first pulse signal pls1 toggles. The latch course signal latcrs and the output signal of the third flip-flop FF3 may shift only when the second pulse signal pls2 toggles. If the output signal of the latch course signal latcrs and the second flip-flop FF2 or the output signal of the third flip-flop FF3 is at a high level at the toggle timing of the first pulse signal pls1, The potential of one node N1 is at a low level. The potential level of the first node N1 is inverted and latched and output as the fixed completion signal lock.

In the operation mode setting apparatus of the DLL circuit according to the related art, when the malfunction occurs and the coarse delay signal crsdl is enabled at an undesired timing and the first pulse signal pls1 is toggled at this time, the fine According to a high level potential of the delay signal findl or the output signal of the first flip-flop FF1, a malfunction may occur in which the fixed completion signal lock is enabled too soon. However, the operation mode setting device of the DLL circuit of the present invention may shift the level of the latch course signal latcrs and the output signal of the third flip-flop FF3 only at the toggle timing of the second pulse signal pls2. As a result, the possibility of the above-described malfunctions is reduced.

That is, in the operation mode setting device of the DLL circuit of the present invention, the timing input of the clock inputted to the DLL circuit is not constant due to external jitter, or the reference clock and the feedback clock inside the DLL circuit are changed due to a PVT change. Even when the phases do not coincide, the coarse delay signal is latched once and the potential of the signal forming node is controlled using this to generate a fixed completion signal with more stable enable timing. Therefore, the DLL circuit has a more accurate coarse fixed mode operation section and a fine fixed mode operation section, thereby reducing the duty ratio mismatch of the clock and a defect in the data output operation.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The operation mode setting device of the DLL circuit of the present invention described above has the effect that the normal operation can be performed even when the clock changes due to the influence of external jitter or PVT.

In addition, the present invention has the effect of improving the stability of the enable timing of the fixed completion signal.

Claims (5)

A reset unit controlling a potential of the first node in response to the reset signal; A power supply unit supplying power to the second node in response to the fixed completion signal and the first pulse signal; A first controller configured to generate a latch course signal by latching a coarse delay signal in response to a second pulse signal, and controlling a potential of the second node in response to the first pulse signal and the latch course signal; A second control unit controlling a potential of the first node in response to the first pulse signal, the latch course signal, and a fine delay signal; And A latch unit for latching a potential formed at the first node and outputting the fixed completion signal; Device for setting the operation mode of the DLL circuit, characterized in that it comprises a. The method of claim 1, The first control unit generates the latch course signal by latching the coarse delay signal when the second pulse signal is at a first level, and when the first pulse signal and the latch course signal are at the first level. The operation mode setting device of the DLL circuit, characterized by supplying the potential of the second level to the second node. The method according to claim 1 or 2, The first control unit, A first flip-flop that latches the coarse delay signal in response to the second pulse signal to generate the latch coarse signal; A first transistor having a latch course signal input to a gate end thereof and a drain end thereof connected to the second node; And A second transistor having a first pulse signal input to a gate terminal, a drain terminal connected to a source terminal of the first transistor, and a source terminal grounded; Device for setting the operation mode of the DLL circuit, characterized in that it comprises a. The method of claim 1, And the second control unit further comprises latching the fine delay signal in response to the second pulse signal to control the potential of the second node. The method of claim 4, wherein The second control unit, An inverter receiving the latch course signal; A first flip-flop for latching an output signal of the inverter in response to the first pulse signal; A first transistor having an output signal of the first flip-flop at a gate end thereof, a drain end thereof connected to the first node, and a source end thereof connected to the second node; A second flip-flop that latches the fine delay signal in response to the second pulse signal; And A second transistor having an output signal of the second flip-flop input to a gate end thereof, a drain end thereof connected to the first node, and a source end thereof connected to the second node; Device for setting the operation mode of the DLL circuit, characterized in that it comprises a.

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