KR100853403B1 - Multiply and demultiply apparatus for semiconductor test partern signal and semiconductor test header apparatus - Google Patents

Abstract

An apparatus for multiplying and dividing a semiconductor test pattern signal and a semiconductor device test header are provided to utilize an ALPG for processing a low frequency signal in an ATE(Automatic Test Equipment) by integrating a test pattern signal conversion unit with a PE(Pin Electronic) in a single chip. An apparatus for multiplying and dividing a semiconductor test pattern signal includes a driver(131), a comparator(133), and a signal processor(135). The driver writes a test pattern on a DUT(Device Under Test) having plural I/O channels according to a test pattern signal. The comparator outputs a comparison signal, which is generated by comparing the written test pattern with a reference signal. The signal processor serializes the test pattern signal of the DUT, which is outputted from an ALPG(Algorithm Pattern Generator), outputs the serialized signal to the driver, parallelizes the comparison signal from the comparator, and outputs the parallel signal to the ALPG. A delay compensator(137) compensates a delay time difference between an inter-channel test pattern signal, which is multiplied by the signal processor, and the comparison signal from the comparator.

Description

Multiply and Demultiply apparatus for semiconductor test partern signal and semiconductor test header apparatus

1 is a perspective view showing a conventional semiconductor test system.

2 is a schematic diagram schematically showing a conventional semiconductor test header device.

3 is a schematic diagram schematically illustrating a test pattern signal multiplication process in the ALPG of a conventional semiconductor test header device.

4 is a block diagram schematically illustrating a semiconductor test header device according to an exemplary embodiment of the present invention.

5 is a block diagram schematically illustrating a PE unit according to an exemplary embodiment of the present invention.

6 is a schematic diagram schematically illustrating a multiplication and division process of a test pattern signal of a signal processing unit according to an exemplary embodiment of the present invention.

*** Description of the symbols for the main parts of the drawings ***

1. High Fix Board

2. test head

10. ALPG

11. Test pattern signal generator 13. Signal multiplier

30.PE part

31.Driver 33.Comparator

50.DUT 70.I / F

3. Handler

5. Control computer

110.ALPG

130.PE part

131.Driver 133.Comparator

135. Signal Processing Unit

135-1. Serialization Part 135-3. Parallelize part

135-5. PLL

137. Delay Compensation Unit

150.DUT 170.I / F

The present invention relates to a semiconductor test apparatus, and more particularly, a semiconductor test system by separating a circuit for multiplying a test pattern signal with a bandwidth of an operation signal required by an ATE from an ALPG and integrating it into a separate single chip together with a PE unit. The present invention relates to a semiconductor test pattern signal multiplying / dividing device and a semiconductor test header device using the same.

As is well known, a semiconductor manufactured by a semiconductor manufacturing process is subjected to a test process for correct operation according to its characteristics after manufacturing. Such a semiconductor test is performed by a semiconductor test system, which will be described in more detail with reference to FIGS. 1 to 3 below.

1 is a perspective view illustrating a conventional semiconductor test system, FIG. 2 is a schematic view illustrating a conventional semiconductor test header device, and FIG. 3 illustrates a test pattern signal multiplication process in ALPG of the conventional semiconductor test header device. It is a schematic diagram schematically. As shown in the drawing, a conventional semiconductor test system includes a test head 2 for testing a semiconductor and a plurality of semiconductors so that the test is carried out and classifies and loads the semiconductors according to a test result by the test head 2. And a HIFIX board interposed between the handler 3 and the test head 2 and the handler 3 to establish an electrical connection between the semiconductor and the test head 2. That is, the semiconductor and the high-fixed board 1 seated in the insert on the test tray in a state where the high-fixed board 1 in which the sockets of the (m * n) arrays are arranged and the test site of the handler 3 are matched. (Mxn) semiconductors are tested simultaneously by sockets on

Meanwhile, the test head 2 includes a single test head substrate and various circuit elements mounted on one or both surfaces thereof. Referring to the configuration of the test head substrate, the test head 2 generates a predetermined test pattern signal for semiconductor testing. An Algorithm Pattern Generater (ALPG) 10, a driver 31 that writes a test pattern signal output from the ALPG 10 to the Device Under Test (DUT) 50, and a test pattern read by the DUT 50 A control unit for controlling a semiconductor test system and a PE (Pin Electronic) unit 30 including a comparator 33 for comparing the readout signal with the reference signal corresponding to the characteristic of the semiconductor and outputting the comparison value. 90 and the interface unit 70 for the interface of the test head (2). Here, the PE unit 30 is a circuit that directly applies a current and a voltage according to the test pattern to the semiconductor provided in the DUT 50.

When the test pattern signal is output by the test pattern signal generator 11 of the ALPG 10, the driver 31 of the PE unit 30 sends the test pattern signal to the DUT 40 of a ball grid array (BGA) type. The data is recorded in the semiconductor under test. The pattern signal thus recorded is read by the DUT and output to the comparator 33. The comparator 33 sends a comparison signal based on a result of comparing the read signal of the test pattern with the reference signal to the control computer. And the control computer can analyze the comparison signal to check that the semiconductor operates correctly to its characteristics.

Meanwhile, semiconductor test systems are driven by signals having different frequency bands for each manufacturer. For example, when the ATE is a system operating at 1 GHz, the test pattern signal output through the ALPG 10 should also have a frequency of 1 GHz, and the test pattern signal of 1 GHz, which is a digital signal output through the ALPG 10, may be a PE. The unit 30 is converted into an analog signal of 1 GHz and recorded in the DUT.

However, PCB technology for high frequency processing such as 1 GHz is not only required for high technology but also expensive to manufacture, which can lead to an increase in manufacturing cost of semiconductor test systems.

According to this problem, the conventional ATE manufacturers implement the ALPG 10 as an ASIC, but output the low frequency test pattern signal inside the ALPG 10 and multiplex it at the end of the ASIC so that the desired frequency band of the ATE is multiplied. The technology used to output a signal was used. The multiplication process of the test pattern signal when the ATE is a system requiring an output frequency of 1 GHz will be described in detail with reference to FIG. 3.

When the test pattern signal of 250 MHz is generated and output by the test pattern signal generator 11 of the ALPG 10, the output test pattern signal is multiplied and output by the signal multiplier 13. Each test pattern signal output from the test pattern signal generator 11 is first output as a 500 MHz signal by a multiplexer. At this time, the first test pattern signal of 36 bits of 250 MHz is output as a signal of 18 MHz 500 MHz in a multiplication process. do. In this case, the 18-bit 500 MHz signal is a parallel signal, and the parallel test pattern signal is multiplied and output by the multiplexer, thereby outputting the 1 GHz signal required by the ATE to the PE unit 30.

However, this method requires the entire ALPG circuit to maintain the output of 1 GHz, so that an additional circuit for multiplying the low frequency test pattern signal output from the ALPG from the ATE to the desired high frequency output signal, that is, the multiplexer described above and connecting the same There is a disadvantage that requires technology.

In other words, ALPG cannot be implemented as a single ASIC circuit, and even if implemented, the system itself is complicated due to the need of a separate circuit to connect to the conventional PE unit, and thus, the system itself becomes complicated and the defects and size thereof increase. .

In addition, since the PE part converts the test pattern signal output from ALPG and ALPG implemented with digital logic in the conventional ATE into an analog signal of a specific protocol and outputs it to the DUT, since the PE part has independent functions and configurations, It was impossible.

However, Korean Patent Application No. 10-2007-0027783 filed by the applicant of March 21, 2007 discloses the above-described digitization technology of the PE part. This patent application discloses a technology in which ALPG and PE units are interconnected through a PCB pattern by implementing driver circuits and comparator circuits in FPGAs or ASICs.

Therefore, the applicant of the present invention reduces the difficulty of the technology through the PCB generated by the signal multiplication by using the low frequency signal output from the ALPG as the background of the prior application of Korean Patent Application No. 10-2007-0027783 The present invention has been studied by studying a technology capable of digitizing.

The present invention has been devised from such a background. By multiplying a portion that multiplies the test pattern signal output from ALPG to the PE unit and integrating it into one chip, the semiconductor test pattern signal multiplication can be improved. A dispenser and a semiconductor test header device using the same are provided.

Furthermore, the present invention provides a low-cost and miniaturized semiconductor test pattern signal multiplication / dividing device and a semiconductor test header device using the same by implementing an ALPG-implemented chip and an ASIC PE chip on a single PCB.

The ALPG of the semiconductor test pattern signal multiplication / dividing apparatus according to the embodiment of the present invention outputs a test pattern signal to the PE unit according to a control signal transmitted from the control computer through the interface unit. The test pattern signal output at this time is a low frequency digital signal.

The signal processing unit of the PE unit multiplies the test pattern signal transmitted from the ALPG to the frequency required by the ATE, and records the multiplied test pattern signal to the DUT through a driver. On the other hand, the comparator receives a read signal of the test pattern recorded in the DUT by the driver, compares it with the reference signal, and outputs the comparison signal according to the comparison result back to the signal processor. The signal processor divides the corresponding comparison signal into a low frequency signal required by the ALPG or the control computer, transmits the divided comparison signal to the ALPG, and the ALPG transmits the comparison signal to the control computer connected through the interface unit.

At this time, the test pattern signal output from the ALPG is a parallel digital signal, and the comparison signal input by the comparator is a serial digital signal. Therefore, the signal processor according to the present invention multiplies the test pattern signal output from the ALPG through serialization, and divides the comparison signal output from the comparator through parallelization, thereby requiring the ATE. Not only the high frequency signal can be satisfied but also the comparison signal output as the high frequency signal can be output as the low frequency signal required by the ALPG.

Therefore, the semiconductor test pattern signal multiplication / dividing apparatus according to the present invention transfers a portion of the low frequency test pattern signal output from the ALPG to the PE unit, and integrates the PE test unit with the original function of the PE unit, thereby integrating the semiconductor test system. It is possible to improve the efficiency of the ALPG-implemented chip and the integrated PE chip can be mounted on a single PCB has the advantage that the cost and size can be miniaturized.

The foregoing and further aspects of the present invention will become more apparent through the preferred embodiments described with reference to the accompanying drawings. Hereinafter, the present invention will be described in detail to enable those skilled in the art to easily understand and reproduce the present invention.

4 is a block diagram schematically illustrating a semiconductor test header device according to an exemplary embodiment of the present invention, and FIG. 5 is a block diagram schematically illustrating a PE (Pin Electroic) unit according to an exemplary embodiment of the present invention. . As shown, the semiconductor test header device according to the present invention includes an ALPG 110 for generating and outputting a parallel test pattern signal for a semiconductor test, and a test pattern having a plurality of input / output channels according to the test pattern signal. Driver 131 for recording the data, a comparator 133 for outputting a comparison signal comparing the reference signal and the read signal of the test pattern recorded on the test semiconductor by the driver 131, and the parallel output from the ALPG 110. Serializes the test pattern signal, multiplies the test pattern signal, and parallelizes the comparison signal serially output from the serializer 135-1 and the comparator 133 to output to the driver 131. And the PE unit 130 including the signal processing unit 135 including the parallelizing unit 135-3 for dividing and outputting the output to the ALPG 110. It is configured to include an interface unit 170 that interfaces between the transmission and reception of data for controlling the overall system control computer and ALPG (110).

In addition, the plurality of test target semiconductors write test patterns to the semiconductors to the semiconductors output by the driver 131 of the PE unit 130, and output the read signals of the recorded test patterns to the comparator 133. The DUT 150 is provided.

The ALPG 110 outputs a test pattern signal used for reading and writing data of a memory device, and may be implemented with, for example, an FPGA or an ASIC. The test pattern signal output from the ALPG 110 is a digital parallel signal, and the test pattern signal is output to the signal processor 135.

The interface unit 170 may be a connector for transmitting and receiving data between the ALPG 110 and the control computer. The interface unit 170 may receive a control signal from the control computer, output the control signal to the ALPG 110, and output a comparison signal from the ALPG 110. Output to the control computer.

The DUT 150 includes a plurality of test target semiconductors, writes a test pattern into semiconductors on each of the semiconductors output by the driver 131 of the PE unit 130, and comparates the read signal of the written test pattern. Output to (133).

 The DUT 150 may be formed by a BGA method. The BGA is arranged in a two-dimensional array of hemispherical solder terminals on a back side of a semiconductor under test, that is, a bare chip. It is a large integrated circuit package (LSI) that replaces the lead. BGAs can be made smaller in LSI packages with a large number of terminals, and 225-460 pin packages are put to practical use. It is used as a package for an application-specific semiconductor (ASIC), a high-speed static RAM (SRAM), and the like, and recently, varieties using a ceramic substrate and varieties using a plastic tape (TAB tape) as a substrate. In addition to double-sided boards, varieties using 4 to 6-layered multilayer boards have been developed for varieties using PCBs.

The PE unit 130 is a circuit for directly applying a current and voltage according to a test pattern to a semiconductor provided in the DUT 150. The PE unit 130 receives a test pattern signal output from the ALPG 110 and records the test pattern signal in the DUT 150. The read signal of the test pattern recorded in the DUT 150 is received and compared with the reference signal, and the comparison signal according to the comparison result is output to the ALPG 110. That is, the PE unit 130 converts the digital test pattern signal output from the ALPG 110 into an analog signal and applies it to the DUT 150, and converts the read signal of the test pattern, which is an analog signal, into a digital signal to convert the ALPG 110 into a digital signal. ) Is a circuit to output.

According to an aspect of the present invention, the PE unit 130 according to the present invention multiplies the test pattern signal of the low frequency output from the ALPG 110 by the high frequency signal required by the ATE and the DUT 150 through the driver 131. The high frequency comparison signal output from the comparator 133 is divided into a low frequency signal required by the ALPG 110 and output. The description of the PE unit 130 will be described in more detail with reference to FIG. 5.

As shown in FIG. 5, the PE unit 130 according to the present invention includes a driver 131 for recording a test pattern into an inspection target semiconductor having a plurality of input / output channels according to a test pattern signal, and a driver 131. The comparator 133 outputs a comparison signal obtained by comparing the read signal of the test pattern recorded on the test semiconductor with the reference signal, and the test pattern signal of the test target semiconductor output from the ALPG 110 is serialized. And a signal processing unit 135 for outputting to the 131, parallelizing the comparison signal output from the comparator 133, and outputting the parallelized signal to the ALPG 110.

The driver 131 receives the digital test pattern signal multiplied by the signal processing unit 135 and applies a corresponding analog signal, that is, a current and a voltage, to the DUT 150 to record the test pattern in the DUT 150. do.

The comparator 133 compares the test pattern readout signal read from the test pattern recorded in the DUT 150 with a preset reference value according to the semiconductor characteristics, and compares the comparison signal according to the comparison result to the signal processor 135. Output The comparator 133 is a kind of comparator. The comparator 133 converts the level of the test pattern readout signal read from the DUT 150 into a low or high digital signal by comparing it with a reference value, and converts the converted comparison signal into the signal processor 135. The comparison signal divided by the signal processor 135 is output to the ALPG 110 and output to the control computer through the interface unit 170 to test whether the semiconductor is operating correctly.

The signal processor 135 multiplies the low-frequency test pattern signal output from the ALPG 110 to the frequency band required by the ATE, outputs it to the driver 131, and compares the high-frequency band output signal from the comparator 133. Is divided into the low frequency band required by the ALPG 110 and outputted. Accordingly, the signal processor 135 according to the present invention serializes the test pattern signals output in parallel from the ALPG 110, multiplies the corresponding test pattern signals, and outputs them to the driver 131. And a parallelizing unit 135-3 parallelizing the comparison signal output from the comparator 133 to divide the comparison signal and output the parallel comparison signal to the ALPG 110. The description of the signal processor 135 will be described in more detail with reference to FIG. 6.

6 is a schematic diagram schematically illustrating a multiplication and division process of a test pattern signal of a signal processing unit according to an exemplary embodiment of the present invention. As illustrated, when the semiconductor test system according to the present invention, that is, the test frequency band required by the ATE is 1 GHz and the test pattern signal output from the ALPG 110 is 250 MHz, the serialization unit 135-1 may use ALPG ( It receives the 250MHz 4bit parallel test pattern signal output from 110) and stores it in 4bit queue, and outputs it as 1GHz signal required by ATE by merging 4bit parallel signals stored in the queue into 1bit serial signal. It will be possible. Accordingly, the serialization unit 135-1 may multiply the low frequency test pattern signal 250 MHz output from the ALPG 110 into a high frequency signal (1 GHz) required by the ATE and output the multiplication unit.

The parallelizing unit 135-3 may be referred to as a concept opposite to the serializing unit 135-1 described above. That is, the test pattern readout signal read from the DUT 150 is a high-speed analog signal of 1 GHz, and the comparator 133 receives it, compares the level of the analog signal with a reference value, and compares the digital comparison signal according to the comparison result. This comparison signal is also a high frequency signal of 1GHz. This high frequency signal cannot be used as an input of ALPG 110 to process a 250 MHz relatively low frequency signal.

Accordingly, the parallelizing unit 135-3 divides the 1 GHz serial 1 bit comparison signal output from the comparator 133 into a 250 MHz 4 bit signal and stores them in a queue, and parallel outputs the 250 MHz 4 bit signal stored in the queue. Thus, the 1 GHz comparison signal can be divided into 250 MHz that can be processed by the ALPG 110.

Reference numeral 135-5 is a phase locked loop (PLL) which is a frequency negative feedback circuit configured to keep the frequency of the output signal constant at all times.

Therefore, the PE unit 130 of the semiconductor test header device according to the present invention multiplies and outputs the test pattern signal of the low frequency ALPG 110 through the signal processor 135 to a high frequency signal required by the ATE, and then comparator ( By dividing the high frequency signal output from 133 into a low frequency signal that can be processed by the ALPG 110, the ALPG 110 capable of processing low frequency signals can be used without any change in an ATE requiring high frequency signal. It has the advantage of low cost and small size FPGA or ASIC.

Meanwhile, a plurality of input / output channels exist in a semiconductor, and a test pattern signal is simultaneously applied to a plurality of input / output channels in the test process of the semiconductor, and reading is performed at the same time. However, since the input and output of the signals of the channels present in the DUT 150 cannot be performed at the same time in real time, synchronization according to the time difference between the input and output signals of the respective channels is required. Therefore, the test pattern signal output from the ALPG 110 and multiplied and then transmitted to the respective channels by the driver 131 should be simultaneously output to the DUT 150 and the comparison signal output by the comparator 133. It should also be input to ALPG 110 at the same time.

In order to compensate for the time difference between the signals, the PE unit 130 according to the present invention is a serialization unit of the signal processor 135 so that the driver 131 can simultaneously write a test pattern on all channels existing in the DUT 150. The time difference between the test pattern signals output from the 135-1 is synchronized and output, and the comparison signal output from the comparator 133 is also synchronized to be input to the ALPG 110 at the same time. Accordingly, the PE unit 130 according to the present invention compensates the delay time of the comparison signal input to the ALPG 110 through the inter-channel test pattern signal or the comparator 133 multiplied and output by the signal processor 135. The delay compensation unit 137 is included.

The delay compensator 137 compensates and synchronizes the time difference so that the serialized test pattern signal output by the ALPG 110 can be simultaneously output to each channel, and simultaneously outputs the synchronized signals to the driver 131. The driver 131 transmits the synchronized test pattern signal to each channel of the DUT 150 to simultaneously record the test pattern.

In addition, the delay compensator 137 compensates and synchronizes the time difference of each channel-specific signal so that the channel-specific comparison signal output from the comparator 133 can be simultaneously input to the ALPG 110, and synchronizes the synchronized comparison signal. It outputs to the parallelization part 135-3 of the process part 135.

The delay compensator 137 is driven by a reference clock. For example, when the reference clock is at a high level, the delay compensator 137 simultaneously outputs a channel-specific test pattern signal transmitted from the signal processor 135, and when the reference clock is at a low level. By simultaneously outputting the comparison signal for each channel transmitted from the comparator 133 to the parallelizing unit 135-3 of the signal processing unit 135, it is possible to compensate and synchronize the time difference between the signals for each channel.

According to a characteristic aspect of the present invention, the PE unit 130 according to the present invention is preferably integrated on a single chip while maintaining its characteristics, and particularly, an ASIC (Application) structure suitable for ATE requiring high-speed test characteristics in the GHz band. Specific Integrated Circuit) is possible. Therefore, it is possible to implement a system that performs performance until the next generation without changing the overall system structure.

In the semiconductor test pattern signal multiplication / dividing device and the semiconductor test header device using the same, a portion for converting a low frequency test pattern signal output from ALPG into a high speed test pattern signal required by ATE is transferred to PE. By integrating into a single chip, the ALPG for low frequency signal processing can be used in ATE requiring high frequency signals, and it has the advantage of enabling low cost and small size FPGA or ASIC.

In addition, the semiconductor test pattern signal multiplication / dividing device and the semiconductor test header device using the same according to the present invention, the ALPG chip and the ASIC-formed PE by ASIC part of the part that multiplies the low frequency test pattern signal output from the ALPG The chip can be mounted on a single PCB, and there is no need for a connection circuit for separately connecting the ALPG chip and the PE chip, thereby miniaturizing the size.

The present invention has been described above with reference to the preferred embodiments, but is not limited thereto, and is interpreted by the appended claims intended to cover many modifications that will be apparent to those skilled in the art without departing from the scope of the present invention. Should be done.

Claims (7)

A driver for writing a test pattern to an inspection target semiconductor having a plurality of input / output channels according to the test pattern signal; A comparator for outputting a comparison signal obtained by comparing a reference signal with a read signal of a test pattern recorded in the test semiconductor by the driver; A semiconductor test pattern including a signal processor that serializes a test pattern signal of an inspection target semiconductor output from an algorithm pattern generator (ALPG) and outputs it to the driver, and parallelizes a comparison signal output from the comparator to an ALPG. Signal multiplication / dividing device. The method according to claim 1, And a delay compensator for compensating for a delay time of an inter-channel test pattern signal multiplied by the signal processor and a comparison signal input to the ALPG through the comparator. Device. The method of claim 1, wherein the signal processing unit A serialization unit serializing a test pattern signal output from the ALPG in parallel and multiplying the test pattern signal to output the test pattern signal to the driver; And a parallelizing unit for parallelizing a comparison signal serially output from the comparator to divide the comparison signal and output the parallel signal to the ALPG. The method according to any one of claims 1 to 3, The semiconductor test pattern signal multiplication / dividing apparatus is implemented as a single chip with an application specific integrated circuit (ASIC). An algorithm pattern generator (ALPG) for generating and outputting parallel test pattern signals for semiconductor testing; A driver for writing a test pattern to an inspection target semiconductor having a plurality of input / output channels according to the test pattern signal, and a comparator for outputting a comparison signal comparing a reference signal and a read signal of the test pattern recorded on the inspection semiconductor by the driver And serializing a test pattern signal output in parallel from the ALPG to multiply the test pattern signal and parallelize the comparison signal output from the comparator and the serialization unit outputting the test pattern signal to the driver. A PE (Pin Electronic) unit including a signal processing unit including a parallelize unit outputting the ALPG; And a interface unit for interfacing data between the control computer controlling the overall semiconductor test system and the ALPG. The method according to claim 5, wherein the PE portion: And a delay compensator configured to compensate a delay time of a test pattern signal output from the serializer or a comparison signal output through the comparator. The method according to claim 5 or 6, And the PE unit is implemented as a single chip having an application specific integrated circuit (ASIC).

Images