KR100851108B1 - Wafer level system in package and fabrication method thereof - Google Patents

Abstract

The present invention provides a package that uses a plurality of memory units at the wafer level as a substrate of a stacked semiconductor package and includes at least one semiconductor element stacked on one surface of the memory unit. The memory unit includes a rearrangement conductive layer on an upper surface of the memory unit, and common wirings connecting the same type terminals formed in each of the plurality of memory units are formed. At least one through hole is formed between the upper surface and the lower surface of the memory unit, and the through hole is electrically connected to a relocation conductive layer formed on a lower surface of the memory unit by filling a conductive material. According to the present invention, a separate substrate for stacking is not required, thereby reducing manufacturing costs, and reducing the length of electrical wiring inside the package, thereby reducing the time delay / distortion occurring during high frequency operation, thereby improving the electrical performance of the system. In addition, the package thickness can be reduced by using a plurality of memory chips as a single layer in the horizontal direction to configure the entire system.

Integrated Package, SIP, Memory Unit, Through Hole

Description

Wafer Level System-in-Package and Manufacturing Method Thereof {WAFER LEVEL SYSTEM IN PACKAGE AND FABRICATION METHOD THEREOF}

1 is a cross-sectional view showing an integrated package of a conventional PoP form.

2 is a plan view showing a semiconductor wafer on which a plurality of memories are formed.

3 is a plan view showing a top surface of a memory unit that is a substrate for laminating a system in package according to the present invention;

4 is a cross-sectional view of a memory unit of a system in package according to the present invention.

5 to 15 are flowcharts showing an example of the manufacturing process of the system in package according to the present invention.

16 is a cross-sectional view showing a system in a package according to an embodiment of the present invention.

Figure 17 is a cross-sectional view showing a system in a package according to another embodiment of the present invention.

18 is a sectional view showing a system in a package according to another embodiment of the present invention.

19 is a sectional view showing a system in a package according to another embodiment of the present invention.

*** Explanation of symbols for the main parts of the drawing ***

200: memory unit 205: solder bump

215: electrode pad 230: insulating layer

240: relocation conductive layer 250: insulating layer

260: through hole 280: relocation conductive layer

300: semiconductor element 310: passive element

330: underfill 340: molding

400: external circuit board

The present invention relates to a wafer-level system-in-package (SIP) and a manufacturing method thereof, and a novel stacked type in which a plurality of memories are used as a substrate for stacking at the wafer level and additionally stacked other semiconductor devices. It's about packages.

Semiconductors are at the center of all high-tech sectors, including spacecraft, aircraft, automobiles, and logistics, and system-on-chip (SoC), which integrates many circuit components into one chip, is in the spotlight. However, the system-on-chip method of stacking multiple circuits on a single chip has technical limitations in circuit integration. Recently, system in package (SiP), system on package (SoP), package on package (PoP), Various stacking technologies such as multi-chip packages (MCP) have been proposed as alternatives to overcome the limitations of circuit integration.

MCP technology, which integrates multiple memory chips, has recently achieved high capacity by stacking up to 16 levels of memory. While MCP stacks only memory, SiP, SoP, and PoP integrate non-memory or system semiconductors and system semiconductors such as memory and system semiconductors into one. SiP, SoP, and PoP stack each layer with various functions or connect them to the left and right. In the case of SiP, a plurality of circuits composed of separate chips are connected to each other and mounted in one package. Research on integrated packages such as MCP and SiP is rapidly progressing at home and abroad, and the market demand for advanced integrated packages is increasing by means of high performance and thinning of portable communication devices.

1 illustrates an integrated package of PoP schemes which are mainly used at present. The top package I includes a plurality of memories 10 stacked in an MCP manner, and the bottom package II is a logic device for performing various functions of a consumer device. Application elements and the like. The two packages are stacked and joined together by a Blll (Balll Grid Array) method.

This type of integrated package has a problem that it is difficult to meet the market demand due to the increased manufacturing cost and difficult to reduce the package thickness because the post-processing step is increased. In particular, there is a problem in that signal length and signal distortion occur during high frequency operation due to excessive wire length. In addition, since it is difficult to insert or mount a passive device constituting the system, there is a limitation in expanding an application field, and a passive device can only be mounted on an external circuit board such as a main board, not inside a package, and thus overall mounting area. This has been increased.

Meanwhile, in the conventional integrated package technology, a substrate for circuit integration is required separately, and an additional medium such as an interposer may be additionally used to increase the degree of freedom of the integrated package when fine pitch response is not possible on the substrate. Since the overall manufacturing cost is increased, the chip stacking technique is used between a plurality of memories, thereby increasing signal distortion and delay when the operating frequency and speed are increased.

As the market demand for integrated packages increases, there is an urgent need for the development of a new and simple structure that can be applied to various fields.

Accordingly, it is an object of the present invention to provide an integrated package of a novel structure in which the manufacturing process is simple and the integration of various components is easy.

In addition, another object of the present invention is to provide a package that is a new system that does not require a separate substrate for lamination.

It is another object of the present invention to provide a package that is easy to mount and smooth signal processing during high frequency operation.

Other objects and features of the present invention will be set forth in more detail in the following detailed description.

In order to achieve the above object, the present invention provides a package that uses a plurality of memory units at the wafer level as a substrate of a stacked semiconductor package and includes at least one semiconductor element stacked on one surface of the memory unit. do.

The memory unit includes a rearrangement conductive layer on an upper surface of the memory unit, and a common wiring connecting the same type of terminals formed in each of the plurality of memory units is formed. The semiconductor device and the memory unit stacked on the memory unit may be connected by solder bumps or wire bonding.

At least one through hole is formed between the upper surface and the lower surface of the memory unit, and the through hole is electrically connected to a relocation conductive layer formed on a lower surface of the memory unit by filling a conductive material. An external circuit board may be electrically connected to the bottom surface of the memory unit through solder bumps.

At least one passive element may be further stacked on the memory unit, and the semiconductor element stacked on the memory unit may be a plurality of semiconductor elements stacked in a multilayer structure bonded to each other with an adhesive material. An underfill material may be filled between the memory unit and the semiconductor device or the passive device, or may further include a molding part that covers and protects the memory unit and the semiconductor device as a whole.

In addition, the present invention uses a plurality of memories as a stacking substrate at the wafer level to form a relocation conductive layer on the upper surface of the memory, to form a through hole through the memory, and to fill the through hole with a conductive material, A method of manufacturing a package, which is a wafer level system, includes forming a relocation conductive layer on a bottom surface of a memory, and mounting one or more system semiconductor devices to be electrically connected to the top surface of the memory.

In the present invention, a system in a package (SIP) in which memory, logic circuits, and other electrical components are integrated in one package, a plurality of memory units are used as a substrate on a wafer in which the memory components are integrated. And other semiconductor elements and / or passive elements constituting the system are stacked on the memory unit substrate to implement one single system.

Therefore, according to the present invention, a stacking substrate necessary for a conventional package-on-package (POP) and multi-chip package (MCP) is not required separately, thereby reducing manufacturing costs, and reducing trenches to silicon through-holes. Holes are formed to reduce the length of electrical wiring inside the package, reducing time delay / distortion during high frequency operation, improving the electrical performance of the system.

In addition, in the conventional MCP, there is a limit in reducing the package thickness by vertically stacking memory chips, but in the present invention, since the entire system is configured by using a plurality of memory chips as a single layer in the horizontal direction, the package thickness can be reduced.

In addition, since the number of memory units used as the substrate can be determined according to the physical dimensions of the active chips constituting the entire system, the degree of freedom for configuring the system is increased, and thus the applications are varied. You can enlarge it.

2 illustrates a semiconductor wafer 100 formed by integrating a plurality of memory devices. In the wafer, fine size memory units 100a and 100b are formed adjacent to each other. These memory units are selected as the number required to implement the system and used as the substrate for stacking the system-in-package.

FIG. 3 is a plan view illustrating a system-in-package using a plurality of memory units 210a, 210b, 210c, and 210d as substrates as an embodiment of the present invention, and FIG. 4 illustrates a partial cross-sectional structure. For the description of the memory unit used as the substrate, FIGS. 3 and 4 exclude other elements or components constituting the system. The number of memory units 210a, 210b, 210c, 210d is determined to be an appropriate number necessary for constructing the system, and need not be limited to the illustrated embodiment.

In the memory units 210a, 210b, 210c, and 210d, electrical components (not shown) and metal wires (not shown), such as transistors and dielectrics, are formed therein and one or more electrode pads 215 are exposed on an upper surface thereof. The electrode pads 215 may be electrically connected to each other by the relocation conductive layer 240, and in particular, may be electrically connected between the same type of terminals to form a memory unit. Thus, the scribe lane 201 shown in the figure is shown for ease of understanding and does not physically separate each memory unit. Identification number 240 'shows common wiring of a relocation conductive layer electrically connecting between the same type of terminals. The number and shape of electrode pads, rearranged conductive layers, and common wirings of the memory units 210a, 210b, 210c, and 210d illustrated in FIG. 3 are shown by way of example in order to help understanding, but the present invention is not limited thereto. .

Portions other than the electrode pads 215 on the upper surface of the memory unit may be protected by the insulating layer 230, and the relocation conductive layer 240 may also be protected by the insulating layer 250. The through hole 260 penetrating the upper and lower surfaces is formed in a predetermined region of the memory unit. An insulating layer 270 and a relocation conductive layer 280 are formed on the bottom surface of the memory unit, and the relocation conductive layer 280 is a relocation conductive layer 240 on the top surface of the memory unit by a conductive material filled in the through hole 260. ) Is electrically connected. Another insulating layer 290 locally protects the rearrangement conductive layer 280 on the bottom surface of the memory unit, and solder bumps 205 are formed at the exposed portions of the relocation conductive layer 280. Through such a structure, a plurality of electrical elements, for example, an application processor, a multimedia processor, a baseband processor, and a digital signal processor (DSP), are provided on the upper surface of the memory units 210a, 210b, 210c, and 210d as substrates. In addition, various passive elements such as resistors, inductors, and capacitors may be mounted, and the bottom surface of the memory unit may be surface mounted on an external circuit board.

Hereinafter, the manufacturing process of the wafer level system phosphorus package according to the present invention will be described by way of example, and also the structure of the system phosphorus package according to the present invention will be described.

5 shows a cross section of a memory unit 200 used as a substrate for stacking a wafer level system in a package. 5 and other figures show only a memory unit of a portion of the wafer for convenience of description, in the actual manufacturing process, a plurality of system in packages are implemented for a plurality of memory units at the wafer level. The memory unit includes a plurality of unit memories 210a and 210b, and transistors, dielectric layers, metal wires, and the like are already formed in each memory.

An insulating layer 230 is formed on the upper surface of the memory unit to locally expose the plurality of electrode pads 215 (FIG. 6). A rearrangement conductive layer 240 is formed on the exposed electrode pads, and the rearrangement conductive layer may selectively make an electrical connection between the electrode pads. FIG. 7 is a cross-sectional view taken along line X-X 'of FIG. 3 and shows that some of the electrode pads are selectively interconnected by the common wire 240'.

The photoresist coating, exposure process, partial etching process, etc., which are performed to locally form the insulating layer, the rearrangement conductive layer, and other thin film layers, are well known to those skilled in the art, and thus detailed descriptions thereof will be omitted.

After the relocation conductive layer is formed, the insulating layer 250 is again formed (FIG. 8) to locally expose only a portion of the relocation conductive layer on the top surface of the memory unit. The exposed portion of the relocation conductive layer is used as a contact site for electrical connection with other semiconductor devices or passive devices, for example, wires or solder bumps may be contacted.

In the present invention, trenches or through-holes penetrating the memory unit are formed to allow surface mounting without a separate wire when the system-in package is mounted on an external circuit board. FIG. 9 is a cross-sectional view taken along the line Y-Y 'of FIG. 3, and illustrates a through hole 260 ′ vertically penetrating the memory unit 200. The through hole 260 ′ may be formed by a physical or mechanical method such as laser punching. However, when the thickness of the memory unit is not large, a chemical method such as local etching may be used, and a fine diameter through hole may be formed. It is also possible to use a combination of physical and chemical methods for this purpose.

The through hole 260 ′ serves as a medium for electrically connecting the top and bottom surfaces of the memory unit by the relocation conductive layer 240. To this end, the through hole 260 ′ is filled with a conductive material (FIG. 10). Identification number 260 denotes a through hole filled with a conductive material. In the case where the fine sized through hole is formed, the conductive material may not be filled to the bottom of the through hole, and for this purpose, the lower surface of the memory unit may be backgrinded to expose the conductive material to the lower surface of the memory unit (FIG. 11). ). This grinding process has the advantage of reducing the overall package thickness by reducing the thickness of the memory unit. If the thickness of the memory unit is small or the conductive material is completely filled in the through hole, the grinding process may be omitted.

An insulating layer 270 is locally formed on the bottom surface of the memory unit (FIG. 12), and a relocation conductive layer 280 is locally formed on the insulating layer to be electrically connected to the through hole 260 filled with the conductive material ( 13). The rearrangement conductive layer 280 at the bottom of the memory unit forms another insulating layer 290 to locally expose (FIG. 14), and form solder bumps 205 at the exposed portions of the relocation conductive layer (FIG. 15). .

Although not shown, one or more under bump metal layers may be formed in the exposed portions of the relocation conductive layer to promote electrical contact of the solder bumps.

As described above, after forming a plurality of memories as one unit at a wafer level and forming a substrate for a stacked package, non-memory elements such as system semiconductors and / or passive elements may be mounted on the upper surface of the memory unit.

FIG. 16 illustrates an exemplary system in a package according to an embodiment of the present invention, in which a semiconductor device 300 is bonded to a top surface of a memory unit 200 through solder bumps 305 and at least one passive component is bonded. The element 310 is directly bonded to the memory unit by solder bumps 315. The semiconductor device 300 includes logic circuit elements such as an application processor, a multimedia processor, a baseband processor, and a digital signal processor (DSP). An underfill 330 is filled under the semiconductor device and the passive device to protect the upper surface of the memory unit. Alternatively, the entire package may be protected by epoxy molding. The memory unit is surface mounted on the external circuit board 400 via the solder bumps 205 on the bottom surface.

17 illustrates another embodiment in which the semiconductor device 500 is electrically connected to the memory unit by a wire 505 on the upper surface of the memory unit 200, and the entire package is protected by the molding 340.

18 and 19 illustrate a plurality of semiconductor devices 300, 500, and 600 that are electrically stacked on the memory unit 200, and are electrically connected to the memory unit, respectively. 305 and the wires 505 and 605 maintain electrical contact with the memory unit. The plurality of stacked semiconductor devices may be bonded to each other with an adhesive film 510.

In addition, the number of stacked semiconductor devices may further increase depending on the needs of the application to be applied, and thus may also increase the electrical contact point with the memory unit.

In the above described exemplary embodiments of the present invention by way of example, but the scope of the present invention is not limited to these specific embodiments, the present invention is in various forms within the scope of the spirit and claims of the present invention May be modified, changed, or improved.

According to the present invention, high capacity, high functionality and high speed operation are possible, and a light and simple system-in-package can be implemented. In a package, a single system may be realized by integrating a plurality of memories, for example, one or more homogeneous memories and / or heterogeneous memories, a plurality of logic circuits, and various passive devices. By using a plurality of memory chips as a system-in-package substrate, it can be applied to a high-capacity system, and the wiring length between logic and passive elements is reduced, thereby greatly improving the electrical characteristics of the system and reducing the system-in-package. Can be implemented.

On the other hand, in view of the process, the present invention forms a system on the wafer in which the memory elements are integrated, which simplifies the manufacturing process and is advantageous for mass production. In addition, since the post-processing step is reduced and a separate substrate for stacking is not required, the manufacturing cost can be greatly reduced, and the insertion and mounting of passive components constituting the system can be easily performed, thereby greatly improving the process efficiency. In addition, by forming a trench through a through-hole structure it is possible to apply Surface Mounting Technology (SMT) it is easy to mount on an external circuit board.

Claims (17)

It is a system-in-package that uses a plurality of memory units at the wafer level in which memory elements are integrated as a medium serving as a substrate, and another semiconductor element is connected to the memory unit by solder bump or wire bonding to implement a single system. , The memory unit has a rearrangement conductive layer formed on an upper surface and a lower surface of the memory unit, and at least one through hole filled with a conductive material is formed to electrically connect the rearrangement conductive layer between the upper surface and the lower surface. Package that is a wafer level system. delete delete delete delete delete The package of claim 1, wherein at least one passive element is stacked in the memory unit. The package of claim 1, wherein an external circuit board is electrically connected to the other surface of the memory unit. The package of claim 1, wherein the semiconductor devices stacked in the memory unit are a plurality of semiconductor devices stacked in a multilayer structure bonded to each other with an adhesive material. The package of claim 1, wherein an underfill is filled between the memory unit and the semiconductor device. The package of claim 1, further comprising a molding covering the memory unit and the semiconductor device. The common wiring of claim 1, wherein common wirings connecting the same type terminals of the respective memory units are formed on upper surfaces of the plurality of memory units. Package that is a wafer level system. At the wafer level, using a plurality of memories as a stacking substrate, a relocation conductive layer is formed on the upper surface of the memory, Forming a through hole penetrating the memory, Filling the through hole with a conductive material, A relocation conductive layer is formed on the lower surface of the memory, Mounting at least one system semiconductor device on an upper surface of the memory to be electrically connected to the memory device; Package manufacturing method which is a wafer level system. 14. The method of claim 13, comprising mounting at least one passive element on the memory top surface. 15. The method of claim 13, wherein the semiconductor device comprises two or more devices stacked vertically. 14. The method of claim 13, comprising forming an underfill or molding protecting the top of the memory unit. The method of claim 13, wherein a solder bump is formed on the bottom surface of the memory unit, And mounting a memory unit on an external circuit board via the solder bumps.

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