KR100843002B1 - duty cycle correction circuit and delay locked loop with the same - Google Patents

Abstract

The present invention improves signal integrity by correcting the duty distortion of the clock inside the chip to obtain a duty window of the output clock or a valid window of the output data, and thus a duty cycle correction circuit applicable to a high speed chip and a delay locked loop having the same. A duty detector for detecting a duty mismatch according to a first and a second signal by receiving a duty-corrected clock signal having a different phase and switching to a level to provide a level, and a first detector detected by the duty detector. And a voltage comparator for comparing the pulse difference of the second signal to determine the duty difference, a counter for performing up counting or down counting according to the duty difference determined by the voltage comparator, and a value counted by the counter. Interpolation fac by adjusting at least one of the number and size of the inverters turned on or off according to the weight. a DCC mixer for changing the ctor) and a DCC controller for determining the weight and controlling the number of on / off inverters of the DCC mixer.

DLL, DCC, Closed Loop, Digital Interpolation

Description

Duty cycle correction circuit and delay locked loop with the same

1 is an overall block diagram of a delay locked loop having a DCC of the open loop digital type according to the prior art.

FIG. 2 is a detailed configuration diagram of the DCC mixer of FIG. 1.

3 is a timing diagram illustrating an operation waveform of the DCC mixer shown in FIG. 2.

4 is an overall block diagram of a delay locked loop having a DCC of the open loop digital type according to the present invention.

FIG. 5 is a detailed configuration diagram of the DCC mixer of FIG. 4.

6 is a circuit diagram illustrating in detail the duty detector of FIG. 4.

* Explanation of symbols for main parts of the drawings

110, 210: buffer 120, 220: delay loop portion

121, 221: first controller 122, 222: first delay line

123, 223: second controller 124, 224: second delay line

130, 230: duty cycle correction circuit 131: third phase detector

132, 235: DCC control unit 133, 231: first DCC mixer

134: second DCC mixer 140, 240: first model portion

150, 250: first phase detection unit 160, 260: second model unit

170 and 270: second phase detection unit 180 and 280: phase splitter

232: counter 233: voltage comparison unit

234: Duty Detector

The present invention relates to a closed loop digital duty cycle correction circuit and a delay locked loop (DLL) having the same.

In general, a delay locked loop (DLL) is a circuit used to synchronize an internal clock of a synchronous memory using a clock in a semiconductor memory device with an external clock without error. That is, a delay time occurs when an external clock is used internally. A delay locked loop is used to control the delay time so that the internal clock is synchronized with the external clock.

However, as the operation is gradually increased, such as DDR / DDR2 / DDR3 SDRAM, the performance of the delay locked loop (DLL) is greatly affected. As a result, the duty of the clock used in the DLL also becomes an important problem. If the clock duty becomes large, the design margin is reduced in circuit design. Therefore, in order to secure enough design margin, a duty cycle correction circuit (DCC) that corrects the duty of the clock is introduced into the DLL.

That is, when the high-speed devices output the data outwardly by the read operation, and two data are equally output in one cycle of the external clock, the valid window of the data is cleared to provide the best signal integrity. In order to do this, the output of the data inside the chip is required to control the output of data having a phase of 0 ° to 180 ° relative to the phase of the external clock.

The duty cycle correction circuit (DCC) corrects the duty error of an external clock or an internal clock for accurate phase output of such a control clock. The duty cycle correction circuit (DCC) is a closed loop analog type and an open loop digital type ( A phase mixer type is used.

First, the closed loop analog DCC shows high performance, but its large layout area, current consumption, and high-speed operation make it difficult to apply to high-speed devices.

Second, the open loop digital type (phase mixer type) DCC is a type suitable for high speed devices, including a phase mixer configured by connecting switch inverters in parallel and is mainly used for high speed devices.

1 is an overall block diagram of a delay locked loop having a DCC of an open loop digital type according to the prior art, and includes a buffer 110, a delay loop unit 120, a duty cycle correction circuit (DCC) 130, and a first model. The unit 140 includes a first phase detector 150, a second model unit 160, a second phase detector 170, and a phase splitter 180.

Referring to FIG. 1, the buffer 110 receives external clock signals CLK and / CLK and generates two clock input signals rclk and refclk having the same phase activated at the edge of the clock.

The delay loop unit 120 receives a clock input from the buffer 110 in response to the first comparison signal CP1 and the second comparison signal CP2 of the first phase detection unit 150 and the second phase detection unit 170. Delay the signal rclk by a predetermined time. In this case, the delay loop unit 120 includes a first controller 121, a first delay line 122, a second controller 123, and a second delay line 124.

The first controller 121 of the delay loop unit 120 adjusts the delay amount of the clock input signal rclk output from the buffer 110 according to the first comparison signal CP1 output from the first phase detector 150. Generate an adjustable first control signal. In addition, the first delay line 122 of the delay loop unit 120 has a first clock signal clk1 delaying the clock input signal rclk for a predetermined time in response to the first control signal output from the first controller 121. Create

The second controller 123 of the delay loop unit 120 delays the delay amount of the clock input signal rclk output from the buffer 110 according to the second comparison signal CP2 output from the second phase detector 170. Generate a second control signal that can be adjusted. Also, the second delay line 124 of the delay loop unit 120 delays and inverts the clock input signal rclk for a predetermined time in response to the second control signal output from the second controller 123. Create (clk2).

The duty cycle correction circuit 130 receives the first clock signal clk1 and the second clock signal clk2 from the delay loop unit 120 to generate the first mixed clock signal and the second mixed clock signal. At this time, the up edges of the first mixed clock signal and the second mixed clock signal are moved to the middle of two rising edges of the first clock signal clk1 and the second clock signal clk2, respectively, and the down edges are respectively A signal is moved between two falling edges of the first clock signal clk1 and the second clock signal clk2. In this case, the duty cycle correction circuit 130 includes a third phase detector 131, a DCC controller 132, a first DCC mixer 133, and a second DCC mixer 134.

The third phase detector 131 of the duty cycle correction circuit 130 receives inverted values of the first clock signal clk1 and the second clock signal clk2 from the delay loop unit 120, respectively, and receives the first clock. A phase detection signal is generated which indicates which one of the signal clk1 and the downward edge of the second clock signal clk2 is leading.

The DCC controller 132 of the duty cycle correction circuit 130 determines the weight K according to the phase detection signal input from the third phase detector 131. Here, the weight K may include a plurality of weighted signals.

The first DCC mixer 130 of the duty cycle correction circuit 130 receives the weight K from the DCC controller 132 and adds the value 1 minus the weight (1-K) to the first clock signal clk1. Then, a weight K is added to the second clock signal clk2 to generate a first mixed clock signal having an adjusted duty. The second DCC mixer 134 of the duty cycle correction circuit 130 receives the weight K from the DCC controller 132, adds the weight K to the first clock signal clk1, and adds the weight K to the second clock signal. At clk2, a value obtained by subtracting the weight from 1 (1-K) is added to generate a second mixed clock signal having an adjusted duty.

The first model unit 140 is a delay circuit modeling a delay path of an internal circuit provided with a clock and is a first mixed clock which is a clock signal of the first DCC mixer 133 whose duty is adjusted from the duty cycle correction circuit 130. The signal fbclk1 is input to compensate for a time difference between an externally applied clock and an actual internal clock, and generates a first compensation clock signal iclk1.

The first phase detector 150 receives the reference clock signal refclk output from the buffer 110 and compares it with the first compensation clock signal iclk1 output from the first model unit 140 to compare the first comparison signal ( CP1) is generated.

The second model unit 160 is a delay circuit modeling a delay path of an internal circuit provided with a clock, and a second mixed clock signal which is a clock signal of the second mixer 134 whose duty is adjusted from the duty cycle correction circuit 130. In response to the input of fbclk2, a time difference between an externally applied clock and an actual internal clock is compensated for, and a second compensation clock signal iclk2 is generated.

The second phase detector 170 receives the reference clock signal refclk output from the buffer 110 and compares it with the second compensation clock signal iclk2 output from the second model unit 160 to compare the second comparison signal ( CP2) is generated.

The phase splitter 180 generates two duty-corrected clock signals CLK and / CLK having a 0 ° phase and a 180 ° phase from the first mixed clock signal fbclk1 output from the first DCC mixer 133. do.

FIG. 2 is a detailed configuration diagram of the DCC mixer of FIG. 1, and FIG. 3 is a timing diagram showing an operation waveform of the DCC mixer shown in FIG. 2. The first and second DCC mixers represent the same configuration and operation, and will be described as a first DCC mixer for easy description.

Referring to FIGS. 2 and 3, the first DCC mixer 133 is configured as a phase mixer in which a plurality of switch inverters are connected in parallel and a drain is connected in common. In addition, the first DCC mixer 133 receives a first clock signal in which a rising edge of an input clock rclk generated by receiving the external clocks CLK and / CLK is aligned with an upward edge of the reference clock reflck. and a second clock signal clk2 in which a falling edge of the input clock rclk generated by receiving the external clocks CLK and / CLK is aligned with a downward edge of the reference clock refclk. Each is input as an input signal.

At this time, two input signals, the first clock signal clk1 and the second clock signal clk2, have high pulse widths tPH-D having different pulse widths by operations of the first and second delay lines 122 and 124. ) And tPL + D (low pulse width).

Then, the DCC mixer 133 receives the first clock signal clk1 having tPH-D (high pulse width) and the second clock signal clk2 having tPL + D (low pulse width) as input. An output of clkout is generated from the average of the sections in which the phases of clk1 and the second clock signal clk2 are inverted. Accordingly, tPH and tPL of clkout have a waveform having the same width.

At this time, the number of on / off of the inverter connected in parallel is fixed according to the control signal (s1 <0: n>) for setting the weight (K) output from the DCC controller 132 is determined the driving amount. Since the delay lock loop is configured as an open loop, the duty of the output clkout cannot be fed back in real time, so the design has to select and fix the appropriate on / off number.

However, since the delay lock loop is configured as an open loop, when a change in a process, a voltage, a temperature, etc. occurs, the phase to be corrected does not have an accurate intermediate value and thus has an error range. In addition, this phase error causes a decrease in the accuracy of the duty correction, which interferes with the high-speed operation of the chip.

Accordingly, an object of the present invention is to provide a closed loop digital duty cycle correction circuit insensitive to changes in process, voltage, temperature, and the like, and a delay locked loop having the same. .

Another object of the present invention is to provide a duty cycle correction circuit that can be applied to a high-speed chip by increasing the signal integrity by correcting the duty distortion of the clock inside the chip to secure a duty window of the output clock or a valid window of the output data, and To provide a delay locked loop.

A close loop digital duty cycle correction circuit and a delay locked loop having the same according to the present invention for achieving the above object are inputted to a level by receiving a duty-corrected clock signal having a different phase and switching to a level. A duty detector for detecting a duty mismatch according to the first and second signals, a voltage comparison unit for comparing a pulse difference between the first and second signals detected by the duty detector to determine a duty difference, and in the voltage comparison unit The interpolation factor is adjusted by adjusting at least one of a counter that performs up counting or down counting according to the determined duty difference, and the number and size of inverters that are turned on or off according to a weight determined as a value counted by the counter. A DCC mixer to change, and a DCC agent to determine the weight and to control the number of on / off inverters of the DCC mixer. It is to include a.

Preferably, the duty detector includes a differential amplifier configured to convert the first and second signals to a level such as a voltage to determine and amplify a duty mismatch and to charge the amplified first and second signals, respectively. It characterized in that it comprises a charge pump for detecting a duty that is mismatched using the difference.

Preferably, the counter is configured as one of a shift register type and a bidirectional type.

Preferably, the DCC mixer is configured as any one of a parallel structure of an inverter having the same width as a switch inverter, or a parallel structure of inverters having different widths.

Preferably, the DCC control unit may control an update time of the feedback loop, a switch on / off, and a reset function according to a normal state of a chip, a self refresh, and a power down state.

Preferably, the duty detector receives two clock signals having a 180 ° phase with each other.

A feature of the delay locked loop having a closed loop digital duty cycle correction circuit according to the present invention for achieving the above object is a clock input signal having the same phase that is activated at the edge of the clock receiving an external clock signal; A first clock signal which delays the clock input signal by a predetermined time in response to a first comparison signal and a second comparison signal output through a comparison between the buffer generating a reference clock signal and the reference clock signal and the compensated clock signal; And a delay loop unit for outputting a second clock signal, and a duty for generating a first mixed clock signal using a weight to which the duty cycle received the first clock signal and the second clock signal from the delay loop unit is applied and fed back in real time. A cycle correction circuit and a first mixed clock signal received from the duty cycle correction circuit to have different phases; A phase splitter for feeding back a duty-corrected clock signal and a first model receiving a first mixed clock signal from a duty cycle correction circuit to compensate for a time difference between an externally applied clock and an internal clock and generating a first compensated clock signal And a first phase detector for outputting, to the delay loop unit, a first comparison signal generated by comparing two signals as inputs of a reference clock signal output from a buffer and a first compensation clock signal output from a first model unit. A second model unit configured to receive a second clock signal from the delay loop unit to compensate for a time difference between an externally applied clock and an internal clock, and generate a second compensated clock signal; a reference clock signal and a first outputted from a buffer; A second comparison signal generated by comparing two signals as a second compensation clock signal output from a second model unit is output to the delay loop unit. Outputting a second phase detector.

Preferably, the delay loop unit may include a first controller configured to generate a first control signal capable of adjusting a delay amount of a clock input signal input from a buffer according to a first comparison signal input from the first phase detector, and the first controller A first delay line for generating a first clock signal delaying a clock input signal by a predetermined time in response to a first control signal input from the second signal, and a clock input from a buffer according to a second comparison signal input from the second phase detector; A second controller for generating a second control signal capable of adjusting a delay amount of the input signal, and a second clock signal for delaying a clock input signal by a predetermined time in response to the second control signal input from the second controller; And a second delay line.

Preferably, in the duty cycle correction circuit, an upward edge of the first mixed clock signal is moved between two rising edges of the first clock signal and the second clock signal, respectively, and the downward edge is respectively the first clock signal and the first edge signal. The signal is moved in the middle of two falling edges of the second clock signal.

Another feature of a delay locked loop having a close loop digital duty cycle correction circuit according to the present invention for achieving the above object is a delay locked loop having a duty cycle correction circuit, wherein It is characterized by consisting of the described structure.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments with reference to the accompanying drawings.

A preferred embodiment of a close loop digital duty cycle correction circuit and a delay locked loop having the same according to the present invention will be described below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, only the embodiments to complete the disclosure of the present invention and complete the scope of the invention to those skilled in the art. It is provided to inform you.

4 is an overall block diagram of a delay locked loop having an open loop digital type DCC according to the present invention, which includes a buffer 210, a delay loop unit 220, a duty cycle correction circuit (DCC) 230, and a first model. The unit 240 includes a first phase detector 250, a second model unit 260, a second phase detector 270, and a phase splitter 280.

Referring to FIG. 4, the buffer 210 receives external clock signals CLK and / CLK and generates two clock input signals rclk and refclk having the same phase activated at the edge of the clock.

The delay loop unit 120 receives a clock input from the buffer 210 in response to the first comparison signal CP1 and the second comparison signal CP2 of the first phase detector 250 and the second phase detector 270. Delay the signal rclk by a predetermined time. In this case, the delay loop unit 220 includes a first controller 221, a first delay line 222, a second controller 223, and a second delay line 224.

The first controller 221 of the delay loop unit 220 controls the delay amount of the clock input signal rclk input from the buffer 210 according to the first comparison signal CP1 input from the first phase detector 250. Generate an adjustable first control signal. In addition, the first delay line 222 of the delay loop unit 220 is the first clock signal clk1 delaying the clock input signal rclk for a predetermined time in response to the first control signal input from the first controller 221. Create

The second controller 223 of the delay loop unit 220 delays the amount of delay of the clock input signal rclk input from the buffer 210 according to the second comparison signal CP2 input from the second phase detector 270. Generate a second control signal that can be adjusted. Also, the second delay line 224 of the delay loop unit 220 delays and inverts the clock input signal rclk by a predetermined time in response to the second control signal input from the second controller 223. Create (clk2).

The duty cycle correction circuit 230 receives the first clock signal clk1 and the second clock signal clk2 from the delay loop unit 220 and performs a first mixing using the weighted K applied to the duty feedback fed back in real time. It generates a clock signal. At this time, the upward edge of the first mixed clock signal is moved to the middle of two rising edges of the first clock signal clk1 and the second clock signal clk2, respectively, and the downward edge is respectively the first clock signal clk1. ) And the second clock signal clk2 are moved to the middle of two falling edges.

The phase splitter 280 divides the first mixed clock signal fbclk1 output from the DCC mixer 231 into two duty-corrected clock signals CLK and / CLK having 0 ° phase and 180 ° phase. .

 In this case, the duty cycle correction circuit 230 includes a DCC mixer 231, a counter 232, a voltage comparator 233, a duty detector 234, and a DCC controller 235.

The duty detector 234 of the duty cycle correction circuit 230 receives two duty-corrected clock signals CLK and / CLK having a phase of 0 ° and a phase of 180 ° from the phase splitter 280, and thus the voltage level. Switch to to determine and amplify the duty mismatch according to DCC (RCKVO) and DCCB (FCKVO).

Then, the voltage comparator 233 of the duty cycle correction circuit 230 determines the duty difference by comparing the pulse difference between DCC (RCKVO) and DCCB (FCKVO), which are current or voltage signals determined / amplified from the duty detector 234. do.

The counter 232 of the duty cycle correction circuit 230 performs up counting or down counting through the up counting signal INC or the down counting signal DEC output according to the duty difference determined by the voltage comparator 233. Perform. In this case, various counters such as a shift register type and a bidirectional type may be applicable to the counter 232 according to the size and number of inverters of the DCC mixer 231.

The DCC mixer 231 of the duty cycle correction circuit 230 may determine the weight K based on the value CNT <0: n> counted by the counter 232 to adjust the number of inverters turned on or off. Alternatively, the interpolation factor is changed by controlling the number and size of the inverters that are turned on / off to output a clock without a phase error, that is, a duty error. Here, the weight K may include a plurality of weighted signals. In this case, the DCC mixer 231 may form inverters of the same size in parallel according to the type of the counter 232, or may combine the widths of the inverters turned on with different sizes. That is, as shown in FIG. 5, the switch inverter has a parallel structure of inverters having the same width or an inverter structure having different widths.

At this time, the DCC control unit 235 of the duty cycle correction circuit 230 determines the weight K according to the value counted by the counter 232 and controls to change the number of on / off inverters of the DCC mixer 231. In addition, the DCC controller 235 controls functions such as update time adjustment, switch on / off, reset, and the like of the feedback loop according to a normal state of the chip and a special function (self refresh, power down, etc.).

As described above, the DCC mixer 231 of the duty cycle correction circuit 230 receives the weight K determined by the DCC controller 235 through the counter 232, and then receives the first clock signal clk1 and the second clock signal clk2. ) Is added to the weight K to generate the first mixed clock signal having the duty adjusted, thereby correcting the duty distortion of the clock inside the chip to secure a duty window of the output clock or a valid window of the output data. You can do it.

The first model unit 240 receives a first mixed clock signal fbclk1, which is a clock signal of the DCC mixer 231 whose duty is adjusted, from the duty cycle correction circuit 230 and between the externally applied clock and the actual internal clock. Compensates the time difference and generates a first compensation clock signal iclk1.

The first phase detector 250 receives the reference clock signal refclk output from the buffer 210 and compares it with the first compensation clock signal iclk1 output from the first model unit 240 to compare the first comparison signal ( CP1) is generated.

The second model unit 260 receives the second clock signal clk2 from the delay loop unit 220 to compensate for a time difference between an externally applied clock and an actual internal clock and generates a second compensation clock signal iclk2. do. At this time, preferably, the second model unit 260 includes means corresponding to the conventional second mixer 134 therein, so that the second clock signal clk2 is not generated before generating the second compensation clock signal iclk2. Adjust the duty first.

The second phase detector 270 receives the reference clock signal refclk output from the buffer 110 and compares it with the second compensation clock signal iclk2 output from the second model unit 260. Create (CP2).

6 is a circuit diagram illustrating in detail the duty detector of FIG. 4.

As shown in FIG. 6, the duty detector 234 includes a charge pump CAP1 CAP2 and a differential amplifier AM1 AM2. At this time, the output of the duty detector 234 can be output as a current or a voltage according to the amplification method.

Referring to the operation of the duty detector 234, a high pulse of RCLK (CLK) of two duty-corrected clock signals CLK and / CLK having 0 ° phase and 180 ° phase output from the phase splitter 280 is generated. If it is larger than the high pulse of FCLK (/ CLK), it means that the amount of current flowing in the path is greater than the amount of current flowing in the path.

Then, the disable signal is applied to the external bias voltage VBIAS so that node B and node A are applied to two differential amplifier circuits. Thus, the first differential amplifier AM1 outputs a DCC (RCKVO) signal, and the second differential amplifier AM2 outputs a DCCB (FCKVO) signal. Accordingly, the amount of current flowing through the DCCB becomes smaller than the amount of current flowing through the DCC.

Accordingly, the duty detector 234 brings the difference in the amount of charge charged in the first capacitor CAP1 connected to the DCC (RCKVO) and the second capacitor connected to the DCCB (FCKVO). If the high pulse is larger than the high pulse of FCLK (/ CLK), the high pulse of the RCLK pulse becomes large, and thus the amount of charge charged in the DCCB is small and the level of DCCB is lower than that of DCC.

As such, the duty detector 234 receives the duty of the signal output from the phase splitter 280 in real time, counts at the counter 232 using the received duty, and then determines the weight K. By changing the number of on / off inverters of the DCC mixer 231 by using the weights, it is possible to determine weights adapted to changes in external processes, voltages, temperatures, and the like.

The duty cycle correction circuit and the delay locked loop having the same according to the present invention as described above have the following effects.

First, it operates at high speeds and can be used with any device that uses a duty cycle corrector (DCC).

Second, by constructing a closed loop digital DCC in DRAM with high-speed operation, it is possible to improve the signal integrity by implementing the clock without phase error, that is, the duty error of the clock, thereby improving the quality and production of high-speed products. .

Claims (10)

A duty detector for detecting duty mismatches according to the first and second signals that receive duty-corrected clock signals having different phases and convert them to current or voltage levels; A voltage comparator configured to compare a pulse difference between the first and second signals detected by the duty detector to determine a duty difference; A counter for performing up counting or down counting according to the duty difference determined by the voltage comparing unit; A DCC mixer changing an interpolation factor by adjusting at least one of the number and size of inverters turned on / off according to a weight determined by a value counted in the counter; And And a DCC controller for determining the weight and controlling the on / off inverter number of the DCC mixer to be changed. The method of claim 1, wherein the duty detector is A differential amplifier converting the first and second signals to a voltage or current level to determine and amplify a duty mismatch; And And a charge pump configured to charge the amplified first and second signals, respectively, to detect a mismatched duty by using a difference in the amount of charge charged. The method of claim 1, And the counter comprises one of a shift register type and a bidirectional type. The method of claim 1, wherein the DCC mixer A duty cycle correction circuit comprising any one of a parallel structure of inverters having the same width or a parallel structure of inverters having different widths as the switch inverter. The method of claim 1, And the DCC controller controls the update time of the feedback loop, the switch on / off, and the reset function according to the normal state of the chip, the self refresh, and the power down state. The method of claim 1, And the duty detector receives two clock signals having a 180 ° phase with each other. A buffer configured to receive an external clock signal and generate a clock input signal and a reference clock signal having the same phase activated at an edge of the clock; A delay for outputting a first clock signal and a second clock signal delaying the clock input signal by a predetermined time in response to the first comparison signal and the second comparison signal output through the comparison of the reference clock signal and the compensated clock signal; A loop portion; A duty cycle correction circuit configured to receive a first clock signal and a second clock signal from the delay loop unit and generate a first mixed clock signal using a weight to which the duty feedbacked in real time is applied; A phase splitter which receives a first mixed clock signal from the duty cycle correction circuit and feeds back duty corrected clock signals having different phases; A first model unit configured to receive a first mixed clock signal from a duty cycle correction circuit to compensate a time difference between an externally applied clock and an internal clock and to generate a first compensated clock signal; A first phase detector configured to output, to the delay loop unit, a first comparison signal generated by comparing two signals with a reference clock signal output from a buffer and a first compensation clock signal output from a first model unit as input; A second model unit configured to receive a second clock signal from the delay loop unit to compensate for a time difference between an externally applied clock and an internal clock and to generate a second compensated clock signal; And A delay including a second phase detector configured to output a second comparison signal, which is generated by comparing two signals as inputs, of a reference clock signal output from a buffer and a second compensation clock signal output from a second model unit; Fixed loops. The method of claim 7, wherein the delay loop unit A first controller generating a first control signal capable of adjusting a delay amount of a clock input signal input from a buffer according to a first comparison signal input from the first phase detector; A first delay line generating a first clock signal delaying a clock input signal by a predetermined time in response to a first control signal input from the first controller; A second controller for generating a second control signal capable of adjusting a delay amount of a clock input signal input from a buffer according to a second comparison signal input from the second phase detector; And And a second delay line configured to generate a second clock signal delaying a clock input signal by a predetermined time in response to a second control signal input from the second controller. 8. The system of claim 7, wherein in the duty cycle correction circuit The up edges of the first mixed clock signal are respectively moved between two rising edges of the first clock signal and the second clock signal, and the down edges are the two down edges of the first clock signal and the second clock signal, respectively. (falling edge) A delay locked loop, characterized in that the signal is moved to the middle. In a delay locked loop having a duty cycle correction circuit, The duty cycle correction circuit is a delay lock loop, characterized in that the structure of any one of claims 1 to 6.

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