KR100842737B1 - Pattern Forming Method of Semiconductor Device - Google Patents
Pattern Forming Method of Semiconductor Device Download PDFInfo
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- KR100842737B1 KR100842737B1 KR1020020013760A KR20020013760A KR100842737B1 KR 100842737 B1 KR100842737 B1 KR 100842737B1 KR 1020020013760 A KR1020020013760 A KR 1020020013760A KR 20020013760 A KR20020013760 A KR 20020013760A KR 100842737 B1 KR100842737 B1 KR 100842737B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
Abstract
본 발명은 반도체 소자의 패턴 형성 방법에 관한 것으로, 특히, 감광막의 상, 하부에 각각 상부 무반사층 박막 및 하부 무반사층 박막을 적용함으로써, 리소그래피 공정 중 회로의 선폭 변화를 방지할 수 있어서, 이에 의한 반도체 소자의 특성 저하를 방지할 수 있는 반도체 소자의 패턴 형성 방법에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a pattern of a semiconductor device, and in particular, by applying an upper antireflection layer thin film and a lower antireflection layer thin film to the upper and lower portions of the photoresist, respectively, it is possible to prevent the line width change of the circuit during the lithography process, The present invention relates to a method of forming a pattern of a semiconductor device capable of preventing the deterioration of characteristics of the semiconductor device.
상부 무반사층 박막, 하부 무반사층 박막, 간섭, 노칭, 스윙 현상Upper antireflection film, lower antireflection film, interference, notching, swing phenomenon
Description
본 발명은 반도체 소자의 패턴 형성 방법에 관한 것으로, 특히, 감광막의 상, 하부에 각각 상부 무반사층 박막 및 하부 무반사층 박막을 적용함으로써, 리소그래피 공정 중 회로의 선폭 변화를 방지할 수 있어서, 이에 의한 반도체 소자의 특성 저하를 방지할 수 있는 반도체 소자의 패턴 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a pattern of a semiconductor device, and in particular, by applying an upper antireflection layer thin film and a lower antireflection layer thin film to the upper and lower portions of the photoresist, respectively, it is possible to prevent a change in the line width of the circuit during the lithography process. The present invention relates to a method of forming a pattern of a semiconductor device capable of preventing the deterioration of characteristics of the semiconductor device.
최근, 반도체 소자가 고집적화됨에 따라, 회로의 레이아웃(layout)은 점차 치밀해지고 있으며, 이러한 집적 회로 소자의 미세화에 따라, 리소그래피 공정 중 회로 선폭의 변화는 소자의 특성 저하에 매우 큰 영향을 미치고 있다. 이러한 리소그래피 공정 중의 회로 선폭의 변화는 감광막 또는 감광막의 하부에 있는 투광 절연막의 두께 변화로 인하여 발생하는 감광막 내에서의 복합적인 간섭 현상(multiple interference) 때문에 일어나게 된다. 이러한 현상을 다른 말로 스윙(swing) 현상이라고도 하는데, 종래부터 이러한 스윙 현상을 방지하기 위한 다양한 패턴 형성 방법이 제안된 바 있다. In recent years, as semiconductor devices have been highly integrated, layouts of circuits have become more and more dense, and with such miniaturization of integrated circuit devices, a change in circuit line width during a lithography process has a great effect on deterioration of device characteristics. The change in circuit line width during this lithography process is caused by multiple interference in the photoresist film caused by the change in thickness of the photoresist film or the light-transmitting insulating film under the photoresist film. In other words, this phenomenon is also called a swing phenomenon. In the past, various pattern formation methods have been proposed to prevent such a swing phenomenon.
이러한 방법으로는 우선, 감광막에 빛에 대한 흡수율이 큰 염료를 첨가하여, 감광막 자체가 빛을 흡수하도록 함으로써, 간섭 현상의 발생을 방지하고, 이에 따라, 스윙 현상을 방지하는 방법이 있다. 그러나, 이러한 방법은 간섭 현상을 줄일 수는 있으나, 해상도 및 초점의 손실을 가져올 수 있는 단점이 있다. 이 때문에, 이러한 감광막을 사용하여 패턴을 형성할 경우, 패턴에 불량을 초래할 수 있으며, 이에 따라, 소자 자체에 불량을 초래할 수 있는 문제점이 있었던 것이 사실이다.As such a method, there is a method of preventing the occurrence of an interference phenomenon and thus preventing a swing phenomenon by first adding a dye having a high absorption rate to light to the photosensitive film so that the photosensitive film itself absorbs light. However, this method can reduce interference, but has a disadvantage in that loss of resolution and focus can be caused. For this reason, when a pattern is formed using such a photosensitive film, it is a fact that it may cause a defect in a pattern, and accordingly, there existed a problem which could cause a defect in the element itself.
이러한 문제점으로 인하여, 스윙 현상을 방지하기 위한 다른 방법으로써 감광막의 상부에 무반사층을 적용하여, 감광막과 공기와의 계면에서 빛의 반사를 줄임으로써, 간섭 현상의 발생을 막는 방법이 제안된 바 있다. 그러나, 이러한 방법을 사용할 경우에는 상기와 같은 스윙 현상은 어느 정도 방지할 수 있으나, 감광막과 기판과의 계면에서 일어나는 빛의 반사 및 이에 의한 노칭 현상은 방지할 수 없는 문제점이 여전히 존재하였으며, 이에 따라, 역시 패턴에 불량을 초래할 수 있었던 것이 사실이다.Due to this problem, a method of preventing the occurrence of interference by reducing the reflection of light at the interface between the photoresist and air by applying an antireflective layer on top of the photoresist as another method for preventing the swing phenomenon has been proposed. . However, when such a method is used, the above-described swing phenomenon can be prevented to some extent, but there is still a problem that the reflection of light occurring at the interface between the photoresist film and the substrate and the notching phenomenon due to the same cannot be prevented. Indeed, it is true that the pattern could also cause defects.
이 때문에, 감광막의 하부에 무반사층을 적용하는 방법이 제안된 바도 있으나, 이러한 방법을 사용할 경우, 감광막과 기판과의 계면에서 일어나는 반사 또는 이에 의한 노칭 현상은 방지할 수 있으나, 감광막과 공기와의 계면에서 일어나는 반사 현상은 방지할 수 없어서, 감광막에서의 간섭 현상으로 인해 일어나는 스윙 형상은 제대로 제어할 수 없게 된다.For this reason, a method of applying an anti-reflective layer to the lower portion of the photoresist film has been proposed. However, when such a method is used, it is possible to prevent the reflection or notching caused by the interface between the photoresist film and the substrate. The reflection phenomenon occurring at the interface cannot be prevented, so that the swing shape caused by the interference phenomenon in the photosensitive film cannot be properly controlled.
이러한 종래 기술의 문제점으로 인하여, 감광막 내에서의 간섭 현상으로 인하여 일어나는 스윙 현상을 제어할 수 있으면서도, 감광막과 공기와의 계면에서 일 어나는 반사 현상 및 이에 의한 노칭 현상을 방지할 수 있어서, 반도체 소자의 신뢰성 및 수율을 증가시킬 수 있는 패턴 형성 방법이 절실히 요구되어 왔다.
Due to the problems of the prior art, it is possible to control the swing phenomenon caused by the interference phenomenon in the photosensitive film, while preventing the reflection phenomenon and the notching phenomenon caused at the interface between the photosensitive film and the air, thereby preventing the semiconductor device. There is an urgent need for a method for forming a pattern which can increase the reliability and yield.
이에 본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여, 패턴 형성 공정시 감광막의 상, 하부에 각각 무반사층 박막을 적용함으로써, 감광막과 공기와의 계면에서의 빛의 반사를 최소화 할 수 있어서, 감광막 내에서의 간섭 현상에 의한 스윙 현상을 방지할 수 있는 동시에, 감광막과 기판과의 계면에서 발생하는 반사 현상 및 이에 의한 노칭 현상을 방지할 수 있는 반도체 소자의 패턴 형성 방법을 제공하는 데 있다.
Accordingly, an object of the present invention is to minimize the reflection of light at the interface between the photosensitive film and the air by applying a non-reflective layer thin film to the upper and lower portions of the photosensitive film during the pattern forming process, in order to solve the problems of the prior art as described above. It is possible to prevent the swing phenomenon caused by the interference phenomenon in the photosensitive film, and at the same time to provide a method for forming a pattern of a semiconductor device capable of preventing reflection phenomenon occurring at the interface between the photosensitive film and the substrate and thereby notching phenomenon. There is.
상기와 같은 목적을 달성하기 위하여, 본 발명은 하부 구조가 형성된 반도체 기판의 상부에 하부 무반사층 박막을 증착하는 단계;In order to achieve the above object, the present invention comprises the steps of depositing a lower anti-reflective layer thin film on top of a semiconductor substrate formed with a lower structure;
상기 하부 무반사층 박막의 상부에 감광막을 증착하는 단계;Depositing a photosensitive film on top of the lower antireflective layer thin film;
상기 감광막의 상부에 상부 무반사층 박막을 증착하는 단계; 및Depositing an upper anti-reflective layer thin film on the photoresist; And
상기 반사층 박막 및 감광막에 대해 식각을 진행함으로써, 패턴을 형성하는 단계로 구성됨을 특징으로 하는 반도체 소자의 패턴 형성 방법을 제공한다. By etching the reflective layer thin film and the photosensitive film, there is provided a pattern forming method of a semiconductor device, characterized in that it comprises a step of forming a pattern.
즉, 상기와 같은 본 발명에 의한 패턴 형성 방법에 따르면, 상기 상부 무반사층 박막은 빛의 파형이 밀리는 현상을 방지(phase shift cancellation)함으로써, 감광막 상부에서 빛의 반사를 방지하고, 이에 따라, 감광막 내에서의 간섭 현상을 억제하는 역할을 하게되며, 하부 무반사층 박막은 감광막을 통하여 유입되는 빛을 흡수(light absorption)함으로써, 감광막과 기판과의 계면에서 일어나는 반사 현상 및 이에 의한 노칭 현상을 방지하는 역할을 하게 되는 바, 이러한 상, 하부 무반사층 박막의 작용으로 인하여, 스윙 현상 및 노칭 현상을 동시에 제어할 수 있어서, 회로 선폭의 변화를 최소화할 수 있게 되는 것이다.That is, according to the pattern forming method according to the present invention as described above, the upper anti-reflective layer thin film prevents light waves from being pushed (phase shift cancellation), thereby preventing reflection of light on the photosensitive film, and thus, the photosensitive film The anti-reflective layer thin film absorbs light flowing through the photosensitive film, thereby preventing reflection and notching from occurring at the interface between the photosensitive film and the substrate. As a result, the action of the upper and lower anti-reflective layer thin films can simultaneously control the swing phenomenon and the notching phenomenon, thereby minimizing the change in the circuit line width.
상기 본 발명에 의한 패턴 형성 방법에 있어서, 상부 무반사층 박막은 실리콘옥시나이트라이드(SiON) 계열의 무기 물질을 사용하여 증착함이 바람직하며, 상기 물질을 증착함에 있어서는 통상의 증착 방법을 이용할 수 있으나, 특히, PECVD(Plasma-enhanced chemical vapor deposition) 방법을 이용하여 증착함이 바람직하다.In the pattern forming method according to the present invention, the upper antireflective layer thin film is preferably deposited using an inorganic material of silicon oxynitride (SiON) series, and in order to deposit the material, a conventional deposition method may be used. In particular, it is preferable to deposit using a plasma-enhanced chemical vapor deposition (PECVD) method.
또한, 상기 무반사 박막층의 두께는 248nm DUV 리소그래피의 경우, 200 내지 600Å의 범위로 함이 바람직하다. 이러한 두께로 적용함으로써, 반사율을 최소화할 수 있으며, 다른 리소그래피 공정에 적용하는 경우에는 하기의 식에 의하여, 바람직한 적용 두께를 계산할 수 있다.In addition, in the case of 248 nm DUV lithography, the thickness of the antireflective thin film layer is preferably in the range of 200 to 600 Hz. By applying at such a thickness, the reflectance can be minimized, and in the case of applying to other lithography processes, the preferred application thickness can be calculated by the following equation.
dTARC=λ/4nTARC.........식 1d TARC = λ / 4n TARC ......... Equation 1
nTARC=(nResist)1/2........식 2n TARC = (n Resist ) 1/2 ........ Equation 2
상기 식에서, dTARC는 상부 무반사층 박막의 두께(nm)이고, λ는 빛의 파장(KrF의 경우는 248nm)이며, nTARC는 상부 문반사층 박막의 굴절율이고, nResist는 감광막의 굴절율이다. Where d TARC is the thickness of the upper antireflective layer thin film (nm), λ is the wavelength of light (248 nm for KrF), n TARC is the refractive index of the upper door reflective layer thin film, and n Resist is the refractive index of the photoresist film.
그리고, 상기 본 발명에 의한 패턴 형성 방법에 있어서, 하부 무반사층 박막은 플로오르화실리콘나이트라이드(SiNxF) 또는 하기의 화학식 1의 구조를 가지는 폴리디페닐실란 공중합체(Polydiphenylsilane copolymer)를 이용하여 증착함이 바람직하며, 이를 증착함에 있어서는 역시 통상의 증착 방법을 사용할 수 있으나, 플로오르화실리콘나이트라이드를 사용하는 경우에는 ICPCVD(Inductively coupled plasma-enduced chemical vapor deposition) 방법을 이용하여 증착함이 바람직하다. In the pattern forming method according to the present invention, the lower anti-reflective layer thin film is made of silicon fluoride nitride (SiN x F) or a polydiphenylsilane copolymer having a structure represented by Chemical Formula 1 below. It is preferable to deposit, and in order to deposit the same, a conventional deposition method may be used, but in the case of using silicon fluoride, it is preferable to deposit using ICPCVD (Inductively coupled plasma-enduced chemical vapor deposition) method. .
(화학식 1)(Formula 1)
상기 플로오르화실리콘나이트라이드를 이용하여 하부 무반사층 박막을 증착하는 방법을 살펴보면, 실리콘하이드라이드(SiH4), 질소(N2), 아르곤(Ar), 니트로젠플로라이드(NF3)를 ICPVD 반응로로 유입시킨후, 200-300℃의 온도에서 200-600Å의 두께로 증착하게 되는 것이다. Looking at the method of depositing the bottom anti-reflective layer thin film using the silicon fluoride nitride, ICPVD reaction of silicon hydride (SiH 4 ), nitrogen (N 2 ), argon (Ar), nitrogen fluoride (NF 3 ) After entering the furnace, it is deposited to a thickness of 200-600- at a temperature of 200-300 ℃.
즉, 상기 패턴 형성 방법에 있어서는 반도체 소자의 패턴을 형성함에 있어서, 감광막의 상부에 실리콘옥시나이트라이드와 같이 빛의 파형이 밀리는 현상을 방지할 수 있는 물질로 구성된 무반사층 박막을 증착함으로써, 감광막과 공기와의 계면에서 빛의 반사가 일어나는 것을 방지할 수 있어서, 감광막 내에서의 간섭 현상 및 이에 의한 스윙 현상을 방지할 수 있는 동시에, 감광막의 하부에 플로오르화실리콘나이트라이드 또는 상기 화학식 1의 구조를 가지는 폴리디페닐실란 공중합체 와 같이 빛을 흡수할 수 있는 물질로 구성된 하부 무반사층 박막을 증착함으로서, 감광막과 기판과의 계면에서 반사가 일어나는 것을 방지할 수 있는 바, 이에 의하여, 노칭 현상을 방지할 수 있게 되는 것이다.
That is, in the pattern forming method, in forming a pattern of a semiconductor device, by depositing an antireflective layer thin film made of a material capable of preventing the wave of light, such as silicon oxynitride, from being pushed on top of the photosensitive film, It is possible to prevent the reflection of light at the interface with air, thereby preventing the interference phenomenon and the swing phenomenon in the photosensitive film, and at the same time, the silicon fluoride nitride or the structure of Chemical Formula 1 By depositing a lower anti-reflective layer thin film made of a material capable of absorbing light, such as polydiphenylsilane copolymer, it is possible to prevent reflection from occurring at the interface between the photosensitive film and the substrate, thereby preventing the notching phenomenon. You can do it.
상기에서 볼 수 있는 바와 같이, 본 발명의 패턴 형성 방법에 따르면, 빛의 파형이 밀리는 현상을 방지할 수 있는 상부 무반사층 박막 및 감광막을 통하여 유입되는 빛을 흡수할 수 있는 하부 무반사층 박막을 감광막의 상, 하부에 각각 적용함으로써, 리소그래피 공정 중 회로 선폭의 변화를 최소화할 수 있으며, 이에 따라, 회로 선폭의 변화에 의한 소자 특성의 저하를 방지할 수 있다.As can be seen from the above, according to the pattern formation method of the present invention, the photoresist is a film of the upper anti-reflective layer thin film that can prevent the wave of light is pushed and the lower anti-reflective layer thin film that can absorb the light flowing through the photosensitive film By applying to the upper and lower portions, respectively, it is possible to minimize the change in the circuit line width during the lithography process, thereby preventing the deterioration of device characteristics due to the change in the circuit line width.
또한, 본 발명에 의한 패턴 형성 방법에 있어서는 기존에 제안되었던 무반사층 구조에 비해 두께 조절의 마진 폭이 커서 공정이 쉽게 될 수 있으며, 플로오르화실리콘나이트라이드를 사용하여 하부 무반사층 박막을 형성하는 경우, 상기 화합물에 포함된 플로오르의 농도를 조절함으로써, 굴절률 및 소멸 계수를 쉽게 조절할 수 있는 바, 어떠한 공정에서도 감광막과의 간섭으로 생기는 간섭 현상을 최소화할 수 있게 된다. In addition, in the pattern formation method according to the present invention, the margin width of the thickness control is larger than that of the conventional antireflective layer structure, and thus the process can be easily performed. In the case of forming the lower antireflective layer thin film using silicon fluoride nitride, By adjusting the concentration of fluoro included in the compound, the refractive index and the extinction coefficient can be easily adjusted, thereby minimizing interference caused by interference with the photosensitive film in any process.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970017935A (en) * | 1995-09-11 | 1997-04-30 | 김광호 | How to form a fine pattern |
| KR19990060897A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Manufacturing Method of Semiconductor Device |
| KR20000001166A (en) * | 1998-06-09 | 2000-01-15 | 김영환 | Method for forming resist patterns |
| KR20000003358A (en) * | 1998-06-27 | 2000-01-15 | 김영환 | Fine pattern forming of semiconductor |
| JP2000195791A (en) * | 1998-12-28 | 2000-07-14 | Infineon Technol North America Corp | Method of reducing resist reflectance in lithography |
| KR20010021370A (en) * | 1999-08-25 | 2001-03-15 | 나카네 히사시 | Multilayered body for photolithographic patterning |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970017935A (en) * | 1995-09-11 | 1997-04-30 | 김광호 | How to form a fine pattern |
| KR19990060897A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Manufacturing Method of Semiconductor Device |
| KR20000001166A (en) * | 1998-06-09 | 2000-01-15 | 김영환 | Method for forming resist patterns |
| KR20000003358A (en) * | 1998-06-27 | 2000-01-15 | 김영환 | Fine pattern forming of semiconductor |
| JP2000195791A (en) * | 1998-12-28 | 2000-07-14 | Infineon Technol North America Corp | Method of reducing resist reflectance in lithography |
| KR20010021370A (en) * | 1999-08-25 | 2001-03-15 | 나카네 히사시 | Multilayered body for photolithographic patterning |
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