KR100834234B1 - Method for forming mask pattern for fabricating semiconductor device - Google Patents

Abstract

A method of determining a mask pattern for manufacturing a semiconductor device is provided to reduce complexity of a pattern through optical proximity correction without passing through complex simulation. A method of determining a mask pattern for manufacturing a semiconductor device comprises the following steps of: firstly expanding the line width of a connection part of first wiring patterns which are adjacent to each other and will be connected to adjacent contact regions to determine a first extension pattern(30); secondly expanding line width of the connection part to determine a second extension pattern having a first overlap region which overlaps with the connection part; expanding the first overlap region to define a second overlay region(42); defining a removal region, the overlap region between the second overlay region and the first extension pattern; and determining the final wiring pattern except for the removal region from the first extension pattern.

Description

Method for determining mask pattern for manufacturing semiconductor device {method for forming mask pattern for fabricating semiconductor device}

1 through 6 are mask pattern diagrams illustrating each step of a process of determining a mask pattern for manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

The present invention relates to a method for determining a mask pattern for manufacturing a semiconductor device, and more particularly, to a method for determining a mask pattern for manufacturing a semiconductor device, which can prevent a bridge between adjacent patterns appearing due to the optical proximity effect.

The high integration of devices in semiconductor devices is due in large part to the use of photolithography processes. Photomasks used in photolithography include circuit patterns corresponding to individual layers of the IC. This circuit pattern can be projected onto a target area, such as a die, on a semiconductor substrate coated with a layer of photosensitive material (resist). In stepper equipment, each pattern is projected on a step-by-step or scanning basis over the entire wafer.

This photolithography operation can be repeated for a plurality of layers. As a result, a device is formed on the substrate (wafer). These devices are separated from each other and form a completed semiconductor device through packaging.

The photo mask includes geometric patterns corresponding to circuit components that are integrated onto the silicon wafer. A CAD (Computer Aided Design) program can be used to form such a mask. The mask pattern forming operation may be referred to as EDA (Electronic Design Automation).

Certain rules apply to the formation of the mask pattern. Usually the CAD program has a set of predetermined design rules for mask formation. For example, design rules define spacing tolerances between circuit devices (such as gates, capacitors, etc.) or interconnect lines so that the circuit devices or lines do not interact in an undesirable manner. .

Typically, the design rule limitation is referred to as "critical dimensions" (CD). The critical dimension of the circuit may be defined as the minimum width of a line or hole or the minimum distance between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.

As the size of integrated circuits decreases and their density increases, the CD of the corresponding mask pattern approaches the resolution limit of the optical exposure tool. The resolution of the exposure tool is defined as the minimum pitch at which the exposure tool can be repeatedly exposed on the wafer.

With high integration of semiconductor device elements, circuit dimensions are also dramatically reduced. The ratio of exposure wavelength to numerical aperture of the imaging system must be reduced for image fidelity. The minimum pitch in chip designs must be gradually reduced to improve semiconductor device performance, and to address these challenges, exposure tools such as lens systems with shorter wavelength light sources and higher numerical aperture (NA) have been developed. On the other hand, in order to overcome the technical limitations of the manufacturing apparatus, the development of new photosensitizers, the development of modified mask technology, and the like are also made.

Improving the pattern technology to increase the integration density while using the photo equipment is the main issue of the pattern process. This is also referred to as RET (Resolution Enhancement Technology). As one of the RETs, in order to overcome the limitations imposed on current photolithography exposure tools, modification of the mask data through operation called optical proximity correction (OPC) is often obtained as an important momentum in advanced photolithography. Lose.

If the optical proximity effect of the mask pattern is not properly considered, pattern line width distortion occurs unlike lithography original exposure intention, which adversely affects semiconductor device characteristics. Therefore, semiconductor photolithography technology is a method of precisely controlling the design of the mask, so that the amount of light emitted by the mask can be properly adjusted, so that optical proximity correction (OPC) is formed by the pattern shape drawn on the mask. It is used as a method to minimize the distortion of light.

Meanwhile, the mask pattern for forming the upper wiring pattern connected to the lower contact region in the semiconductor device may be connected even when the lower contact region and the wiring pattern are partially displaced in position, that is, to enlarge the process margin. Techniques for artificially forming contacts and connection portions of wiring patterns are widely used. The pattern where both ends or portions are enlarged for contact and connection is called a dog bone pattern by focusing on the shape. When the extended pattern region is arranged adjacent to each other, the line width at the portion where one pattern and another pattern are adjacent to each other is formed. Is increased by the optical interference effect. If the line width is enlarged in the exposure process for manufacturing a semiconductor device, such a problem occurs as a short circuit between patterns.

In other words, the dog-bone style OPC pattern is a technique that can be used to easily obtain the overlay margin of the contact area when used well, but if the size is not properly considered, it is the easiest to cause the bridge between patterns. It's a technology.

Even in this case, it is necessary to determine the pattern shape so as to increase the process margin in terms of optical proximity correction while preventing the short circuit caused by the connection between the patterns.

According to the present invention, in order to increase the possibility of connection between patterns connected to each other, such as a lower contact region and an upper wiring pattern, that is, to increase the process margin, the enlarged portions are adjacent to each other while partially expanding the pattern width of the connecting portion. It is an object of the present invention to provide a method for determining a mask pattern for forming a semiconductor device that can be disposed to suppress a problem of causing a short circuit between patterns.

The mask pattern determination method for forming a semiconductor device of the present invention for achieving the above object,

Determining a primary expansion pattern by expanding a connection line of separate adjacent first patterns to be connected to a contact area adjacent to each other by a first line width relative to other portions;

Determining a secondary expansion pattern having a first overlap region overlapping each other by expanding the connection portion by a secondary line width;

Expanding the first overlap region to define a second overlap region;

Defining a removal region that is an overlapping region of the second overlapping region and the first extension pattern;

And determining a final mask pattern excluding the removal region from the first extension pattern.

In the present invention, the primary line width extension may be performed by a method of determining an area in which an extended contact region obtained by multiplying the contact region by a predetermined multiplication constant with respect to the center and an initial wiring pattern as a primary expansion pattern.

In the present invention, the multiplication constant used for the primary linewidth extension may use a numerical value used in a conventional pattern design, and the multiplication constant used for the secondary linewidth extension may be the same as the multiplication constant used for the primary linewidth extension. Or a simple constant such as '2'.

In the present invention, in the step of defining the second overlap region by expanding the first overlap region, the multiplication constant used for the first line width expansion or the second line width expansion may be equally applied.

In the present invention, the removal region may be formed so as not to overlap the original pattern.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

Referring to FIG. A typical initial wiring baton 10 and contact pattern 20 are shown. If the initial wiring pattern 10 is sufficiently apart, this is not a problem at all. However, if the original wiring pattern 10 is spaced apart at a specific interval as shown in FIG.

In the case of FIG. 2, the contact pattern 20 of FIG. 1 is expanded by a multiplication constant of a size 'a' to obtain an extended contact pattern 22. Then, the original wiring pattern 10 and the extended contact pattern 22 are merged to obtain a modified wiring pattern called a primary expansion pattern 30 as shown in FIG. 3. If this is expressed as an expression, it may be represented by the following first Boolean expression (Boolean Equation).

V1 = Sizing V by a (V is the initial contact pattern, V1 is the extended contact pattern)

M2 = M.OR. V1 (M2 is the primary expansion pattern, M is the initial wiring pattern)

As shown in FIG. 3, the wiring pattern was modified in the original style to secure the overlay margin of the contact pattern, but as the distance between the obtained primary expansion patterns became too close, short-circuit between patterns could be caused by light interference. have.

The following second Boolean equation can be used to easily block the bridge.

If you used 'a' as a multiplying constant to obtain an extended contact pattern, that is, a multiplying constant necessary to obtain an overlay margin, a, apply a multiplying constant of 2a to the initial contact pattern, or an extended contact pattern. By applying the multiplication constant "2" to it can be obtained a more extended contact pattern as shown in FIG. Of course, a second multiplication constant may use a separate multiplication constant called 'b'.

As a result of this expansion, the extended contact patterns 24 overlap each other. If you express this as

V2 = Sizing V by 2a (V2 is an extended contact pattern)

K1 = Overlapped area of V2 (K1 is the first overlapped area, which is an area overlapped by a further extended contact pattern)

K2 = Sizing K by 2a (K2 is the second overlap region obtained by extending the first overlap region by the multiplication constant 2a)

As expressed by the above equation, in FIG. 4, the area overlapped by enlarging the initial contact pattern 20 by 2a is referred to as the first overlapping area 40, and the enlarged K1 by 2a is the second area in FIG. 5. This is referred to as overlap region 42.

In this state, when the second overlapping region 42 is removed from the primary expansion pattern 30, which is the original style wiring pattern illustrated in FIG. 3, the final wiring pattern 60 as shown in FIG. 6 is obtained. This can be expressed as a complete Boolean equation:

V1 = Sizing V by a

V2 = Sizing V by 2a

K1 = Overlapped area of V2

K2 = Sizing K1 by 2a

Final Target (final wiring pattern) = (M .OR. V1) .NOT. K2

The final wiring pattern is obtained by the above equation. In the above example, 'a', '2a', etc. are used as multiplication constants, but other values may be applied or the values may be changed adaptively.

According to the present invention, a process margin of a contact connection area can be secured at a faster time than a hammer head type OPC using a rule based OPC method, and a bridge between wiring patterns, There is an advantage that the short circuit can be easily prevented.

In addition, by performing optical proximity compensation (OPC) without complex simulation, the complexity of the pattern can be reduced, so that the program run type for optical proximity compensation can be reduced, and the mask formation can be easily performed.

Claims (5)

Determining the primary expansion pattern by expanding the connection portions of the separate adjacent first wiring patterns to be connected to the adjacent contact regions with respect to the other portions by the first line width; Determining a secondary expansion pattern having a first overlap region overlapping each other by expanding the connection portion by a secondary line width; Expanding the first overlap region to define a second overlap region; Defining a removal region that is an overlapping region of the second overlapping region and the first extension pattern; And determining a final wiring pattern excluding the removal region from the first expansion pattern. The method of claim 1, And the first extension pattern is obtained by adding the extended contact region obtained by multiplying the contact region by a predetermined multiplication constant with respect to the center and the first wiring pattern. The method of claim 1, And a multiplying constant 'a' used for the primary linewidth extension and a multiplying constant 'b' used for the secondary linewidth extension are constant values. The method of claim 1, The method of determining a mask pattern for forming a semiconductor device according to claim 1, wherein 'a' or 'b' is used as a multiplication constant for the expansion even when the first overlap region is expanded to define the second overlap region. The method of claim 1, And the removal region is formed so as not to overlap with the initial wiring pattern.

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