KR100827287B1 - Semiconductor secondary memory unit and data saving method using the same - Google Patents

Abstract

A semiconductor secondary memory device and a data storing method using the same are provided to improve a data transfer rate of a DMA(Direct Memory Access) controller in interface with a host and improve a data storage rate by replacing a mechanical storage medium with a semiconductor memory device. A host interface unit(310) is connected to a system bus(200) and receives a command from a host. A memory controller(330) inputs and outputs data from a memory(350). A backup storage device controller inputs and outputs the data from a backup storage device(360). A DMA controller(320) reads or writes the data to the memory and a system main storage device(100) by controlling a memory controller or a backup storage device controller, and backs up or restores the data between the backup storage device and the memory by the command received from the host through the host interface unit. A power controller(370) supplies power received from an external PSU(Power Supply Unit) to each part. A sub PSU(380) supplies the power to the power controller when the power is abnormally supplied to each part from the external PSU. The power controller informs abnormal power supply to the DMA controller when abnormal power supply of the external PSU is detected.

Description

Semiconductor secondary memory device and data storage method using the same {Semiconductor Secondary Memory Unit and Data Saving Method Using the Same}

1 is a block diagram illustrating a configuration of a semiconductor auxiliary memory device according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a DMA control apparatus in FIG. 1; FIG.

3 is a flowchart illustrating a procedure of a data storage method using a semiconductor auxiliary memory device according to an embodiment of the present invention.

*** Explanation of symbols for the main parts of the drawing ***

100: system main memory 200: system bus

300: semiconductor auxiliary memory 310: host interface

320: DMA control unit 321: host interface control unit

322: DMA Status Register 323: DMA Status Machine

324: memory controller controller 325: first buffer

326: second buffer 327: backup storage controller controller

328: third buffer 329: fourth buffer

330: memory controller 340: storage controller for backup

350: memory 360: storage device for backup

370: power control unit 380: auxiliary power unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor auxiliary storage device and a data storage method using the same. And an auxiliary memory device for improving data storage speed by replacing a semiconductor (memory) with an FDD) and a data storage method using the same.

In general, the semiconductor auxiliary memory device has a function related to a direct memory connection (hereinafter referred to as DMA).

DMA is a bus feature of some computers that can send data directly from attached peripherals to storage media on the computer motherboard.

In the DMA scheme, the data transfer path is prevented from being limited by a central processing unit (CPU) or a microprocessor when transferring data between various auxiliary storage devices and the main memory device. Eliminating the central processing unit, the peripherals directly manage the memory bus to increase the transfer rate. In other words, the central processing unit or microprocessor is not involved in the data transfer, thereby increasing the overall computer performance.

In other words, during execution of the DMA function, the central processing unit rests without controlling the memory bus.

To this end, various DMA schemes in connection with the auxiliary storage device are defined on the specification. These specifications give users the flexibility to design their own DMA engines to meet their needs.

A representative engine among such DMA engines is a buffered DMA engine.

The buffer DMA manages information and addresses of a plurality of data frames in a structure named a buffer descriptor, and the buffer descriptors are connected in a linked list structure.

However, the DMA engines for the auxiliary memory that have been presented up to now are basically for the auxiliary memory using magnetization, and the speed control on the host interface side is developed because the magnetization speed is slower than that of the host interface part. It is not.

On the other hand, computer systems use data backup technology as a data storage technology in order to preserve large amounts of data for a long time or safely. Such data backup technology uses a backup schedule designated by a central processing unit for a predetermined time or space. It is a technique for setting a book and controlling and storing the auxiliary memory accordingly.

Such data backup refers to storing a copy in another separate storage space due to a backup policy that designates important data.

However, with the recent development of data transfer technology, the backup time increases exponentially with the increase of data capacity to be transferred. Therefore, if the backup policy is incorrectly set, the central processing unit performs other important tasks to perform the backup. There was a problem that the phenomenon that can not be performed.

In order to solve the above problems, the present invention improves the data transfer speed of the DMA control device at the interface with the host, and the storage medium is transferred from mechanical (for example, HDD and FDD) to semiconductor (memory). An object of the present invention is to provide a semiconductor auxiliary memory device and a data storage method using the same, which are intended to improve data storage speed.

In addition, the present invention backs up the data stored in the memory in the auxiliary storage device by itself, thereby reducing the load on the central processing unit when the auxiliary storage device performs other functions, and improves the data backup speed to increase reliability when storing data. , Its purpose is.

A semiconductor auxiliary memory device according to an embodiment of the present invention for achieving the above object is connected to a system bus to which an external power supply for supplying power and a system main memory device for storing data are connected. A semiconductor auxiliary memory having a memory as a storage means and a backup storage device, comprising: a host interface connected to the system bus and receiving a command from a host; A memory controller for inputting and outputting data into the memory; A backup storage controller for inputting / outputting data into the backup storage device; The memory controller and the backup storage controller are controlled to read or write data between the memory and the system main storage device according to a command from the host through the host interface unit, and data is written between the backup storage device and the memory. A DMA control device for backing up and restoring; And a power control unit for supplying power from the external power supply unit to the host interface unit, a memory controller, a backup storage controller, and the DMA control device.

Meanwhile, the data storage method using the semiconductor auxiliary memory device according to an embodiment of the present invention is connected to a system bus to which an external power supply unit for supplying power and a system main memory device for storing data are connected. A data storage method using a semiconductor auxiliary memory device having an in-memory and a backup storage device, comprising: a first step of checking a power supply error from the external power supply unit and analyzing a command from a host when there is no error; A second process of writing data to or reading data from the memory according to the analyzed command; And a third step of backing up the data recorded in the memory to the backup storage device or restoring the data backed up to the backup storage device to the memory according to the analyzed command.

According to an embodiment of the present disclosure, a semiconductor auxiliary memory device may include a host interface 310 and a DMA connected to a system main memory device 100 and a system bus 200 as illustrated in FIG. 1 in a computer system. The control device 320, the memory controller 330, the backup storage controller 340, the memory 350, the backup storage device 360, and the power control unit 370 are provided.

For example, the backup storage device 360 may include a hard disk (HDD), FDD, MMC, SD, PCMCI, and the like.

The DMA control device 320 is connected to the host interface 310, the memory controller 330, and the backup storage controller 340. The memory controller 330 is connected to the memory 350, and the backup storage controller 340 is connected to the backup storage 360. The power control unit 370 is connected to the system bus 200 and the auxiliary power supply unit 380.

The host interface 310 transmits a command from the host to the DMA control device, and externally outputs information from the DMA control device to the host. That is, the host interface 310 supports a physical connection according to the interface with the host.

For example, the host interface 310 may be a physical device such as Small Computer System Interface (SCSI), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect (PCI), PCI-X, and PCI Express, depending on the interface with the host. Support connection.

The DMA control device 320 controls the memory controller 330 according to a command received from the host through the host interface 310 to read or write data to the memory 350.

In addition, the DMA control device 320 controls the backup storage controller 340 according to a command received from the host through the host interface 310 to back up / restore data to the backup storage device 360.

As shown in FIG. 2, the configuration of the DMA control device 320 includes a host interface controller 321, a DMA state register 322, a DMA machine 323, and a memory controller. The controller 324, the first and second buffers 325 and 326, the backup storage controller controller 327, and the third and fourth buffers 328 and 329 are provided.

The host interface controller 321 analyzes a command from a host input through the host interface 310, writes information about the analyzed command into the DMA status register 322, and then writes the DMA state machine 323. ).

In addition, the host interface controller 321 checks whether the system bus 200 can be occupied in response to a request of the DMA state machine 323, and when the system bus 200 is occupied, After occupying a system bus 200 and connecting to the system main storage device 100 via the occupied system bus 200, the DMA state machine 323 is informed about this.

In addition, the host interface controller 321 analyzes a command from the host and, when the analyzed command is a data write, obtains data to be written to the memory 350 from the system main storage device 100 and executes the data. After buffering one buffer 325, the DMA state machine 323 is informed about this.

In addition, the host interface controller 321 writes the data buffered in the second buffer 326 to the system main memory device 100 according to the notification of the DMA state machine 323.

In addition, the host interface controller 321 releases the occupation of the system bus 200 when the command from the host is completed.

In addition, the host interface controller 321 writes data buffered in the second buffer 326 to the system main memory device 100 through the occupied system bus 200.

In addition, the host interface controller 321 continuously checks whether a data read error occurs while reading data from the memory 350, so that an error is not checked while reading data from the memory 350, and the memory 350 In the case where data reading is completed), the host reads that the data reading is normally completed through the host interface 310 and notifies the host, and notifies all modules involved in the data reading that the data reading is completed.

Here, the host interface controller 321 continuously checks whether a data read error occurs while reading data from the memory 350. In other words, the host interface controller 321 sends the second buffer 326 to the second buffer 326. While writing the buffered data to the system main memory device 100 through the occupied system bus 200, it means to continuously check whether a data read error has occurred.

In addition, when an error is confirmed while reading data in the memory 350, the host interface controller 321 analyzes the type of the identified error and outputs the result through the host interface 310 to the host. Notifies all modules involved in reading the data that the data reading is completed.

In addition, the host interface controller 321 interrupts communication with the host interface 320 according to the notification of supply power failure detection from the power controller 370, generates a self backup command, and provides information on the command. Write to DMA status register 322 to drive DMA state machine 323.

The DMA status register 322 receives and writes information on a data write / read / backup / restore command from the host interface controller 321.

The DMA state machine 323 controls each module such as the host interface controller 321, the memory controller controller 324, and the backup storage controller controller 327 according to the value of the DMA status register 322. It generates a command signal for monitoring the status of each module.

In addition, the DMA state machine 323 is the host interface control unit 321, the memory controller control unit 324, and the memory controller control unit 324 according to the information about the command recorded in the DMA state register 322 And a data transfer command between the backup storage controller controller 327.

The DMA state machine 323 also occupies the system bus 200 with the host interface controller 321 to access the system main storage device 100 in accordance with the information recorded in the DMA state register 322. Make a request.

In addition, the DMA state machine 323 informs the memory controller controller 324 that data to be written to the memory 350 is buffered in the first buffer 325 according to the notification of the host interface controller 321. Notify.

In addition, the DMA state machine 323 requests the memory controller controller 324 to read data from the memory 350.

In addition, the DMA state machine 323 notifies the host interface controller 321 that the second buffer 326 is buffered with data to be read from the memory 350.

In addition, the DMA state machine 323 checks whether data can be input to the backup storage device 360 to back up data to the backup storage controller controller 327 according to the information recorded in the DMA state register 322. Ask.

In addition, the DMA state machine 323 requests the memory controller controller 324 to back up data in the memory 350.

In addition, the DMA state machine 323 notifies the backup storage controller controller 327 that the data to be backed up from the memory 350 is buffered in the third buffer 328.

In addition, the DMA state machine 323 checks whether data can be output from the backup storage device 360 to restore data to the backup storage controller controller 327 according to the information recorded in the DMA state register 322. Ask.

The DMA state machine 323 also requests the backup storage controller controller 327 to restore data in the backup storage 360.

The DMA state machine 323 also informs the memory controller controller 324 that the data to be restored from the backup storage device 360 is buffered in the fourth buffer 329.

The memory controller controller 324 controls the memory controller 330 for connection to the corresponding memory 350 according to the type of the memory 350.

For example, the memory 350 may include dual data rate (DDR) SDRAM, DDR2 SDRAM, quad data rate (QDR) SDRAM, SRAM, FRAM, PRAM, and Flash Memory.

In addition, the memory controller controller 324 checks whether or not data can be input to the memory 350 to which data is to be written at the request of the DMA state machine 323, and when data can be input to the memory 350. The data buffered in the first buffer 325 is written or restored to the memory 350.

In addition, the memory controller controller 324 continuously checks whether a data write / restore error occurs while data is written / restored to the memory 350, and thus the error is not confirmed during data write / restore to the memory 350. When the data write / restore is completed in the memory 350, the host notifies the host that the data write / restore has been normally completed through the host interface 310, and notifies all modules involved in the corresponding data write / restore. Notify that data writing is completed.

In addition, the memory controller controller 324 analyzes the type of the identified error and outputs the result through the host interface 310 when an error is confirmed during data writing / restore to the memory 350. Notifies the host and notifies all modules involved in the data write / restore that the data write / restore is complete.

In addition, the memory controller controller 324 checks whether data can be output from the memory 350 to read data, and, when data can be output to the memory 350, obtains data to be read from the memory 350. And buffer it in the second buffer 326, then notify the DMA state machine 323 about it.

In addition, the memory controller controller 324 determines whether data can be output from the memory 350 to back up data, and when data can be output from the memory 350, the data to be backed up from the memory 350. And buffer it in the third buffer 328, then notify the DMA state machine 323 about it.

In addition, the memory controller controller 324 checks whether data can be input to the memory 350 to restore the data, and when data can be input to the memory 350, the data restoration is performed to the memory 350. Notify the DMA state machine 323 that it is possible.

In addition, the memory controller controller 324 restores the data buffered in the fourth buffer 329 to the memory 350 according to the notification of the DMA state machine 323.

The backup storage controller controller 327 controls the backup storage controller 340 for controlling an interface for a storage device for various backups.

In addition, the backup storage controller controller 327 generates a backup command by itself at predetermined time intervals and records the backup command in the DMA status register.

For example, since the backup storage controller 340 is made of a microprocessor, the backup storage controller 340 may independently perform backup without being influenced by an external device such as a central processing unit.

In addition, the backup storage controller controller 327 checks whether data can be input to the backup storage device 360 according to a request of the DMA state machine 323, and inputs data to the backup storage device 360. If this is possible, the backup storage device 360 is notified to the DMA state machine 323 that data backup is possible.

In addition, the backup storage controller controller 327 backs up the data buffered in the third buffer 328 to the backup storage device 360 according to the notification of the DMA state machine 323.

In addition, the backup storage controller controller 327 continuously checks whether a data backup error occurs while the data is backed up to the backup storage device 360, and makes an error while backing up data to the backup storage device 360. Is not confirmed, and when data backup is completed in the backup storage device 360, the host is output through the host interface 310 to inform the host that data backup is normally completed, and all the modules involved in the data backup are notified. Notify that data backup is complete.

In addition, the backup storage controller controller 327 analyzes the type of the identified error when the error is confirmed while backing up data to the backup storage device 360 and outputs the result of the host interface 310. It outputs through and notifies host and notifies all modules involved in data backup that data backup is completed.

In addition, the backup storage controller controller 327 checks whether data can be output from the backup storage 360 according to a request of the DMA state machine 323, and outputs data from the backup storage 360. If this is possible, the DMA state machine 323 is notified that data can be restored from the backup storage device 360.

In addition, the backup storage controller 340 retrieves the data to be restored from the backup storage 360 and buffers it in the fourth buffer 329, and then notifies the DMA state machine 323 about this. .

The first and second buffers 325 and 326 provide fast data transmission and transmission synchronization through buffering during data transmission between the host interface controller 321 and the memory controller controller 324.

In addition, the first buffer 325 receives data from the host interface controller 321 and buffers the data, and transfers the buffered data to the memory controller controller 324.

In addition, the second buffer 326 receives data from the memory controller controller 324 and buffers the data, and transfers the buffered data to the host interface controller 321.

The third and fourth buffers 328 and 329 provide fast data transfer and transfer synchronization through buffering during data transfer between the memory controller controller 324 and the backup storage controller controller 327.

In addition, the third buffer 328 receives the data from the memory controller controller 324 and buffers the data, and transfers the buffered data to the backup storage controller controller 327.

In addition, the fourth buffer 329 receives data from the backup storage controller controller 327 and buffers the data, and transfers the buffered data to the memory controller controller 324.

The memory controller 330 obtains data stored in the memory 350 under the control of the DMA control device 320 and provides the data to the DMA control device 320.

In addition, the memory controller 330 writes data to the memory 350 under the control of the DMA control device 320.

The backup storage device controller 340 takes data stored in the backup storage device 360 under the control of the DMA control device 320 and provides the data to the DMA control device 320.

In addition, the backup storage device controller 340 backs up data to the backup storage device 360 under the control of the DMA control device 320.

The power control unit 370 receives power from an external power supply unit (not shown) through the system bus 200 and stores the power in the host interface 310, the DMA control unit 320, the memory controller 330, and the backup. Supply to device controller 340, respectively.

In addition, the power control unit 370 checks whether there is an abnormality of the supply power from the external power supply unit and notifies the DMA control device 320 when a supply power supply abnormality is detected, and the host interface (380) from the auxiliary power supply unit 380. 310, power to be supplied to the DMA control device 320, the memory controller 330, and the backup storage controller 340, respectively.

Specifically, the power control unit 370 checks whether the power supplied from the external power supply unit is abnormal and notifies the host interface control unit 321 of the DMA control apparatus 320 when an abnormal state is detected.

In addition, the auxiliary power supply 380 is made of a rechargeable battery, and usually charges itself to maintain a constant voltage by using the power of the external power supply.

In the above-described configuration, a data storage method using a semiconductor auxiliary memory device according to an exemplary embodiment of the present invention will be described with reference to the drawings shown in FIG. 3.

First, in the semiconductor auxiliary memory device 300, when there is no abnormality in the corresponding power supply while receiving power from an external power supply unit through the system bus 200, the DMA control device 320 and the memory controller ( 330 and the backup storage device controller 340 receive power from the power control unit 370 and perform their own reset (initialization) (step S31).

For example, the power control unit 370 considers the case where the voltage of the supply power supply from the external power supply unit falls below a reference voltage (for example, 4.7V) or less.

Thereafter, when a host inputs a data write / read / backup / restore command through the host interface 310, the host interface 310 transmits the received command to the host interface controller 321.

Then, the host interface controller 321 analyzes the command received through the host interface 310.

Specifically, the host interface controller 321 determines whether a command input through the host interface 310 relates to data read / write between the host and the memory 350 or is for backup with the memory 350. It is checked whether data backup / restore is among the storage devices 360 (step S32).

In this case, when the command relates to data read / write between the host and the memory 350, the host interface controller 321 determines whether the command reads or writes data between the host and the memory 350. Check (step S33).

As a result, when the command corresponds to writing data between the host and the memory 350, the host interface controller 321 writes information about the command into the DMA status register 322, and the DMA Run state machine 323.

Accordingly, the DMA state machine 323 occupies the system bus 200 with the host interface controller 321 to access the system main memory 100 according to the information recorded in the DMA state register 322. After making a request (step S34), the result is awaited. That is, the DMA state machine 323 waits for the occupancy response of the system bus 200 from the host interface controller 321.

In this case, the DMA state machine 323 waits for receiving the occupancy response of the system bus 200 from the host interface controller 321, and the data amount and block of data to be written to the memory 350. The size is calculated and a data communication connection is prepared between the host and the memory 350 for data writing. That is, communication between the host interface controller 321 and the memory controller controller 324 is connected.

Accordingly, the host interface controller 321 checks whether the system bus 200 can be occupied at the request of the DMA state machine 323 (step S35). That is, it is checked whether the system bus 200 is in use by another system.

In this case, when the occupation of the system bus 200 is possible, the host interface controller 321 occupies the system bus 200 and the system main storage device 100 through the occupied system bus 200. Accesses the data to be written to the memory 350, buffers it in the first buffer 325 (step S36), and informs the DMA state machine 323 of this.

Accordingly, the DMA state machine 323 notifies the memory controller controller 324 that the first buffer 325 is buffered with data to be written to the memory 350.

Then, the memory controller controller 324 checks whether data can be input to the memory 350 to which data is to be written (step S37). That is, the memory controller controller 324 checks whether the memory 350 to which the corresponding data is to be written is in progress of data input / output by the previous command.

In this case, when data input is possible to the memory 350, that is, when data input / output by a previous command is not in progress, the memory controller controller 324 reads the data buffered in the first buffer 325. Write to memory 350 (step S38).

Here, the memory controller controller 324 continuously checks whether a data write error occurs while writing data to the memory 350 (step S39).

In this case, when an error is not confirmed while writing data to the memory 350, after confirming whether data writing to the memory 350 is completed (step S40), when it is completed, the memory controller controller 324 The host device 310 outputs that the data writing is normally completed and notifies the host. After notifying all modules involved in the data writing that the data writing is completed, the system bus 200 is released. (Step S41), it returns to the initial stage 31st step S31.

On the other hand, when an error is confirmed while writing data to the memory 350, the memory controller controller 324 analyzes the type of the identified error and outputs the result through the host interface 310 to host the same. After notifying to all modules involved in the data writing, the data writing is completed, the system bus 200 is released (step S41), and the initial step 31 (S31) is returned.

If the command corresponds to reading data between the host and the memory 350, the host interface controller 321 writes information about the command into the DMA status register 322, and the DMA state machine. 323 is driven.

Accordingly, the DMA state machine 323 occupies the system bus 200 with the host interface controller 321 to access the system main memory 100 according to the information recorded in the DMA state register 322. After making a request (step S42), the result is awaited. That is, the DMA state machine 323 waits for the system bus 200 occupation response from the host interface controller 321.

In this case, the DMA state machine 323 waits for receiving the occupancy response of the system bus 200 from the host interface controller 321, and the data amount and block of data to be written to the memory 350. The size is calculated and a data communication connection is prepared between the host and the memory 350 for data writing. That is, communication between the host interface controller 321 and the memory controller controller 324 is connected.

Accordingly, the host interface controller 321 checks whether the system bus 200 can be occupied at the request of the DMA state machine 323 (step S43). That is, it is checked whether the system bus 200 is in use by another system.

In this case, when the occupation of the system bus 200 is possible, the host interface controller 321 occupies the system bus 200, and the system main memory device 100 is occupied by the occupied system bus 200. (Step S44), the DMA state machine 323 is notified about this.

Accordingly, the DMA state machine 323 requests the memory controller controller 324 to read data from the memory 350.

Thus, the memory controller controller 324 checks whether data can be output from the memory 350 to read data (step S45). That is, the memory controller controller 324 checks whether the memory 350 to read the corresponding data is in progress of data input / output by the previous command.

In this case, when data output is possible to the memory 350, that is, when data input / output by a previous command is not in progress, the memory controller controller 324 obtains data to be read from the memory 350 and the second data is read. After buffering the buffer 326 (step S46), the DMA state machine 323 is informed about this.

Accordingly, the DMA state machine 323 notifies the host interface controller 321 that the second buffer 326 is buffered with data to be read from the memory 350.

Then, the host interface controller 321 writes the data buffered in the second buffer 326 to the system main memory device 100 through the occupied system bus 200 (step S47).

Here, the host interface controller 321 continuously checks whether a data read error occurs while reading data from the memory 350. That is, continuously checking whether or not a data read error occurs while writing data read from the memory 350 to the system main memory device 100 (step S48).

At this time, when the error is not confirmed during the data reading from the memory 350, after confirming that the data reading is completed in the memory 350 (step S49), if completed, the host interface controller 321 Through the host interface 310 to output that the data read is normally terminated to notify the host, and after notifying all modules involved in the data read that the data read is completed, release the occupancy of the system bus 200 (Step S50), it returns to the initial stage 31st step S31.

On the other hand, when an error is confirmed while reading data into the memory 350, the host interface controller 321 analyzes the identified error type and outputs the result through the host interface 310 to the host. After notifying, and notifying all modules involved in reading the data that the data reading is completed, the system bus 200 is released (step S50), and the process returns to the initial step 31 (S31).

On the other hand, when the command relates to data backup / restore between the memory 350 and the backup storage device 360, the host interface controller 321 determines that the command is stored in the memory 350 and the backup storage device ( 360, it is checked whether or not it is related to data backup or restoration (step S51).

As a result, when the command corresponds to data backup between the memory 350 and the backup storage device 360, the host interface controller 321 sends information about the command to the DMA status register 322. Write and drive the DMA state machine 323.

Accordingly, the DMA state machine 323 requests the backup storage controller controller 327 to confirm whether data can be input to the backup storage device 360 according to the information recorded in the DMA status register 322. .

Accordingly, the backup storage controller controller 327 checks whether data can be input to the backup storage device 360 in response to a request of the DMA state machine 323 (step S52). That is, the backup storage controller controller 327 checks whether the backup storage device 360 to back up the corresponding data is performing data input / output by the previous command.

In this case, when data input is possible to the backup storage device 360, that is, when data input / output is not in progress by a previous command, the backup storage controller controller 327 backs up data to the backup storage device 360. Notify the DMA state machine 323 that this is possible.

Accordingly, the DMA state machine 323 requests the memory controller controller 324 to back up data in the memory 350 (step S53).

Accordingly, the memory controller controller 324 checks whether data can be output from the memory 350 to back up the data (step S54). That is, the memory controller controller 324 checks whether the memory 350 to back up the corresponding data is in progress of data input / output by the previous command.

In this case, when data output is possible to the memory 350, that is, when data input / output by a previous command is not in progress, the memory controller controller 324 obtains data to be backed up from the memory 350 and stores the data to be backed up. After buffering the three buffers 328 (step S55), the DMA state machine 323 is notified about this.

Accordingly, the DMA state machine 323 notifies the backup storage controller controller 327 that the data to be backed up from the memory 350 is buffered in the third buffer 328.

Then, the backup storage controller controller 327 backs up the data buffered in the third buffer 328 to the backup storage device 360 (step S56).

Here, the backup storage controller controller 327 continuously checks whether a data backup error occurs while backing up data to the backup storage device 360 (step S57).

In this case, when an error is not confirmed while the data is backed up to the backup storage device 360, after confirming that the data backup is completed in the backup storage device 360 (step S58), the backup data storage device is completed. The storage controller controller 327 outputs that the data backup is normally completed through the host interface 310 to notify the host, and notifies all modules involved in the data backup that the data backup is completed. Return to step 31 (S31).

On the other hand, when an error is identified while backing up data to the backup storage device 360, the backup storage controller controller 327 analyzes the type of the identified error and displays the result of the host interface 310. After notifying the host by outputting through) and notifying all modules involved in the corresponding data backup that the data backup is completed, the process returns to the initial step 31 (S31).

If the command corresponds to data restoration between the memory 350 and the backup storage device 360, the host interface controller 321 writes information about the command into the DMA status register 322. The DMA state machine 323 is driven.

Thus, the DMA state machine 323 is capable of outputting data from the backup storage device 360 to restore data to the backup storage controller controller 327 according to the information recorded in the DMA status register 322. Ask for confirmation.

Accordingly, the backup storage controller controller 327 checks whether or not data can be output from the backup storage 360 according to the request of the DMA state machine 323 (step S59). That is, the memory controller controller 324 checks whether the backup storage device 360 for restoring the corresponding data is performing data input / output by the previous command.

In this case, when data output is possible from the backup storage device 360, that is, when data input / output is not in progress by a previous command, the backup storage controller controller 327 restores data from the backup storage device 360. Notify the DMA state machine 323 that this is possible.

Accordingly, the DMA state machine 323 requests the memory controller control unit 324 to restore data to the memory 350 (step S60).

Then, the memory controller controller 324 checks whether data can be input to the memory 350 to restore the data (step S61). That is, the memory controller controller 324 checks whether the memory 350 to restore the corresponding data is performing data input / output by the previous command.

In this case, when data input is possible to the memory 350, that is, when data input / output by a previous command is not in progress, the memory controller controller 324 indicates that data can be restored to the memory 350. Notify machine 323.

Accordingly, the DMA state machine 323 makes a request for outputting data in the backup storage controller 360 to the backup storage controller controller 327.

Accordingly, the backup storage controller 340 obtains data to be restored from the backup storage 360 and buffers the data in the fourth buffer 329 (step S62), and then the DMA state machine 323. Notify

Thus, the DMA state machine 323 notifies the memory controller controller 324 that the data to be restored from the backup storage device 360 is buffered in the fourth buffer 329.

Then, the memory controller controller 324 restores the data buffered in the fourth buffer 329 to the memory 350 (step S63).

In this case, the memory controller controller 324 continuously checks whether a data restoration error occurs while restoring data to the memory 350 (step S64).

In this case, when an error is not confirmed while restoring data to the memory 350, after confirming that the data restoration is completed in the memory 350 (step S65), when it is completed, the memory controller control unit 324 ) Outputs through the host interface 310 that the data restoration has been completed normally and notifies the host, and notifies all modules involved in the data restoration that data restoration has been completed, and then proceeds to step 31 of the initial stage. Go back.

On the other hand, when an error is confirmed while restoring data to the memory 350, the memory controller controller 324 analyzes the identified type of error and outputs the result through the host interface 310. After notifying the host and notifying all modules involved in the data restoration that data restoration is completed, the process returns to the initial stage 31 (S31).

On the other hand, if there is an error in the power supply from the external power supply unit, the power control unit 370 notifies the DMA control device 320, and receives the power from the auxiliary power supply unit 380 it is the host interface And supply to the 310, the DMA control device 320, the memory controller 330, and the backup storage controller 340.

Specifically, the power control unit 370 checks whether the power supplied from the external power supply unit is abnormal and notifies the host interface control unit 321 of the DMA control apparatus 320 when an abnormal state is detected.

Then, the host interface controller 321 interrupts communication with the host interface 320 according to the notification of power supply abnormality detection from the power controller 370, generates a self backup command, and generates information on the command. The DMA state register 322 is written to drive the DMA state machine 323.

Accordingly, the DMA state machine 323 requests the backup storage controller controller 327 to confirm whether data can be input to the backup storage device 360 according to the information recorded in the DMA status register 322. .

Accordingly, the backup storage controller controller 327 checks whether data can be input to the backup storage device 360 according to the request of the DMA state machine 323.

That is, when power supply from the external power supply is interrupted or an abnormality in supply power occurs, the power control unit 370 supplies power from the auxiliary power supply 380 to protect data stored in the memory 350. This is supplied to the host interface 310, the DMA control device 320, the memory controller 330 and the backup storage controller 340, respectively.

Thereafter, the data backup step from the 52nd step S52 to the 56th step S56 is performed by itself.

Here, when the supply of power from the external power supply unit is not interrupted or the supply power does not occur, the power supply control unit 370 cuts off the supply power from the auxiliary power supply unit 380. It is to be understood that when the power supply is interrupted or an abnormality of the power supply is detected, the power supply from the auxiliary power supply 380 is released by canceling the supply power cutoff from the auxiliary power supply 380.

The auxiliary power source 380 is made of a rechargeable battery, and normally charges itself to maintain a constant voltage by using the power of the external power source. For example, the auxiliary power supply unit 380 maintains the voltage of the charging power supply at 12V.

Alternatively, the backup storage controller controller 327 generates a backup command by itself at predetermined time intervals and records the backup command in the DMA status register.

As a result, by backing up data stored in the memory in the auxiliary storage device without controlling the command from the system central processing unit (not shown), it is possible to secure the stability of the data stored in the memory and to reduce the load on the system central processing unit. Can be reduced.

According to the present invention as described above, the data transfer speed of the direct memory access (DMA) control device at the interface with the host is improved, and the storage medium is mechanically (e.g., HDD and FDD) to a semiconductor (memory). ) To increase the data storage speed.

In addition, by backing up data stored in the memory in the auxiliary storage device by itself, the auxiliary storage device may reduce the load of the central processing unit when performing other functions, and improve the data backup speed, thereby improving reliability in data storage.

Claims (28)

A semiconductor auxiliary memory device having a memory and a backup storage device, which are connected to a system bus to which an external power supply unit for supplying power and a system main storage device for storing data, are connected. A host interface connected to the system bus and receiving a command from a host; A memory controller for inputting and outputting data into the memory; A backup storage controller for inputting / outputting data into the backup storage device; The memory controller and the backup storage controller are controlled to read or write data between the memory and the system main storage device according to a command from the host through the host interface unit, and data is written between the backup storage device and the memory. A DMA control device for backing up and restoring; And a power control section for supplying power from the external power supply section to the host interface section, the memory controller, the backup storage controller, and the DMA control apparatus. The method of claim 1, The auxiliary power supply unit may further include an auxiliary power supply unit which checks whether there is an abnormality of the supply power supply from the external power supply unit and supplies the power control unit with power to be supplied to the host interface, the DMA control unit, the memory controller, and the backup storage controller when the supply power supply is detected. Semiconductor auxiliary memory, characterized in that The method of claim 2, And the power supply control unit notifies the DMA control device of the detection of abnormal supply power from the external power supply unit. The method of claim 3, The DMA control apparatus may block a command from a host according to the notification of the power control unit, and control the memory controller and the backup storage controller to back up data stored in the memory to the backup storage device. Auxiliary memory. The method of claim 1, And the DMA controller controls the memory controller and the backup storage controller to back up the data stored in the memory to the backup storage device at predetermined time intervals. The method of claim 1, The DMA control apparatus may include: a host interface controller configured to analyze a command from a host and input data buffered and output from the memory into a system main memory, or obtain data from a system main memory and buffer the data; A backup storage controller controller configured to input data buffered from the memory to the backup storage device or output data from the backup storage device and buffer the data; A memory controller controller configured to input data buffered by the backup storage controller controller and the host interface controller to the memory, or output data from the memory and buffer the data; A DMA status register for recording information on commands from the host interface controller; A DMA state machine for performing a data transfer command between the host interface controller and the memory controller controller and between the memory controller controller and the backup storage controller controller in accordance with information about a command recorded in the DMA status register; And a buffer unit configured to buffer data transmitted between the host interface controller and the memory controller controller and between the memory controller controller and the backup storage controller controller. The method of claim 6, And the host interface controller analyzes whether a command from a host relates to data write / read or data backup / restore. delete The method of claim 6, And the host interface controller interrupts communication with the host interface unit when detecting a power supply abnormality, generates a backup command by itself, and writes it to the DMA status register. The method of claim 6, And the backup storage controller controller generates a data backup command at predetermined time intervals and writes the data backup command to the DMA status register. The method of claim 10, And the backup storage controller controller is a microprocessor. The method of claim 6, The buffer unit may include: a first buffer configured to buffer data transmitted from the host interface controller to the memory controller controller; A second buffer buffering data transmitted from the memory controller controller to the host interface controller; A third buffer buffering data transmitted from the memory controller controller to the backup storage controller controller; And a fourth buffer for buffering data transmitted from the backup storage controller controller to the memory controller controller. The method of claim 1, The memory comprises a dual data rate (DDR) SDRAM, DDR2 SDRAM, Quad Data Rate (QDR) SDRAM, SRAM, FRAM, PRAM, and Flash Memory. The method of claim 1, And said backup storage device is comprised of HDD, FDD, MMC, SD and PCMCI. A data storage method using a semiconductor auxiliary memory device having a memory and a backup storage device connected to a system bus to which an external power supply unit for supplying power and a system main storage device for storing data are connected. , A first step of checking whether there is a power failure from the external power supply unit and analyzing a command from the host when there is no error; A second process of writing data to or reading data from the memory according to the analyzed command; And backing up the data recorded in the memory to the backup storage device or restoring the data backed up to the backup storage device to the memory according to the analyzed command. How to save data using the device. The method of claim 15, The first step is to analyze whether the command from the host relates to data write / read or data backup / restore. The method of claim 15, The second process includes: making a request to occupy the system bus if the analyzed command is a data write; Checking the availability and buffering the data to occupy the system bus and write to memory if available; Checking whether data can be input to the memory, and writing the buffered data to the memory if possible; Checking whether an error occurs while writing to the memory, and if the error does not occur, checking whether data writing is completed; And when the writing of the data is completed, releasing the occupancy of the system bus. The method of claim 17, The step of checking whether the data writing is completed may include: notifying the host by outputting that the data writing is normally completed when the error does not occur; And notifying all modules involved in the data writing that the data writing is completed. The method of claim 18, Analyzing the type of the error and outputting the result to the host when the error occurs; And notifying all modules involved in the data writing that the data writing is completed. The method of claim 15, The second process includes: making a request for occupying the system bus when the analyzed command is reading data; Checking the availability and occupying the system bus if available and connecting to a system main memory; Confirming whether data output is possible from the memory, and if possible, fetching and buffering data from the memory; Reading the buffered data in a system main storage device; Checking whether an error has occurred while the system main memory device reads data, and if the error has not occurred, checking whether data reading is completed; And when the reading of the data is completed, releasing the occupancy of the system bus. The method of claim 20, The step of checking whether the data reading is completed may include: notifying the host by outputting that the data reading is normally completed when the error does not occur; And notifying all modules involved in the data reading that the data reading is completed. The method of claim 21, Analyzing the type of the error and outputting the result to the host when the error occurs; And notifying all modules involved in the data reading that the data reading has been completed. The method of claim 15, The third step may include: when the analyzed command is a data backup, checking whether data can be input to the backup storage device, and requesting data backup in the memory if possible; Checking whether data can be output from the memory according to a data backup request in the memory, and if possible, obtaining and buffering data to be backed up from the memory; Backing up the buffered data to a backup storage device; Checking whether or not an error has occurred during data backup to the backup storage device, and if the error does not occur, outputting through the host interface to notify the host that the data backup is normally completed; And notifying all modules involved in the data backup that the data backup has been completed. The method of claim 23, wherein The step of outputting through the host interface and notifying the host may include analyzing the type of the generated error and outputting the result to the host when the error occurs; And notifying all modules involved in the data backup that the data backup is completed. The method of claim 15, The third step may include: when the analyzed command is data restoration, checking whether data output from the backup storage device is possible, and requesting data restoration in the memory if possible; Checking whether data can be input to the memory according to a data restoration request to the memory, and if possible, obtaining and buffering data to be restored from the backup storage device; Restoring the buffered data to the memory; Checking whether an error has occurred while restoring data to the memory, and if the error has not occurred, outputting to the host via a host interface that data restoration has been normally terminated; And notifying all modules involved in the data restoration that data restoration has been completed. The method of claim 25, The step of outputting through the host interface and notifying the host may include analyzing the type of the error and outputting the result to the host when the error occurs; And notifying all modules involved in the data restoration that data restoration has been completed. The method of claim 15, Interrupting a command from the host when an abnormality in power supplied to the semiconductor auxiliary memory device occurs; After blocking a command from the host, driving by using an auxiliary power source, checking whether data can be input to a backup storage device, and requesting data backup in a memory if possible; Checking whether data can be output from the memory according to a data backup request in the memory, and if possible, obtaining and buffering data to be backed up from the memory; And backing up the buffered data to the backup storage device. The method of claim 15, And backing up the data stored in the memory to the backup storage device at regular time intervals regardless of the command from the host.

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