KR100825956B1 - Reference voltage generator - Google Patents

Abstract

A reference voltage generator is provided to improve pumping efficiency by decreasing power consumption, and to reduce complexity of a circuit diagram. A reference voltage generator includes a first current generator(120), a second current generator(130), and a combining unit(140). The first current generator generates a temperature-compensated first current. The second current generator generates a second current which is proportional to a second order function representing a temperature variation. The combing unit receives the first and second currents and generates a reference voltage. A driver(110) controls the first and second current generators. The driver includes first and second NMOS(Negative Metal Oxide Semiconductor) transistors and a capacitor. The capacitor couples gates of the NMOS transistors with a source voltage. A divided voltage is delivered to the gates of the NMOS transistors. The divided voltage is generated by a voltage divider which includes a parasitic capacitor and a capacitor.

Description

Reference voltage generator

1 is a diagram illustrating a configuration of a reference voltage generator according to an embodiment of the present invention.

2 is an integrated part of a reference voltage generator according to an embodiment of the present invention.

3 is a circuit diagram showing the configuration of a reference voltage generator first current generator according to an embodiment of the present invention.

4 is a circuit diagram illustrating a configuration of a second current generator 130 of a reference voltage generator according to an embodiment of the present invention.

5 is an overall circuit diagram of a reference voltage generator according to an embodiment of the present invention.

Figure 6 is a graph showing the output voltage characteristics different from the temperature change of the reference voltage generator according to an embodiment of the present invention.

The present invention relates to a reference voltage generator, and more particularly to a reference voltage generator independent of temperature changes at low voltage.

In general, a bandgap reference circuit is a circuit that provides a reference voltage using a power source applied from the outside. At this time, the reference voltage providing circuit must be independent of the power supply or processor parameters or the temperature change. That is, the reference voltage providing circuit must provide a constant reference voltage despite a change in the power supply, the process parameters, or the temperature supplied.

Looking at the existing reference voltage generator, (1) Piecewise-linear compensation implements the nonlinearity of temperature by adding more nonlinear current above the reference temperature by using the characteristics of metal oxide semiconductor (MOS). However, there is a problem in that it cannot be implemented at a low supply voltage using a complementary metal-oxide-semiconductor (CMOS) process.

(2) Register temperature compensation is the easiest approach, but it is very reliable because on-chip resistors with different temperature coefficients must be guaranteed in the process and the compensation method is very dependent on the process method. There is a problem.

(3) Quadratic temperature compensation can be implemented by adding a function proportional to the secondary function to offset only the second order function among the higher order functions, but there is a problem in that the circuit diagram becomes complicated and the power consumption increases a lot.

(4) Exponential temperature compensation uses the characteristics of the forward-current gain temperature of bipolar transistors and is relatively simple. However, it is sensitive to temperature in CMOS, which causes problems in device reliability.

(5) Different temperature dependent current is implemented through the current mirror and closed loop by using the property that the currents have different functions in temperature, but it is complicated to implement in circuit. There is this.

(6) Exact method can eliminate the components of T * ln (T) by using process parameters that are well defined by experiments, but there is a problem that the device does not operate at low supply voltage.

In order to solve the conventional problems as described above, the present invention proposes a reference voltage generator that is independent of temperature change.

In addition, the present invention proposes a reference voltage generator capable of operating at a low supply voltage and having a low complexity of the circuit diagram.

In addition, the present invention proposes a reference voltage generator that increases the pumping efficiency by reducing power consumption.

Still other objects of the present invention will be readily understood through the following description of the embodiments.

In order to achieve the above object, according to an aspect of the present invention, in the reference voltage generator independent of the temperature change, the first current generating unit for generating a first compensation first current corresponding to the temperature change; A second current generator for generating a second current corresponding to the quadratic function of the temperature change; And an integrated unit configured to receive the first and second currents to generate a reference voltage.

The apparatus may further include a driver configured to control whether the first and second current generators are operated.

The driving unit includes first and second N-channel metal oxide semiconductors (NMOS) and a capacitor connected to a gate, and the capacitor connects the gates of the first and second NMOSs with a power supply voltage Vdd. A predetermined voltage value may be transferred to the gates of the first and second NMOSs by using a parasitic capacitor generated by the gate and a voltage divider formed by the capacitor.

When the predetermined voltage value exceeds the threshold voltage values of the first and second NMOSs, the first and second current generators connected to drains of the first and second NMOSs may be operated.

The driving unit may further include third, fourth and fifth NMOSs coupled in a mirror form, wherein the third to fifth NMOS gates are connected to each other, and the drains of the fifth NMOS are connected to the first and second NMOSs. Gates of the third and fourth NMOSs connected to the gates of the NMOS and coupled in the mirror form may receive a predetermined voltage from any one of a plurality of MOS devices connected in the form of mirrors of the first current generator. have.

When the first current generator is operated and a predetermined voltage value transmitted to the gates of the fifth NMOS through the gates of the third and fourth NMOSs exceeds the threshold voltage value of the fifth NMOS, the fifth NMOS is configured to perform the above-mentioned operation. The gate voltage levels of the first and second NMOSs may be reduced.

The first current generator may include a plurality of P-channel metal oxide semiconductors (PMOS) connected with gates; An amplifier connected to the gate and the output terminal; First to fifth resistors R1, R2, R3, R4, and R5; A first and second diodes Q1 and Q2, wherein the connection point between the first resistor R1 and the second resistor R2 is connected in series between the drain of the first PMOS and the substrate voltage Vss. A second input of the amplifier to a connection point between the third resistor R3 and the fourth resistor R4 connected in series between the first input terminal of the amplifier and the drain of the second PMOS and the substrate voltage Vss A terminal is connected, and a connection point between the first resistor R1 and the first PMOS pd1 is connected to an emitter of the first transistor Q1, and the third resistor R3 and the third resistor are connected to each other. The connection point between two PMOS pd2 may be connected to the emitter of the second transistor Q2 through the fifth resistor R5.

The second current generator includes a plurality of P-channel metal oxide semiconductors (NMOS); And a plurality of P-channel metal oxide semiconductors (PMOSs) having gates connected and a source connected to a power supply voltage Vdd, wherein drains of the first and second PMOSs are connected to the gates of the first and second NMOSs. Respectively connected to the drains of the first and third PMOSs, respectively, to drains of the third and fourth NMOS gates connected to the drains thereof, and the gates of the first PMOS, the first NMOS and the third NMOS, respectively. It is connected to the drain and can generate a second current at the drain of the fourth PMOS, corresponding to the secondary function of temperature change.

The first, second and fourth PMOS operate in a strong inversion, the first and second NMOS operate in a weak inversion, and the fourth NMOS operates in a linear operating region ( linear).

The integrated unit extracts and integrates the first and second currents respectively generated by the first and second current generators through a current mirror to pass a predetermined resistance to supply a reference voltage to an external circuit. Can be.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and shall not be construed in ideal or excessively formal meanings unless expressly defined herein. Do not.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, the same reference numerals will be used for the same means regardless of the reference numerals in order to facilitate the overall understanding.

1 is a diagram illustrating a configuration of a reference voltage generator according to an embodiment of the present invention.

Referring to FIG. 1, a reference voltage generator according to an embodiment of the present invention includes a first current generator 120, a second current generator 130, a driver 110, and an integrated unit 140.

The first current generator 120 generates and outputs a first current that is first compensated according to a temperature change, and the second current generator 130 generates a second function of temperature change (for example, T ² ). In response to the second current is generated and output.

The driving unit 110 starts up the first current generating unit 120 and the second current generating unit 130, and the integrating unit 140 generates the first current generating unit 120 and the second current. The first and second currents generated by the unit 130 are integrated to generate a reference voltage.

Each component included in the reference voltage generator according to an embodiment of the present invention will be described later with reference to the accompanying drawings.

2 is an integrated unit 140 of a reference voltage generator according to an embodiment of the present invention.

Referring to FIG. 2, the integrating unit 140 of the reference voltage device according to an embodiment of the present invention mirrors the first and second currents generated by the first and second current generating units 120 and 130, respectively. After extracting each using the (current mirror), the A node 210 is integrated and passed through a predetermined resistor Rout 220 to supply a reference voltage to an external circuit.

Here, since a technology for a current mirror is already known, a detailed description thereof will be omitted herein except for a part related to the gist of the present invention.

In addition, the generation of the first and second currents 205 and 206 in the first and second current generators 120 and 130, respectively, will be described in detail later with reference to FIGS. 3 and 4. A process of integrating the first and second currents 205 and 206 in the unit 140 will be described.

In FIG. 2, the first and second current generators 120 and 130 are briefly represented to first compensate for the change in temperature through the first and fourth P-channel metal oxide semiconductors (PMOS) 201 and 204. It is shown that the first current I1 205 and the second current I2 206 respectively flow in proportion to the quadratic function of the temperature change.

Here, the same current as the first current I1 205 is generated in the second PMOS 202 coupled to the first PMOS 201 in the form of a current mirror, and flows to the A node 210.

Similarly, the same current as the second current I2 206 is generated in the third PMOS 203 coupled to the fourth PMOS 204 in the form of a current mirror and flows to the A node 210.

Therefore, in node A 210, the first and second currents 205 and 206 are integrated and output to the external circuit as a reference voltage by the predetermined resistor Rout 220.

Here, the first current 205 is a primary convex current with respect to the temperature change, and a large convex curve (for example, the voltage when the first current passes through a predetermined resistance is 230 in FIG. 2). And the second current 206 is a current proportional to the second function of the temperature change, and a small concave curve (for example, when the second current passes through a predetermined resistance, the voltage is shown in FIG. 2). The first and second currents 205 and 206 are complementary to each other (described in detail below with reference to FIGS. 3 and 4) as a form.

Therefore, when the complementary first current 205 and the second current 206 are integrated at the A node 210, mutual cancellation effects may occur to generate a reference current independent of temperature change, and Using the set Rout 220, a reference voltage 250 independent of temperature change may be generated and provided to an external circuit.

Here, in FIG. 2, a current mirror is made using PMOS in accordance with an embodiment of the present invention, but N-channel metal oxide semiconductor (NMOS), complementary metal oxide semiconductor (CMOS), and bipolar junction transistors are used. It will be apparent to those skilled in the art that it can be configured as).

In the above, the integrated unit 140 integrates the first and second currents 205 and 206 to output a reference voltage to an external circuit.

Hereinafter, the first and second current generators 120 and 130 will be described.

3 is a circuit diagram illustrating a configuration of a first current generator 120 of a reference voltage generator according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the first current generator 120 according to an embodiment of the present invention may include a plurality of PMOSs (pd1 and pd2), a plurality of PNP type Bipolar Junction Transistors (BJTs) 350 and 351, and a plurality of resistors. 331, 332, 333, 334 and an operational amplifier 320.

However, the sum of R1_1 331 and R1_2 332 is equal to the sum of R2_1 333 and R2_2 334, and the area of the emitter of the second BJT 351 is the area of the emitter of the first BJT 350. N times larger than area.

Hereinafter, the proportional component (Proportional to absolute temperature, hereinafter referred to as 'PTAT') and the inverse proportional component (Completmentary to absolute temperature, hereinafter referred to as 'CTAT') in the first current generator according to the embodiment of the present invention. The process of generating the first compensated current in response to the temperature change will be described.

More specifically, the PTAT component current flowing from the current flowing through the second PMOS 312 toward the R0 335 at the node E 344 is described, and then the CTAT current component flowing toward the resistor R2_1 333 has the same magnitude. The current flowing in the direction of the R1_1 (331) at the node D 343 will be described.

First, the PTAT component will be described using a current component flowing in the direction of R0 335 at the node E 335.

The operational amplifier 320 serves to equalize the voltages of the node B 350 and the node C 351. At this time, the resistor R0 335 is inserted between the emitters of the second BJT 351 at the node E 344, and thus the emitter of the Veb2 (the second BJT 351) of the second BJT 351 is inserted. The voltage difference between the emitter and the base is smaller than Vbe1 (the voltage difference between the emitter and the base of the first BJT 350). Therefore, the current flowing through R0 335 may be represented by Equation 1 below.

Here, the Veb of the BJT may be represented by the following Equation 2 using the current formula of the BJT.

Where Is is saturation current and Vt = kT / q (k is Boltzmann's constant, q is electric charge).

Using Equations 1 and 2 can be represented by Equation 3 below.

Here, since the area of the emitter of the second BJT 351 is n times larger than the area of the emitter of the first BJT 350, Is2 is n times larger than Is1. Therefore, summarizing Equation 3, the current flowing through R0 335 may be represented by Equation 4 below.

Referring to Equation 4, the current flowing through the resistor R0 335 becomes a linear function that is a PTAT component proportional to the temperature T.

Next, the CTAT component which is a component inversely proportional to temperature is demonstrated.

The current flowing in the direction of R2_1 333 at node E 344 is equal to the current flowing in the direction of resistor R1_1 331 at node D 343.

Here, the sum of the resistors R1_1 331 and R1_2 332 is represented by the resistor R1, and the sum of the R2_1 (333) and R2_2 (334) is represented by the resistor R2. The current flowing through the resistor R1 or the resistor R2 is expressed by Equation 5 below. Can be represented.

In general, as the temperature increases by 1 ° C, the Veb decreases by approximately 2mV. Therefore, referring to Equation 5, the current flowing through the resistor R1 or R2 is a CTAT component that is primarily inversely proportional to temperature.

The current flowing in the second PMOS 312 of FIG. 3 may be divided into a PTAT component flowing in the R0 335 direction at the node E 344 and a CTAT component flowing in the R2_1 333 direction. Also, the current flowing through the third PMOS 313 is equal to the current flowing through the second PMOS 312 by the current mirror. Therefore, referring to Equations 4 and 5, the current I1 205 generated by the first current generator 120 may be represented by Equation 6 below.

Here, i _PTAT is a current value of the PTAT component, i _CTAT is a current value of the CTAT component.
Referring to Equation 6, the current I1 205 generated by the first current generator 120 is a sum of PTAT components that are first proportional to temperature and components that are first inversely proportional to each other. Generate a current. In addition, I1 205 has a large convex shape at the top, which is the same as the first graph 230 at the bottom of FIG.

So far, the generation of the current I1 205 which is primarily compensated for the temperature change generated by the first current generator 120 has been described. Hereinafter, the second current generator 130 is used as a second function of the temperature change. Correspondingly, a process of generating the second current 206 will be described.

4 is a circuit diagram illustrating a configuration of the second current generator 130 of the reference voltage generator according to an embodiment of the present invention.

Referring to FIG. 4, the second current generator 130 of the reference voltage generator according to an embodiment of the present invention may include a plurality of PMOSs 410, 411, 412, and 413 connected to gates, and a plurality of NMOSs coupled in a mirror form. 421, 422, 423, 424.

Here, although the second current generator 130 of the reference voltage generator according to the exemplary embodiment of the present invention shown in FIG. 4 is configured using only MOS (Metal Oxide Semiconductor) devices, NMOS, PMOS, BJT, etc. may be used. It is apparent to those skilled in the art that the configuration can be made.

In general, the MOS device can be used in the following three operating regions depending on conditions.

1) steel inversion zone; Vgs> Vth, Vds> Vgs-Vth

2) weakly inverted region; Vgs <Vth

3) linear operating range; Vgs> Vth, Vds <Vgs-Vth

(Vgs is the gate-source voltage, Vds is the drain-source voltage, and Vth is the threshold voltage.)

The MOS device has a characteristic of an ideal current source in a circuit in a strong inversion region, and this state is called a turn-on state. In the weakly inverted region, a turn-off state in which no current flows, but in reality, a slight current flows, and the MOS device is similar to that of the BJT. In the linear operating region, the MOS device acts as a resistor.

Referring to FIG. 4, the first, second, and fourth PMOSs 410, 412, and 413 operate in a strong inversion region because they must serve as ideal current sources to serve as current mirrors. The first and second NMOSs 421 and 422 operate in a weakly inverted region in order to have the property of BJT. The third and fourth NMOSs 423 and 424 operate in a linear operating region to act as a resistor.

Referring to FIG. 4, the current I 2 output to the external circuit through the fourth PMOS 413 may be summarized by Equation 7 below.

는 선형 동작영역에서의 제3 및 제4 NMOS(423, 424)가 회로에서 구성하는 저항이며,

는 노드 F(450)에서의 전압이며,

및

는 제1 및 제2 NMOS(421, 422)의 게이트(gate)와 소스(source)간의 전압이다.here

Is the resistance that the third and fourth NMOSs 423 and 424 constitute in the circuit in the linear operating region,

Is the voltage at node F 450,

And

Is the voltage between the gate and the source of the first and second NMOSs 421 and 422.

와

를 하기의 수학식 8과 같이 나타낼 경우 상기 수학식 7은 하기의 수학식 9로서 나타낼 수 있다. here,

Wow

When Equation 8 is expressed as Equation 8 below, Equation 7 may be represented as Equation 9 below.

Here, W / L means the ratio of the width (W) and the length (L) of the MOS, and in other terms, also referred to as WL ratio. W / L is an important factor in obtaining the current of the MOS, and is represented by β in the equation.
Here, x is a natural number and is a variable for distinguishing each W / L of each MOS.
For example, the WL ratios of the n3 Morse 423 and the n4 Morse 424 may be represented as β ₃ = (W / L) ₃ and β ₄ = (W / L) ₄ , respectively.
Referring to Equation 9, I 2 output to the external circuit through the fourth PMOS 413 is proportional to the second function of the temperature change, and is first compensated for by the temperature change generated by the first current generator 120. It becomes a concave graph 240, which is complementary to I1 of the convex curve 230.

The current I2 proportional to the secondary function of the temperature change generated by the second current generator 130 has been described.

Hereinafter, the entire circuits of the driver 110 and the reference voltage generator for driving the first current generator 120 and the second current generator 130 will be described.

5 is an overall circuit diagram of a reference voltage generator according to an embodiment of the present invention.

Referring to FIG. 5, a reference voltage generator according to an embodiment of the present invention may include a first current generator 120 (see FIG. 3), a second current generator 130 (see FIG. 4), an integrated unit 140, and a driving unit. It may include the unit 110.

The driving unit 110 of the reference voltage generator according to an embodiment of the present invention requires two start-up circuits for driving the first and second current generators 120 and 130, respectively, for structural reasons. Do.

Therefore, in order to overcome the disadvantage of complicated circuit design, according to an embodiment of the present invention, the driving unit 110 includes five NMOSs 501, 502, 503, 504, 505 and one capacitor Csu, 510. It can include a simple form of startup circuit.

In general, in the bootstrapping structure, in which the circuit itself is subjected to voltage biasing, there are two conditions under which the circuit can operate stably. One is an operating point that has a normal value and is stabilized, and the other is an operating point that operates by being saturated with a supply voltage.

In the reference voltage generator having a bootstrap structure, when the entire circuit does not operate normally, the voltages of the node vctrl 520 and the node np1 521 become close to the power supply voltage Vdd, and the voltage of the node nbias1 522 is the substrate. It approaches the voltage Vss. Therefore, in order for the reference voltage generator to have a normal value and operate in a stable manner, the voltages of the nodes vctrl 520, the nodes np1 521, and the nodes nbias1 522 must be made to a predetermined value. I need a circuit.

According to an embodiment of the present invention, as the capacitors Csu and 510 provided in the driver 110 and the parasitic capacitors Cpar and 511 generated in the node nsu 523, the node nsu 523 may be formed using characteristics such as a voltage divider. Increase the voltage level. The voltage of the node nsu 523 may be represented by Equation 10 below.

Parasitic capacitor (Cpar, 511) is the value of the change, but, in general, its value is to several tens femto (femto, 10 ^-15), so the capacitor (Csu, 510) the value is smaller the above-mentioned voltage divider according to the equation (10) Due to the characteristics, the value of the power supply voltage Vdd can be sufficiently transmitted to the node nsu 523.

Therefore, when the voltage of the node nsu 523 increases as the power supply voltage Vdd increases to exceed the threshold voltage values Vth of the first and second NMOSs 501 and 502, the first and second NMOSs 501. , 502 is operated, and finally a predetermined voltage value is transmitted to the node vctrl 520 and the node np1 521 for the circuit to operate normally.

Herein, operations of the first current generator 120, the second current generator 130, and the integrated unit 140 have been described above with reference to FIGS. 2 to 4, and thus descriptions thereof will be omitted.

When the first current generator 120, the second current generator 130, and the integrator 140 operate at a desired operating point, and the entire circuit starts to perform a desired operation, the voltage value of the node nbias1 522 increases. As a result, the threshold voltage values Vth of the third to fifth NMOSs 503, 504, and 505 are exceeded, and the third to fifth NMOSs 503 and 504 operate.

At this time, the fifth NMOS 505 operates to lower the gate voltages of the first and second NMOSs 501 and 502 to disconnect the first and second NMOSs 501 and 502 from the entire circuit. .

So far, the role of the driving unit in the entire circuit has been described with reference to FIG. 5.

6 is a graph illustrating output voltage characteristics that are different from temperature changes of a reference voltage generator according to an exemplary embodiment of the present invention.

Referring to FIG. 6, an output voltage characteristic graph 230 when the first current generator 120 first compensates for a temperature change generated by integrating a complementary PTAT component and a CTAT component, and FIG. According to an embodiment, a graph 600 illustrating characteristics of an output voltage when the second current generated by the second current generator 130 corresponding to the quadratic function of the temperature change is further superimposed on the first current described above. There is.

Here, it can be seen that the reference voltage generator according to the embodiment of the present invention can reduce the variation of the output voltage change according to the temperature change than the output voltage when the first compensation is made to the existing temperature change.

The above-described embodiments of the present invention are disclosed for the purpose of illustration, and those skilled in the art may make various modifications, changes, and additions within the spirit and scope of the present invention. Should be considered to be within the scope of the following claims.

As described above, the reference voltage generator according to the present invention has an advantage of providing a reference voltage independent of a change in temperature.

In addition, the present invention has the advantage of providing a reference voltage generator that can operate at a low supply voltage and has a low complexity of the circuit diagram.

In addition, the present invention has the advantage of providing a reference voltage generator to increase the pumping efficiency by reducing the power consumption.

Claims (10)

For a reference voltage generator that is independent of temperature changes, A first current generator for generating a first compensated first current according to the temperature change; A second current generator for generating a second current proportional to a quadratic function of the temperature change; And A reference voltage generator including an integrated unit configured to receive the first and second currents and generate a reference voltage. The method of claim 1, And a driving unit for controlling the operation of the first and second current generators. The method of claim 2, The driving unit A first and second N-channel metal oxide semiconductor (NMOS) and a capacitor connected to the gate, The capacitor connects the gate and power supply voltage Vdd of the first and second NMOS, And a division voltage value using a parasitic capacitor generated at the gate and a voltage divider formed by the capacitor is transferred to the gates of the first and second NMOSs. The method of claim 3, wherein When the divided voltage value exceeds the threshold voltage values of the first and second NMOS, the first and second current generators connected to the drains of the first and second NMOS, respectively, are operated. . The method of claim 4, wherein The driving unit Further comprising a third, fourth and fifth NMOS coupled in a mirror form, A gate of the third NMOS is connected with the fourth NMOS gate, the fourth NMOS gate is connected with the fifth NMOS gate, A drain of the fifth NMOS is connected to gates of the first and second NMOS, The gates of the third and fourth NMOSs coupled in a mirror form are supplied with a predetermined voltage from any one of a plurality of MOS devices connected in a mirror form of the first current generator. The method of claim 5, When the first current generator is operated and a predetermined voltage value transmitted to the gates of the fifth NMOS through the gates of the third and fourth NMOSs exceeds the threshold voltage value of the fifth NMOS, the fifth NMOS is configured to perform the above-mentioned operation. And reducing the gate voltage levels of the first and second NMOS. The method of claim 1, The first current generating unit A plurality of P-channel metal oxide semiconductors (PMOS) connected with gates; An amplifier connected to the gate and the output terminal; First to fifth resistors R1, R2, R3, R4, and R5; Including the first and second diodes (Q1, Q2), The first input terminal of the amplifier is connected to the connection point between the first resistor (R1) and the second resistor (R2) connected in series between the drain of the first PMOS and the substrate voltage (Vss), A second input terminal of the amplifier is connected to a connection point between the third resistor R3 and the fourth resistor R4 connected in series between the drain of the second PMOS and the substrate voltage Vss; A connection point between the first resistor R1 and the first PMOS pd1 is connected to an emitter of the first transistor Q1. The connection point between the third resistor (R3) and the second PMOS (pd2) is connected to the emitter of the second transistor (Q2) through the fifth resistor (R5). The method of claim 1, The second current generating unit A plurality of N-channel metal oxide semiconductors (NMOS); And It includes a plurality of P-channel metal oxide semiconductor (PMOS), the gate is connected and the source is connected to the power supply voltage (Vdd), The drains of the first and second PMOSs are connected to the drains of the first and second NMOSs, respectively, to which gates are connected. The drains of the first and third PMOSs are connected to the drains of the third and fourth NMOS gates, respectively. Gates of the first PMOS, the first NMOS, and the third NMOS are respectively connected to a drain; And generate the second current at the drain of a fourth PMOS. The method of claim 8, The first, second and fourth PMOS operate in strong inversion, The first and second NMOS operate in a weak inversion, And the fourth NMOS operates in a linear operating region. The method of claim 1, The integrated portion Extracting and integrating the first and second currents respectively generated by the first and second current generators through a current mirror to pass a predetermined resistance to supply a reference voltage to an external circuit. Reference voltage generator.

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