KR100821571B1 - Apparatus for Generating Input Data for Semiconductor Memory Apparatus - Google Patents

Abstract

The present invention relates to an input data generating device of a semiconductor memory device for easily generating various test patterns in a compression test mode of a semiconductor memory device and performing a compression test. The present invention relates to a test using external data received in a data compression test mode. Receiving at least one first input data driver for generating data and the test data generated from the first input data driver in place of the external data in the data compression test mode, the test as a pattern control signal being a column address signal; At least one second input data driver for controlling and outputting a logic level of the data. As a result, various test patterns for data compression test can be easily generated by using the column address signal.

Data Compression Modes, Test Patterns

Description

Input data generating device for semiconductor memory device {Apparatus for Generating Input Data for Semiconductor Memory Apparatus}

1 is a diagram for describing an input data generating device for a general semiconductor memory device;

2 is a schematic diagram of an input data generating device according to the present invention;

FIG. 3 is a detailed configuration diagram of the input data generating device shown in FIG. 2;

4 is a detailed configuration diagram of the input data driver shown in FIG. 3;

5 is a detailed circuit diagram of the input data multiplexer shown in FIG. 4;

6 is a detailed circuit diagram of the multiplexer shown in FIG. 5;

7 is a diagram illustrating an example of a test pattern output from the input data generating device according to the present invention.

<Description of the symbols for the main parts of the drawings>

110: address buffer 120: address latch unit

130: test signal generator 140: input data generator

1410: data input buffer 1420: latch portion

1430 input data multiplexer 1440 input data sense amplifier

200: comparison unit 210: multiplexer

2110: selector 2120: amplifier

The present invention relates to a semiconductor memory device, and more particularly, to an input data generating device of a semiconductor memory device for easily generating various test patterns in a compression test mode of a semiconductor memory device and performing a compression test.

In order to guarantee the reliability of the memory device due to the high integration of the memory device, it is necessary to perform the test for a long time with expensive test equipment, and to reduce the time and cost of the test by embedding the self test circuit inside the chip in advance in the design stage. I'm making it.

Among the self test methods, the DQ compression test is a method of storing the same data in a plurality of memory cells, outputting these data at the same time, checking the output data at the same time, and testing the presence or absence of errors in the memory device as a result. Using the DQ compression test, multiple chips can be tested simultaneously in parallel, reducing test time and reducing test equipment size.

1 is a diagram for describing an input data generating device for a general semiconductor memory device.

In general, the input data generator 20 is connected to a plurality of data input buffers for converting external input data DIN applied to an input / output pad into an internal signal and outputs the output signals of the plurality of data input buffers, respectively. And a data input driver for amplifying the output signal of the buffer and outputting it through the write global input / output line (WGIO).

In order to perform data compression test by inputting data into the input data generating device 20, data is input to only some input / output pads without applying data to all the input / output pads externally, and the data is output from the data input buffer. The signal is shared by the data input driver.

For example, if eight input / output pads are provided, the data input driver inputs data only to the 0th and 4th input / output pads and is connected to the 1st to 3rd data input buffers, and the data outputted from the 0th data input buffer. Is used as input data, and the data input driver connected to the fifth to seventh data input buffers uses the data output from the fourth data input buffer as input data.

In the data compression test mode, the input data generation device 20 enables the external input data DIN, the reference voltage VREF, the synchronized clock signal DLL_CLK, the data input strobe signal DINSTBP, and the test mode enable. In response to the signals TM_COMP, TM_COMP1 and TM_COMP2, the input data DIN is amplified and output to the even / odd write global input / output lines WGIO_e0 / WGIO_o0 to WGIO_e3 / WGIO_o3.

Here, the test mode enable signals TM_COMP, TM_COMP1, and TM_COMP2 are signals output from the test signal generator 10 in response to the address signal ADD and the mode register setting signal MRSP.

Since the general input data generating device uses the data input to one input / output pad in common in the data compression mode, for example, the four data input drivers have the same output signal from the four data input drivers. The same data is stored in. That is, since the type of the pattern to be tested is limited, there is a problem in that the input data must be changed several times in order to perform the test using another pattern.

In order to solve this problem, a method of changing the same input data using a separate test mode enable signal and using it in a data input driver is considered. However, in this case, it is not limited to generating a test pattern. It takes time, and there is inconvenience such as the need to use a separate test device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and provides an input data generating device capable of simply generating various test patterns by performing a test by changing input data using a column address in a data compression test mode. There are technical challenges.

Another technical problem of the present invention is to shorten the time required for data compression test by performing a test using various test patterns.

According to an aspect of the present invention, there is provided an input data generating device including at least one first input data driver for generating test data using external data received in a data compression test mode, and the data. At least one second input data receiving the test data generated from the first input data driver instead of the external data in a compressed test mode, and controlling and outputting a logic level of the test data as a pattern control signal which is a column address signal. Contains the driver.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a schematic diagram of an input data generation device according to the present invention, and FIG. 3 is a detailed configuration diagram of the input data generation device shown in FIG.

2 and 3, the input data generating device 140 of the present invention includes at least one input data driver 1400 # 0, 1400 # 4; 1 input data driver ') and at least one input data driver (1400 # 1) for receiving test data generated by the first input data drivers 1400 # 0 and 1400 # 4 without external data being input in the compression test mode. 1400 # 3, 1400 # 5-1400 # 7, hereinafter referred to as 'second input data driver'. The second input data driver 1400 # 1 to 1400 # 3 and 1400 # 5 to 1400 # 7 use at least one of the column address signals output from the address latch unit 120 as the pattern control signal C_AT_TM. The logic state of the test data provided by the first input data drivers 1400 # 0 and 1400 # 4 is controlled and output.

More specifically, referring to FIG. 2, the address buffer 110 buffers and outputs the address signal in response to the address signal ADD and the reference voltage VREF, and the address latch unit 120 outputs the address buffer ( The column address signal C_AT and the pattern control signal C_AT_TM are output in response to the output signal ADDBUF and the column address strobe signal C_ADDSTB of 110.

In addition, the input data generating device 140 includes at least one first input data driver and at least one second input data driver, wherein the first input data driver includes external input data DIN, a reference voltage VREF, In response to the synchronized clock signal DLL_CLK, the data input strobe signal DINSTBP, and the test mode enable signal TM_COMP, test data generated from the external input data DIN is even / odd write global. Outputs to I / O lines WGIO_e0 / WGIO_o0 to WGIO_e3 / WGIO_o3, and the second input data driver outputs a reference voltage VREF, a synchronized clock signal DLL_CLK, a data input strobe signal DINSTBP, and a test mode enable signal TM_COMP. And the logic level of the test data provided from the first input data driver in response to the pattern control signal C_AT_TM output from the address latch unit 120. The.

The test mode enable signal TM_COMP is a signal output from the test signal generator 10 in response to the address signal ADD and the mode register setting signal MRSP.

For example, in FIG. 2, when the input address signal ADD is 12 bits, the column address output from the address latch unit 120 becomes C_AT <3: 9>. That is, not all column addresses are used in the read / write operation, only the column addresses C_AT <3: 9> are used, and the remaining column addresses, that is, C_AT <0: 2, 10, 11> are not used.

Therefore, if the test data is controlled using at least one of the unused column addresses as the pattern control signal C_AT_TM, various patterns for data compression testing can be generated without the need for adding a separate test device. will be.

In FIG. 3, for example, when there are eight input / output pads (DQ pads), at least one of the second input data drivers 1400 # 1 to 1400 # 3 is input to the input data drivers 1400 # 1 and 1400 # 3. The pattern control signal C_AT_TM <0> is input and the pattern control signal C_AT_TM is input to at least one of the second input data drivers 1400 # 5 to 1400 # 7. (1)) to control the logic state of the test data provided from the first input data driver.

The second input data driver 1400 # 1 to 1400 # 3 and 1400 # 5 to 1400 # 7 may receive input data DIN <0> and DIN <4> from the first input data driver 1400 # 0 and 1400 # 4. ) Receives test data (ALGN_COMP <0>, ALGN_COMP <4>) generated by parallel conversion, and in particular, the second input data driver (1400 # 1, 1400 # 3, 1400 # 5, 1400 # 7) receives test data. In addition to the (ALGN_COMP <0>, ALGN_COMP <1>), the pattern control signals C_AT_TM <0> and C_AT_TM <1> are input to control the logic level of the test data. For example, when the pattern control signal C_AT_TM <0> is supplied at a high level, the input data drivers 1400 # 1, 1400 # 3, 1400 # 5, and 1400 # 7 may receive the test data ALGN_COMP <0>. When the logic level is shifted and output and the pattern control signal C_AT_TM <0> is supplied at the low level, the input data drivers 1400 # 1, 1400 # 3, 1400 # 5, and 1400 # 7 receive the test data ALGN_COMP. <0>) is output without changing the level.

On the other hand, the pattern control signal input terminals of the first input data driver 1400 # 0 and 1400 # 4 and the second input data driver 1400 # 2 and 1400 # 6 to which the pattern control signal C_AT_TM is not input are connected to the ground terminal. It is preferable to connect to (VSS).

In addition, the output signal DOUT of each input data driver 1400 # 0 to 1400 # 7 is output through the write global input / output line WGIO.

FIG. 4 is a detailed configuration diagram of the input data driver illustrated in FIG. 3. The operation of the first input data driver and the operation of the second input data driver will be described as follows.

First, when the input data driver shown in FIG. 4 operates as an input data driver into which external data is input, after converting the external input data DIN into the internal data DIN4, the test mode enable signal TM_C0MP is generated. As enabled, it generates test data ALGN_COMP <0: n> from internal data DIN4 and then writes the global write I / O lines WGIO_e <0: n / 2-1>, WGIO_o <0: n / 2-1> ) On the other hand, in the normal mode other than the data compression test mode, the data (ALGN <0: n>) obtained by converting the internal data DIN4 in parallel is written to the write global I / O lines WGIO_e <0: n / 2-1> and WGIO_o <0: n / 2-1>).

Meanwhile, when the input data driver 1400 illustrated in FIG. 4 operates as the second input data driver, external input data DIN does not exist, and the second input data driver is a test generated by the first input data driver. The global level of the write global I / O line WGIO_e <0: n / is controlled by receiving the data ALGN_COMP <0: n> and controlling the logic level of the test data ALGN_COMP <0: n> by the pattern control signal C_AT_TM <0>. 2-1>, WGIO_o <0: n / 2-1>).

The configuration of the input data driver 1400 will be described in more detail as follows.

The data input buffer 1410 of the input data driver 1400 outputs the internal data DIN4 in response to the external data DIN and the reference voltage VREF, and the latch unit 1420 at the data input buffer 1410. In response to the output internal data DIN4, the synchronized clock signal DLL_CLK, and the test mode enable signal TM_COMP, when the test mode enable signal TM_COMP is disabled, that is, in the normal mode, the internal data ( Outputs data in parallel conversion of DIN4) (AGLN <0: n>), and when the test mode enable signal (TM_COMP) is enabled, that is, in the data compression test mode, in parallel conversion of the internal data (DIN4) Output the data ALGN_COMP <0: n>.

In addition, the input data multiplexer 1430 may perform parallel conversion of the data ALGN <0: n>, the test data ALGN_COMP <0: n>, the pattern control signal C_AT_TM <0>, and the test mode enable signal TM_COMP. In response to the test mode enable signal TM_COMP is enabled, the pattern-controlled test data ALGND_COMP <0: n> is output.

In addition, the input data sense amplifier 1440 may perform pattern controlled test data ALGND_COMP in response to the pattern controlled test data ALGND_COMP <0: n> and the input data strobe signal DINSTBP output from the input data multiplexer 1430. <0: n> is amplified and output to the write global I / O lines WGIO_e <0: n / 2-1> and WGIO_o <0: n / 2-1>.

The input data driver 1400 illustrated in FIG. 4 maintains or outputs the logic level of the test data ALGN_COMP <0: n> as it is or according to the logic level of the pattern control signal C_AT_TM <0>. This will be described below with reference to FIG. 5.

FIG. 5 is a detailed circuit diagram of the input data multiplexer shown in FIG. 4.

As shown, the input data multiplexer 1430 is connected to a plurality of (n + 1) comparators 200 # 0 to 200 # n and output terminals of the comparators 200 # 0 to 200 # n, respectively. A plurality of pattern-controlled test data ALGND_COMP is output in response to the output signal ACOMP of the comparator 200 # 0 to 200 # n, the parallel-converted data ALGN, and the test mode enable signal TM_COMP. The multiplexers 210 # 0 to 210 # n are included.

Here, each of the comparators 200 # 0 to 200 # n receives the test data ALGN_COMP and the pattern control signal C_AT_TM, and when the logic level of the pattern control signal C_AT_TM is high, the test data ALGN_COMP. ), The comparison signal ACOMP is output by inverting the level, and when the logic level of the pattern control signal C_AT_TM is low, the comparison signal ACOMP is output while maintaining the logic level of the test data ALGN_COMP.

To this end, each of the comparators 200 # 0 to 200 # n receives a test logic ALGN_COMP and a pattern control signal C_AT_TM, and compares and outputs the first logic element G1 and the inverted signal of the test signal. The second logic element G2 and the output signals of the first logic element G1 and the second logic element G2, which receive and compare the ALGN_COMPb and the inversion signal C_AT_TMb of the pattern control signal, are compared with each other. The third logic element G3 for outputting the comparison signal ACOMP may be configured, and the first to third logic elements G1, G2, and G3 may be configured as NAND gates, respectively.

As can be seen in FIG. 5, when the pattern control signal C_AT_TM is input at the high level, the test data ALGN_COMP is inverted and output, and the pattern control signal C_AT_TM is input at the low level or the pattern control signal is input. When the terminal is connected to the ground terminal, it can be seen that the level of the test data ALGN_COMP is maintained as it is.

FIG. 6 is a detailed circuit diagram of the multiplexer shown in FIG. 5.

As illustrated, the multiplexer 210 amplifies a signal selected by the selector 2110 and the selector 2110 for selecting any one of the parallel-converted data ALGN and the comparison signal ACOMP, and performs pattern controlled test data. And an amplifier 2120 for outputting (ALGND_COMP).

Here, the selector 2110 is driven by the test mode enable signals TM_C0MP and TM_COMPb to output the first transmission gate T1 and the test mode enable signal T1 to output the data ALGN converted in parallel to the output terminal. The second transfer gate T2 is driven by TM_C0MP and TM_COMPb to output the comparison signal ACOMP to the output terminal. The amplifier 2120 may be implemented by serially connecting a plurality of inverting elements.

When the test mode enable signal TM_COMP is enabled in the multiplexer 210 of FIG. 6, the second transfer gate T2 is turned on, and accordingly, the comparison signal ACOMP is selected and the amplification unit 2120 is selected. When the test mode enable signal TM_COMP is disabled, the first transmission data T1 is turned on to be amplified and output as the pattern-controlled test data AGLND_COMP and the data ALGN is amplified and output.

FIG. 7 illustrates that data is input only to the first and fifth input / output pads DIN0 and DIN4 when eight input / output pads are used, and the column address signal C_AT <0: 1> is used as the pattern control signal C_AT_TM <0,1>. In the case of the compression test, the type of test pattern generated by the input data generator of the present invention is shown.

It can be seen that 16 test patterns are generated when the pattern control signal is controlled to 0 or 1 while changing the data input to the first and fifth input / output pads DIN0 and DIN4 to 00, 01, 10, and 11. . Therefore, the compression test can be performed in various patterns while minimizing the number of changes of external data.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

According to the present invention described above, various test patterns for the data compression test can be easily generated by using the column address signal.

In addition, since various test patterns can be generated within a short time, the number of changes of external data can be minimized, thereby reducing the time required for the data compression test.

Claims (13)

At least one first input data driver for generating test data using external data received in a data compression test mode; And At least one second receiving the test data generated from the first input data driver instead of the external data in the data compression test mode, and controlling and outputting a logic level of the test data using a pattern control signal which is a column address signal. An input data generating device of a semiconductor memory device comprising an input data driver. delete The method of claim 1, The first input data driver generates test data from the external data in response to external input data, a reference voltage, a clock signal, a data input strobe signal, and a test mode enable signal, and outputs the test data to the write global input / output line. An input data generating device of a semiconductor memory device. The method of claim 1, The second input data driver of at least one of the second input data drivers is provided by the first input data driver in response to a reference voltage, a clock signal, a data input strobe signal, a test mode enable signal, and a pattern control signal. And controlling the logic level of the test data to be output to a write global input / output line. The method of claim 1, The first and second input data driver, A data input buffer configured to output internal data in response to the external data and a reference voltage; In response to the internal data output from the data input buffer, a clock signal, and a test mode enable signal, when the test mode enable signal is enabled, the test data is output, and the test mode enable signal is disabled. A latch unit for outputting parallel converted data; And Input data for receiving the test data and the parallel-converted data output from the latch unit and outputting pattern-controlled test data when a test mode enable signal is enabled in response to a test mode enable signal and a pattern control signal. Multiplexer; Input data generating device of a semiconductor memory device comprising a. The method of claim 5, wherein The input data generating device may further include an input data sense amplifier configured to receive the pattern controlled test data output from the multiplexer and amplify and output the pattern controlled test data in response to an input data strobe signal. An input data generating device of a semiconductor memory device. The method of claim 5, wherein And the input data multiplexer inverts the test data when the logic level of the pattern control signal is high. The method of claim 5, wherein The input data multiplexer may include a comparator configured to receive the test data and the pattern control signal and output a comparison signal by controlling a logic level of the test data according to a logic level of the pattern control signal; And A multiplexer configured to output the pattern controlled test data in response to a comparison signal output from the comparator, the parallel converted data, and a test mode enable signal; Input data generating device of a semiconductor memory device comprising a. The method of claim 8, The comparator comprises: a first logic element configured to receive and compare the test data and the pattern control signal; A second logic device configured to receive and compare the inverted signal of the test data and the inverted signal of the pattern control signal; And A third logic element configured to receive and compare the output signal of the first logic element and the output signal of the second logic element; Input data generating device of a semiconductor memory device comprising a. The method of claim 9, And the first to third logic elements are NAND gates. The method of claim 8, The multiplexer includes a selector for receiving the parallel-converted data and the comparison signal, and selecting one of the two input signals and outputting the selected one. The method of claim 11, The selector is driven by the test mode enable signal and outputs the parallel-converted data to an output terminal; And A second transmission gate driven by the test mode enable signal and outputting the comparison signal to an output terminal; Input data generating device of a semiconductor memory device comprising a. The method of claim 11, The selector further comprises an amplifier for amplifying and outputting the signal output from the selector.

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