KR100812705B1 - Method for Linking Host Data in Programmable Logic ControllerPLC - Google Patents

Abstract

The present invention relates to a host data link method in a logical computing device. The host data link method in the logical operation device (PLC) of the present invention includes: a first step of checking a host command and determining whether the command is valid when a host command of a minimum size or more is received; A second step of requesting a service from a PLC central processing unit (CPU) when all data of an expected value are received; And a third step of sending a response to the host computer based on the response received from the PCPU. According to the present invention, the data link between the PLC performing the master (MASTER) function and the PLC performing the slave (SLAVE) function can be efficiently performed, thereby efficiently performing the data link between the PLC and satisfy the multi-channel requirements. It has the effect of making it possible.

PLC, data link, CPU, PCPU, host instruction

Description

Method for Linking Host Data in Programmable Logic Controller (PLC)}             

1 is a schematic diagram of a communication system to which the present invention is applied;

2 is a structural diagram of an embodiment of a host data link device in a PLC to which the present invention is applied;

3 is a flowchart illustrating a method of linking a host data in a PLC according to the present invention;

4A is a data structure diagram when a host computer reads data from a data link device;

4B is a data structure diagram when writing data from a host computer to a data link device;

5A is a structural diagram of a first embodiment of a data protocol when a host computer reads data from a PCPU;

5B is a structural diagram of a first embodiment of a data protocol when a host computer writes data into a PCPU;

6A is a structural diagram of a second embodiment of a data protocol when a host computer reads data from a PCPU;

6B is a structural diagram of a second embodiment of a data protocol when a host computer writes data into a PCPU;

7A is a structural diagram of a third embodiment of a data protocol when a host computer reads data from a PCPU;

7B is a structural diagram of a third embodiment of a data protocol when a host computer writes data into a PCPU;

8A is a structural diagram of a fourth embodiment of a data protocol when a host computer reads data from a PCPU;

8B is a structural diagram of a fourth embodiment of a data protocol when a host computer writes data into a PCPU.

* Explanation of symbols for the main parts of the drawings

210: main controller 220: 2-port storage unit

230: main storage unit 240: bus interface unit

250: sub-control unit 260: UART

270 interface

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a host data link method in a logic computing device, and more particularly to a host data link method in a logic computing device used to overcome reliability in input / output data link according to the distance between a controller, a driver and various sensors in a large-scale plant. It is about.

Generally, in the case of a programmable logic controller (hereinafter, simply referred to as a 'PLC'), a central processing unit (hereinafter, simply referred to as a 'CPU') may use a serial port built in the module itself. Communication system can be established through

However, in order to communicate a large amount of data through several channels at the same time, a unit having several separate communication ports is required. The conventional PLC, as described above, establishes a communication system through a serial port built in the CPU module itself. Therefore, there is a problem in that input / output transmission of data between a driver and a plurality of sensors that exist at a long distance becomes difficult.

The present invention has been proposed in order to solve the above problems, and in order to communicate a large amount of data through several channels, by embedding several separate communication ports, the data between the driver and a plurality of sensors that exist at a long distance The purpose is to provide a host data link method in a PLC for facilitating input and output.

According to an aspect of the present invention, there is provided a host data link method in a logical operation device (PLC), comprising: a first step of checking a host command and determining whether the command is valid when a host command of a minimum size or more is received; A second step of requesting a service from a PLC central processing unit (CPU) when all data of an expected value are received; And a third step of transmitting a response to the host computer based on the response received from the PCPU.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same components have the same number as much as possible even if displayed on different drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram of a communication system to which the present invention is applied.

As shown in the figure, the communication system to which the present invention is applied, the system to which the present invention is applied, comprises a data link device 110 and a loader 120 of the present invention, and a plurality of host computers and modems. It can be linked with. Communication between each component may be performed through a wired / wireless network.

2 is a structural diagram of an embodiment of a host data link device in a PLC to which the present invention is applied.                     

As shown in the figure, the link device to which the present invention is applied includes a main controller 210, a two-port storage unit 220, a main memory unit 230, and a bus interface unit. 240, a control logic 250, a universal asynchronous receiver / transmitter (hereinafter, simply referred to as a 'UART') 260, and an interface 270.

The main storage unit 230 is responsible for storing program codes and data, and the two-port storage unit 220 is responsible for performing data processing.

Since the data link device of the present invention adopts a dual port memory access method, it is not possible to directly access the PLC bus, so that the bus interface 240 interworks with the PLC bus. In charge of the function.

In addition, the interface unit 270 is responsible for communicating with the host computer 130, and the UART 260 is responsible for connecting the data received from the main control unit 210 to the bit communication network. .

The main controller 210 receives a control of a PCPU (PLC CPU) to control input / output of data and allocates a map so that the main storage unit 230 stores the data. In addition, the two-port storage unit 220, responsible for the function to control the UART (260).

The sub-control unit 250 is responsible for generating, interpreting and using the control data.

Referring to the host data link method in the PLC using the host data link device to which the present invention as described above is as follows.

3 is a flowchart illustrating a host data link method in a PLC according to the present invention.

The start command of the data link method of the present invention has four modes (acknowledgment (ACK), negative response (NAK), inquiry (ENQ), and text start (STX)). After initializing the hardware (S301), the host command is continuously checked (S302).

At this time, if a host command of more than the minimum size is received, it distinguishes ACK, NAK, ENQ, and STX, and responds immediately in case of ACK and NAK. Wait until (character) comes in (S304).

When all data of the expected value is received, the service is requested to the PCPU (S305), and the response is transmitted to the host computer based on the response (S306 to S309) received from the PCPU (S310).

Errors occurring during this series of processes are processed by appropriate error codes and sent to the NAK (S304, S307).

On the other hand, the data link device of the present invention can transmit and receive data with respect to the command of the PCPU.

The PCPU sends a command indicating which port to use and how many data to send. In this case, the data link device can send the command to the corresponding port.

In this case, the PLC data link device must first be 'OPEN'. Through this OPEN command, the PLC data link device is defined as a communication port between PCPUs, and the general host command service is stopped.

After sending the data, the user waits for a response. The waiting time for this response can be specified in 10msec units through the 'CONNECT' command. For example, if CONNECT 20 is transmitted to the corresponding port, it waits for response in 200msec unit and can transfer the accumulated data to PCPU every 200msec.

The host data link method in the PLC of the present invention can link data between the PCPU and an external device including a host computer using four types of protocols and various commands.

Hereinafter, four types of protocols used in the present invention will be described, and first, a general structure of the protocols will be described.

4A is a data structure diagram when the host computer reads data from the data link device, and FIG. 4B is a data structure diagram when data is written from the host computer to the data link device.

In FIG. 4A, areas A and C mean data transmitted from a host computer to a PLC data link device (hereinafter, simply referred to as 'HDT'), and area B means data transmitted from a PLC HDL to a host computer. Means. At this time, data transmission proceeds in the order of left to right, and the program in the C area allows the communication to end and enter the next communication without communication.

In FIG. 4B, area A means data transmitted from the host computer to the PLC HDL, and area B means data transmitted from the PLC HDL to the host computer. At this time, the data is transferred in order from left to right.

In this case, the PLC HDL receives the ASCII code from the host computer, converts it into a BIN code, and then transmits the data to the PCPU, converts the empty code received from the PCPU into an ASCII code to host. Can be transferred to a computer That is, communication between all host computers and PLC HDL to which the present invention is applied is made up of ASCII codes.

FIG. 5A is a structural diagram of a first protocol of a data protocol when a host computer reads data from a PCPU, and FIG. 5B is a structural diagram of a first protocol of a data protocol when a host computer writes data to a PCPU.

6A, 7A, and 8A are structural diagrams of the second to fourth embodiments of the data protocol when the host computer reads data from the PCPU, and FIGS. 6B, 7B, and 8B are diagrams illustrating how the host computer sends data to the PCPU. Structure diagrams of the second to fourth embodiments of the data protocol at the time of writing.

For convenience, the first to fourth embodiments will be referred to as format I, format II, format III and format IV.

As shown in the figure, format III, unlike other formats, does not use ENQ and uses STX, so it can be easily distinguished using this.                     

To distinguish between format II, it is necessary to know the position of the instruction. All other formats have the form "ENQ (STX) + station number + PC number + command + WAIT +…", but format II is intermediate like "ENQ + BL number + station number + PC number + command + WAIT +…" BL number is 2 bytes more.

Therefore, when used together with other formats, the 6th and 7th bytes are recognized as commands, so the PC number of format II is recognized as a command. Since the PC number cannot be greater than "FF", there is no possibility of recognizing it as a command to the host computer. Therefore, if the command is not defined by analyzing the commands in the format I, the format III, and the format IV, the command as the format II can be analyzed. In this way, format II can be distinguished.

Format IV has no difference between Format I and CR, LF at the end. Since the CR and LF are not included in the checksum calculation, it can be distinguished by checking whether the character exists after the checksum.

As described above, format I, format II, format III and format IV are compared with the following equation.

Format I

Format II = Format I + Block (BL) Number

Format III = Format I + STX, ETX

Format IV = Format I + CR, LF                     

The code of each data format will be described below.

All control codes are transmitted / received in hexadecimal and are shown in Table 1 below.

At this time, the null code (00H) is ignored in all messages, and "GG" and "NN" in format III have the same meaning as "ACK" and "NAK" in other formats.

"BL Number" is an arbitrary number for appropriately referencing data when it is difficult to simultaneously transmit and receive a large amount of data, and the BL number can be used up to 00H-FFH.

"Station Number" is determined by two station number setting switches on the front of the CPU, and indicates the unique number of the corresponding station. The station number is given as a two-digit ASCII code from 00 to 99.

"PC Number" is the number of the corresponding host computer and only "FF" is useful. "Command" is used to command the desired operation and refers to the command from the host computer to the PLC HDL. The command consists of two ASCII code.                     

On the other hand, some types of computers may require a delay time in order to switch to a reception state after transmitting data. In this case, "WAIT (Wait For Message)" may specify an appropriate delay time according to the specifications of the computer.

The "Sum Check Code" is calculated only for the "*" display part, and the binary value of each part is added, and only the lower 1 byte (8 bits) is transmitted as the 2-digit ASCII code.

The "Error Code" is transmitted after the NAK and consists of a two-digit ASCII code in the 00H-FFH range. If more than one error occurs at the same time, only the lowest numbered code is sent.

The types of commands are shown in Tables 2 and 3 below.                     

On the other hand, the data link method of the present invention can be used when reading the remote RUN / STOP and CPU type (Type) of the CPU. The CPU instructions are shown in Table 4 below.                     

In addition, the error codes that PLC HDL provides after the NAK are shown in Table 5 below. If several types of errors occur, only the lowest number code is transmitted.

Lastly, the PLC HDL of the present invention not only exchanges data with each other through a sequence program between PCPUs, but also transmits and receives data with a general serial port. The sequence program is written using five commands: OPEN, CONNECT, ASEND, ARECV, and CLOSE. Using these commands, data frames of any structure can be transmitted and received.

The command used for this is described in detail as follows.

In "OPEN node port STATUS (WR)", "node" means a node number of a transmission and reception node, and "port" means an upper 8 bit slot number and a lower 8 bit slot number in the transmission and reception port. In addition, "STATUS (WR)" means a word register to be allocated to the STATUS register.

The PLC HDL can use node numbers from 0 to 7. It stores all the information about the connection to this node. The port designates the slot number and port number of the module to send and receive, and the register to use as the status register in STATUS.

In addition, "CLOSE node" initializes the node information used for communication and also initializes the information of the connected communication module.

In "ASEND node REG1 REG2", REG1 means a register to be transmitted and REG2 means a data counter to be transmitted.

In "ARECV node REG1 REG2", REG1 means a register to store data to be received, and REG2 means a maximum counter to be received. If more data is received than the value specified in REG2, only the number of data specified in REG2 is read. If there are only 50 registers available and the Receive Counter may exceed 50, you need to define the maximum value for this value. When 50 or less values are received, the received counter is stored in REG2.

Finally, "CONNECT node DREG1 DREG2" is a command to specify the time to receive the received data of the PLC HDL. Waiting time is specified in DREG1 in 10msec units. If this command is not executed, it is basically set to 20 and receives data for 200msec from the first received data and passes it to PCPU. If you set 200 in DREG1, it will wait 2000msec, or 2 seconds.

The method of the present invention as described above may be implemented as a program and stored in a computer-readable recording medium (CD-ROM, RAM, ROM, floppy disk, hard disk, magneto-optical disk, etc.).

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

According to the present invention as described above, the data link between the PLC performing the master (MASTER) function and the PLC performing the slave (SLAVE) function is efficiently performed, thereby efficiently performing the data link between the PLC, and multi-channel This has the effect of satisfying the demand.

Claims (3)

In the host data link method in a logical operation unit (PLC), Checking a host command and determining whether the command is valid when a Hexadecimal number is received at least 02H; A second step of requesting a service from a PLC central processing unit (CPU) when all data of an expected value are received; And The third step of sending a response to the host computer based on the response received from the PCPU Host data link method in the PLC including a. The method of claim 1, If an error occurs, the fourth step of transmitting the NAK by treating it with an appropriate error code Host data link method in the PLC further comprising. The method of claim 1, The determination of the valid command of the first step, ACK, NAK, ENQ, STX is classified and responds immediately in case of ACK / NAK, and in case of ENQ / STX, calculates the expected data size and waits for receiving more data. Host data link method in the PLC, characterized in that.

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