KR100810780B1 - Tracking of a multi-path resolved signal in a rake receiver - Google Patents

Abstract

A rake receiver tracks a multi-path signal transmitted from a base station to a mobile station. The rake receiver comprises rake fingers each assigned to a multi-path component. Typically a rake finger performs an early late detection using early and late component of the energy of the component taken before and after a presumed occurrence of an optimum of the energy. An early-late signal is generated from a comparison between a product of a first integer and the early component and a product of another integer and the late component.

Description

TRACKING OF A MULTI-PATH RESOLVED SIGNAL IN A RAKE RECEIVER}             

The present invention relates to a method for tracking the decomposition components of a multipath signal assigned to a rake finger of a spread spectrum rake receiver, in particular spread spectrum communication such as a CDMA handset. A rake receiver included in a device.

Cellular communication systems are well known. Such cellular communication systems include a cell or a radio zone, which together cover a given geographical area. The cell establishes and maintains communication links with mobile communication devices included in the system via a control and communication channel, and includes a base station that communicates with the mobile communication device over an established communication link.

One type of cellular communication system is a so-called direct sequence code division multiple access (CDMA) spread spectrum system. In such CDMA spread spectrum systems, mobile communication devices typically decompose components of spread spectrum signals received in multiple paths in addition to transmitters, and diversity combine the resolved components to vary the signal to noise ratio of the received signal. It has a so-called rake receiver having a plurality of rake fingers to enhance. The spread spectrum signal is received from a transmitter that spreads the data signal in a frequency band using a spreading sequence. The components of this sequence are so-called chips. In order to spread different data signals at different transmitters, Walsh sequences are used for channelization, and pseudo-noise-spreading sequences are used for scrambling. The rake receiver receives the spread spectrum received by de-scrambling the received spread spectrum signal into the same pseudo noise sequence and then de-spreading the signal into the Walsh sequence used for spreading the data signal. Regenerate the data signal from the signal, and diversity combine the multipath received signals generated from the same data signal. The rake receiver needs to be synchronized to the transmitter that initially wants to receive the data signal. During this initial synchronization, a searcher included in the rake receiver decomposes the components of the multipath received signal, which components arise from the desired data signal. The rake receiver then employs tracking mode synchronization to keep the rake fingers synchronized to the resolved components resulting from the same desired data signal. During tracking mode synchronization, the rake fingers remain aligned with their disassembled components.

Summary of the Invention

It is an object of the present invention to provide a rake receiver in which the rake fingers are aligned to the decomposition components of their multipath signal using simple alignment means during tracking mode synchronization.

It is a further object of the present invention to provide a rake receiver having alignment means requiring a limited amount of memory.

It is yet another object of the present invention to provide a rake receiver with reduced power consumption.

According to the present invention, there is provided a method for tracking the decomposition component of a multipath signal assigned to a rake finger of a spread spectrum rake receiver, the method comprising:

Variably delaying said degradation component,

Performing an early-late detection on the variable delayed degradation component to determine whether the degradation component has reached first or later for an optimal time of arrival, and the early-expiration Generating a first pulse if the detection determines that the decomposition component has arrived first, and generating a second pulse if the early-expiration detection determines that the decomposition component has arrived later;

-Counting the first pulse, the first pulse causing a count in a first direction, and the second pulse-the second pulse causing a count in a second direction;

Deriving a fractional-chip delay timing adjustment signal from the counting step and feeding back the derived partial chip delay timing adjustment signal to adjust the variable delay of the decomposition component; ,

Deriving a chip delay phase adjustment time from the counting step and feeding back the induced chip delay phase adjustment signal to control the phase of a pseudo noise generator.

The present invention is based on the insight that a simple variable delay device can be used to provide a variable delay by distributing multipath alignment for the timing alignment of the variable delay and the phase alignment of the pseudo noise generator.

In an embodiment, a shift register performs a variable delay. Due to the present invention, the shift register may be made very short and typically has only eight sections.

Preferably, at least a portion of the variable delay is obtained with a bulk delay of the adjustable digital filter. Here, the length of the shift register can typically be further reduced by 2 or 4 samples per chip. Reduction of samples, thereby reducing clock rate and complexity at the receiver, results in reduced power consumption and reduced chip area. The delay of the digital filter can be adjusted by selecting a filter coefficient from the lookup table, the entry of the lookup table including filter coefficients representing a predetermined delay.

In an embodiment, the counter counts pulses generated by the early-expiration detector. The first counter counts pulses to obtain a partial chip delay timing adjustment signal, and provides a carry signal to the second counter at the chip boundary. The second counter provides a chip delay phase adjustment signal for controlling the phase of the pseudo noise generator.

1 diagrammatically shows a CDMA spread spectrum system;

2 is a diagram illustrating decomposition components and early / expiration signals of a multipath signal;

3 illustrates a communication device having a rake finger in a rake receiver in accordance with the present invention;

4 illustrates an early / expiration detector in a rake finger of a mobile communication device in accordance with the present invention;

5 shows a counter device in a rake finger in accordance with the present invention;

6 illustrates an adjustable digital FIR filter in a rake finger in accordance with the present invention;

7 shows a lookup table with filter tap coefficients for a FIR filter, FIG.

8 illustrates a controllable shift register in a rake finger in accordance with the present invention.

In the drawings, like reference numerals are used to indicate like features.

1 diagrammatically shows a CDMA spread spectrum system 1. Such a system 1 comprises wireless zones 2 to 8, each wireless zone comprising base stations 9 to 15. The mobile communication device 16 is included in the wireless zone 7. The mobile communication device 16 may be a cell phone or a handset, or other suitable mobile communication device. In the given example, the system 1 is a direct sequence spread spectrum system and the mobile communication device 16 comprises a rake receiver as shown in more detail in FIG. A group of autonomous base stations is coupled to switching centers (not shown), which are coupled to each other.

2 shows the decomposition components 20-22 of the multipath signal and the early / expiration signals E and L. When initially synchronizing the mobile communication device 16 with the system, a searcher (not shown in detail) in the power-on state of the device 16 disassembles the components 20 to 22 from the system 1. Are then assigned to the rake fingers of the rake receiver. Such initial synchronization is well known in the art. Thereafter, the rake fingers adopt tracking mode synchronization, with each rake finger aligned and kept aligned with its disassembled components. Early / expiration signals E and L represent each current situation where the rake finger first or later receives the multipath component for the optimal reception time 23 which is the maximum signal energy.

3 shows a communication device 16 having a rake finger 30 in a rake receiver in accordance with the present invention. The rake receiver diversity combines the decomposition components of the multipath signal to form a diversity combined signal supplied to the symbol detector. The communication device 16 includes a wireless transmit and receive front end 31 and a plurality of rake fingers, in which the rake fingers 30 are shown. The wireless front end 31 provides typical receive, down-mixing, signal sampling and transmission tasks, and provides a sampled baseband signal, which is a complex input signal 32 to the rake fingers. In principle, the complex input signal may be a low intermediate frequency signal. The transmit branch is denoted by Tx. Only rake fingers 30 are shown in greater detail for the purposes of the present invention. The processing means processes the complex input signal 32. Such processing means may be hard-wired logic or DSP signal (Digital Signal Processor firmware) or software program. In the illustrated embodiment, the rake finger 30 includes a complex variable delay device 33 that delays the complex input signal for up to eight samples (chip contains eight samples) of the complex input signal 32. do. Complex variable delay 33 provides a partial chip delay of complex input signal 32. Once the correct partial chip delay is applied, the delay signal is immediately downsampled to one sample per chip by down sampling means that decimates the delayed signal to eight. The down sampled signal 35 is then multiplied by the conjugate complex number of the complex PN (pseudo noise) sequence 36 generated by the pseudo noise generator 37. At the chip boundary, the complex PN sequence is adjusted in phase to match the decomposition component 22 of the complex input signal 32. The resulting descrambled signal 37 provided by multiplier 38 is then generated by multiplier 39, orthogonal variable spreading factor code (OVSF) generated by VSF sequence generator 41, such as the Walsh code. Multiplied by the same OVSF code. In addition, the phase of the OVSF code is controlled by the delay locked loop shown, providing both the partial chip and chip boundary control signals. Next, in the embodiment given above 64 chips, a sliding integrator 42 provides sliding integration over the length of the OVSF code 40. After integration, the complex variable delay 43 provides delay equalization to the integer of the nearest symbol before decimation by 64 to the symbol rate by the down sampling means 44. Typically, also eventually, to generate an output, a de-spread signal 45 is obtained from a pilot channel broadcast by a base station, for example base station 14. The conjugate complex number of a channel tap estimate is multiplied. The timing control means 46 provides a delay control signal to the complex variable delays 33 and 43 and a phase control signal to the PN sequence generator 37 and the OVSF sequence generator 41. The rake finger 30 further comprises an early / expiration detector 47 which provides the timing control means 46 with power estimation signals of the early and expiration signals E and L.

4 shows an early / expiration detector 47 in the rake finger 30 of the mobile communication device 16 according to the invention. The early / expiration detector 47 has respective pre and post branches 60 and 61. Early / expiration timing detector 47 is used to derive a feedback signal for the timing loop. Decimation-by-eight operations by two 8 are performed at different timing offsets by the respective down samplers 62 and 63. The timing offset is selected in the sample isolation of the portion of the chip. The pre and post branches 60 and 61 are both descrambled by multiplication with the conjugate complex numbers of the scrambling PN sequence with their respective multipliers, followed by integral-and-dump operations 66 and 67. Are integrated for each period. The complex magnitude is then squared on both branches 60 and 61 by the squarer devices 68 and 69 to provide additional integration and dump to provide the power estimation signals 72 and 73 of the early and expiration signals E and L. This allows for subsequent non-coherent integration by integrate-and-dump operations 70 and 71. The timing error signal e is derived at processing block 74 using the logic below. E = -1 when three times the power estimation signal of signal E is greater than two times the power estimation signal of signal L; otherwise, three times the power estimation signal of signal L is greater than two times the power estimation signal of signal E E = +1, else e = 0. Thus, a dead zone exists in the region where the power estimate of E ≤ 3/2 divided by the power estimate of 2/3 ≤ L. Where ≤ represents the same or less. The timing error event of the early signal and the expiration signal has a value of either a positive unit pulse or a negative unit pulse depending on the output of the early / expiration detector 47, ie the direction of the error. In order to derive the various timing control signals required for the rake finger 30, the pulses 75 are counted by an up / down counter correctly configured in the timing control means 46.

5 shows a counter device in a rake finger 30 according to the invention. The counter device comprises up / down counters 81, 82 and 83 which provide control signals 84, 85 and 86, respectively. A counter carry signal 87 of counter 81 is provided to the hold input of counter 82 via an inverter 88 and counter carry signal 89 of counter 82. Is provided to the hold input of counter 83 via inverter 90. Positive and negative unit pulses 75 are isolated by comparators 91 and 92 and provided to the up and down counter inputs of respective counters 81-83. Counters 81-83 are clocked according to the initial delay estimate (as provided through the initial synchronization to system 1). The additional estimate is loaded into the counter, and then decreases to zero. During times when counter values are greater than zero, control inputs to counter chains 81 to 83 and PN sequence generator 37 are held in logic '1' so that they are preloaded values. . Thereafter, the control input is switched to the output of the early-expiration event detector 47. Equivalent functionality can be obtained by using a presettable counter and a preset PN sequence. The up / down counters 81 to 83 are samples, chips and symbol counters each having a cycle count value equal to the number of samples per chip, the number of chips per symbol, and the number of symbols per frame. Thus, the output or control signals 84, 85, and 86 control the sample delay control signal, the slewable OVSF sequence generator 41, which controls the complex variable delay 33 at the partial chip delay. A symbol delay control signal used outside the rake finger 30 for symbol alignment prior to the maximum ratio combination of the chip delay control signal and the output signal of the different rake fingers. The PN sequence generator 37 is a conjugated complex PN source including a slewable PN generator that forms a complex real part and an imaginary part of the PN source. Conjugate complex numbers are obtained by invalidating the polarity of the imaginary output. The PN generator block accepts a control input of +1 or -1 to speed up or slow down the generator phase by one chip. That is, the PN generator only shifts when the sample clock rolls over from one chip to another.

Once the sample delay control signal, the chip delay control signal and the symbol delay control signal are obtainable, it is possible to derive the necessary timing control value inside the rake finger 30. The following equation is implemented in the timing control means.

The complex variable delay 33 is set to the value of δ ₁ = N _s 1 -sample delay control signal (N _s is the number of samples per chip).

The phase of the slewable OVSF generator is set to the minus value of the chip delay control signal.

The complex variable delay 43 is set to the value of the N _w 1-chip delay control signal (N _w is the number of chips per Walsh symbol).

The total delay calculated by the rake finger 30

d = a _total of N times N _{s w} times the value of the sample delay control times N _s + symbol delay control signal of the value of the chip delay control signal + signal value.

In the above described embodiment, oversampling rates between 4 and 8 samples are used. In another embodiment, using an adjustable FIR filter to produce a time delay, the oversampling rate and thus power consumption is preferably reduced.

6 shows an adjustable digital FIR filter 100 of another embodiment of a rake finger 30 according to the present invention. The filter 100 is used to generate at least part of a partial chip or sub-chip delay. For this purpose, the bulk delay of the filter 100 is chosen. In this way, a rake finger is constructed that requires only two or four samples per chip at its input. Depending on the structure of the analog converter included in the front end 31 and the receiver's tolerance to aliasing, the maximum sampling rate used by the CDMA receiver can thereby be reduced. In the described embodiment, the adjustable digital FIR (finite impulse response) filter 100 sets the pre-calculated FIR tap coefficients 105 to 108 that set the tap weights 109 to 112 of the filter 100. Has four filter stages 101 to 104 having a set of Using the adder stage 113, the outputs of the weighted filter stages are summed to produce the filter output signal 114.

7 shows a lookup table 120 with entries of filter tap coefficients 105-108 for the FIR filter 100 for the desired bulk delay. Each set of FIR filter coefficients has a predetermined group delay while operating as a low pass filter. FIR filter coefficients are synthesized directly from the desired response using an inverse Fast Fourier Transform. To facilitate the calculation, the frequency response is assumed to be an ideal low pass filter with a cliff-edge at half the Nyquist frequency. The phase is assumed to be linear with respect to the slope according to the required group delay.

Using the above principle, the table below is an example of filter coefficients suitable for time shifting.

8 illustrates a clocked controllable shift register 130 of a rake finger 30 according to the present invention as an embodiment of the real part of the complex variable delay 33. Register 130 has eight shift register sections. The shift register contains at most eight samples of the input signal 32. To generate the desired partial chip delay, the output 131 of the register 130 is coupled to the appropriate shift register section.

In view of the foregoing, various modifications may be made within the spirit and scope of the invention as defined by the appended claims, and therefore, it will be apparent to those skilled in the art that the invention is not limited to the examples provided. something to do. The term "comprising" does not exclude the presence of elements or steps other than those described in a claim.

Claims (10)

Tracking a resolved component 20 to 22 of the multipath signal 32 assigned to a rake finger 30 of a spread spectrum rake receiver. In the method, Variably delaying the decomposition component (33), An early-late detection 47 is performed on the variable delayed degradation component to determine whether the degradation component reached early (E) or reached late (L) for an optimal time of arrival (23). The first pulse 75 is generated when it is determined that the decomposition component has arrived early in the early-expiration detection, and when it is determined that the decomposition component has arrived late in the early-expiration detection. Generating a second pulse, Counting the first and second pulses, wherein the first pulses cause counting in a first direction and the second pulses cause counting in a second direction (81, 82, 83), A fractional-chip delay timing adjustment signal 84 is derived from the counting step, and the feedback of the induced partial chip delay timing adjustment signal is fed back to the decomposition components 20 to 22. Adjusting the variable delay step 33 of, A chip delay phase adjustment signal 85 is derived from the counting step and a pseudo-noise generator 37 is fed back by feeding the induced chip delay phase adjustment signal 85. Controlling the phase of Tracking method comprising a. The method of claim 1, Performing the variable delay step 33 by the maximum number of samples per chip in the multipath signal 32, and counting carry signals 87 from the partial chip counting step 81 during the counting step. Thereby generating the chip delay phase adjustment signal (85), wherein the partial chip counting step results in the carry signal at a coefficient value representing the number of samples per chip. The method of claim 2, A tracking method for generating the partial chip delay timing adjustment signal (84) from the partial chip counting step (81). The method of claim 1, And variably delaying (33) by controlling a shift register (130) using the partial chip delay timing adjustment signal (84). The method of claim 1, And variably delaying (33) by controlling a delay of a digital filter register (100) using the partial chip delay timing adjustment signal (84). As a rake receiver, A rake finger 30 of a spread spectrum rake receiver; The rake finger 30 tracks the decomposition components 20 to 22 of the multipath signal 32 assigned to the rake finger 30, Means 33 for variably delaying the decomposition components 20 to 22, Early-expiration detection 47 is performed on the variable delayed degradation components 20-22 to determine whether the degradation components arrive early (E) or late (L) for the optimal time of arrival (23). And a first pulse when the decomposition component arrives early in the early-expiration detection, and a second pulse when the decomposition component arrives late in the early-expiration detection. Means for generating a (74), Means (81,82,83) for counting the first and second pulses 75, wherein the first pulse causes digitization in a first direction and the second pulse is digitized in a second direction Causes -and, Means for deriving a partial chip delay timing adjustment signal 84 from the coefficients and feeding back the derived partial chip delay timing adjustment signal to adjust the variable delay 33 of the decomposition components 20 to 22; Means for deriving a chip delay phase adjustment signal 85 from the coefficients and feeding back the induced chip delay phase adjustment signal 84 to control the phase of the pseudo noise generator 37. Rake receiver comprising a. As a rake receiver, A rake finger 30 of a spread spectrum rake receiver, The rake finger 30 tracks the decomposition components 20 to 22 of the multipath signal 32 assigned to the rake finger 30, A variable delay device 33 configured to delay the decomposition components 20 to 22, Early-expiration detection is performed on the variable delayed degradation component to determine whether the degradation component arrived early (E) or late (L) for the optimal time of arrival (23), and in the early-expiration detection An early-expiration detector configured to generate a first pulse if it is determined that the decomposition component has arrived early and to generate a second pulse if it is determined that the decomposition component has arrived late in the early-expiration detection. With 47, An adjustable pseudo noise generator 37 for generating a pseudo-noise sequence that descrambles the decomposition component; A first counter 81 configured to count the first and second pulses 75-the first counter 81 converts the time alignment of the rake finger 30 into the decomposition components 20-22. Providing a partial chip delay timing adjustment signal 84 to the variable delay device 33 to provide < RTI ID = 0.0 > A second counter 82-the second counter 82 configured to count the carry signal 87 generated by the first counter 81 to provide the decomposition component with the phase alignment of the rake fingers. Providing a chip delay phase adjustment signal 85 to an adjustable pseudo noise generator 37 Rake receiver comprising a. The method of claim 7, wherein The variable delay device 33 is a digital filter 100 having an adjustable delay set through selection of a shift register 130 or filter coefficients 109 to 112, and Filter coefficients 109 through 112 are selected from a look-up table 120 included in the rake receiver, the lookup table having a rake having an entry of filter coefficients corresponding to a predetermined delay. receiving set. The method of claim 7, wherein And the variable delay device is a combination of a shift register and a digital filter having an adjustable delay. A mobile communication device (a) in communication with a plurality of cells (2 to 8) and base stations (9 to 15) covering the cells and one of the base stations (9 to 15) A spread spectrum communication system 1 having a mobile communication device) 16, The mobile communication device 16 has a rake receiver with a rake finger 30, The rake finger 30 tracks the decomposition components 20 to 22 of the multipath signal 32 assigned to the rake finger 30, Means 33 for variably delaying the decomposition components 20 to 22, Means for performing early-expiration detection 47 on the degradation components 20-22 to determine whether the degradation components arrived early (E) or late (L) for an optimal time of arrival (23); Generate a first pulse if the early-expiration detection determines that the decomposition component has arrived early, and generate a second pulse if the degradation component has reached late in the early-expiration detection. Means 74, Means (81,82,83) for counting the first and second pulses 75, wherein the first pulse causes a count in a first direction and the second pulse causes a count in a second direction - Means for deriving a partial chip delay timing adjustment signal 84 from the coefficients and feeding back the derived partial chip delay timing adjustment signal to adjust the variable delay 33 of the decomposition components 20 to 22; Means for deriving a chip delay phase adjustment signal 85 from the counting step and feeding back the induced chip delay phase adjustment signal 85 to control the phase of the pseudo noise generator 37 Spread spectrum communication system comprising a.

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