KR100805092B1 - Stacked multi-chip package and the fabrication method thereof - Google Patents

Abstract

The multilayer multichip package according to the present invention applies a general repositioning technique to form redistribution and bumping pads for applying a flip chip connection to pads in which electrical characteristics are important in a chip on a wafer, and simultaneously wires to the remaining pads. A wire bonding pad is formed to apply a bonding connection. In this case, when the first dielectric layer is formed, a groove is formed so that the first dielectric layer does not exist at the edge of the upper surface of the semiconductor chip in the direction in which the wire bonding pad is to be located, and the second dielectric layer is formed. When forming, the wire bonding pad portion is also exposed so that the dielectric layer does not exist to provide a structure that can reduce the package thickness by securing a space for easy wire bonding connection without the spacer used in the existing multi-chip package.

Description

Stacked Multi-Chip Package and Its Manufacturing Method {STACKED MULTI-CHIP PACKAGE AND THE FABRICATION METHOD THEREOF}

1 is a cross-sectional view showing a conventional stacked multi-chip package structure,

2A to 2F are cross-sectional views illustrating each step of a redistribution process in a manufacturing step of a stacked multi-chip package according to an embodiment of the present invention;

3 is a cross-sectional view illustrating a wire bonding step after a redistribution process in a manufacturing step of a stacked multi-chip package according to an embodiment of the present invention;

4 is a cross-sectional view showing a stacked multi-chip package structure according to an embodiment of the present invention;

4A is an enlarged cross-sectional view of part A of FIG. 4;

4B is an enlarged cross-sectional view and a bottom view of a portion B of FIG. 4;
4C is a perspective view from below of part B of FIG. 4;

5 is a cross-sectional view illustrating a stacked multi-chip package structure according to another embodiment of the present invention;

6 is a cross-sectional view illustrating a stacked multi-chip package structure according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

30: printed circuit board 30a: substrate pad

40: first wiring chip 41: first semiconductor chip

41a: first chip pad 43: first protective film (first dielectric layer)

45: second protective film (second dielectric layer) 47: the first rewiring

47a: first bonding pad 50: second wiring chip

51: second semiconductor chip 51a: second chip pad

53: first protective film (first dielectric layer) 55: second protective film (second dielectric layer)

57: second wiring 60: bonding wire

70: adhesive member 80: bump

90: encapsulant

s1: first groove, second region s2: second groove, first region

The present invention relates to a stacked multi-chip package and a method of manufacturing the same, and more particularly, to a stacked multi-chip package and a method for manufacturing the stacked multi-chip package to implement a chip between the heterogeneous or heterogeneous chips in one package.

In recent years, with the trend of light and short reduction of electronic devices, high-performance and high-density packaging of packaging technology for mounting semiconductor devices is required. Recently, multi-chip packages or chip-scale packages that package semiconductor device chips in a minimal space have become mainstream.

1 is a cross-sectional view illustrating a conventional stacked multi-chip package.

Referring to the drawings, the first rewiring chip 14 is attached to the upper surface of the printed circuit board 10 having the substrate pad 10a on which the solder mask is not applied via the adhesive member 11 and the first rewiring chip. A spacer 12 for securing the wire bonding space of the first rewiring chip 14 is attached to the spacer 14 via the adhesive member 11, and the spacer 12 is attached to the spacer 12 through the adhesive member 11. Two rewiring chips 15 are stacked.

The pad 14a of the first rewiring chip and the substrate pad 10a of the printed circuit board are connected to each other using a bonding wire 13 by using the space secured through the spacer 12. In addition, the pad 15a of the second rewiring chip and the substrate pad 10a of the printed circuit board are connected to each other by a bonding wire 13. Then, molding is performed with the encapsulant 18 to protect the bonding wire 13 and the stacked chips 14 and 15.

However, the conventional stacked multi-chip package structure has the following problems.

First, since the spacer 12 is used to secure a space required for the wire bonding connection of the first rewiring chip 14, the thickness of the entire package increases by the thickness of the spacer 12. In addition, as the second wiring chip 15 is wire-bonded and connected, the bonding wire 13 protrudes upward from the second wiring chip 15, and in the molding 18 process, the protruding portion must be completely covered. The package thickness increases beyond the bonding wire height.

Second, since the stacked chips 14 and 15 are connected to the bonding wires 13, the length of the bonding wires 13 becomes relatively long in the case of the second rewiring chip 15. In the case of stacking communication devices and the like, there is a possibility of electrical problems.

The present invention is to solve the above problems,

First, regardless of whether the chips stacked on the top and bottom are the same type or heterogeneous chips, and regardless of the size of the chips stacked on the top and bottom or the placement of the bonding pads, the chips can be stacked at a high density, making the package compact. Its purpose is to.

Secondly, the purpose of the present invention is to provide a package having improved electrical characteristics by performing flip chip connection having a short wiring length.

According to an aspect of the present invention, there is provided a stacked multi-chip package including a printed circuit board having a substrate pad; A first rewiring chip fixed on the printed circuit board, the first semiconductor chip having a first chip pad provided on an upper surface thereof, and a first rewiring chip electrically connected to the first chip pad; A second rearrangement chip connected to the flip chip through bumps on the first rearrangement chip; And bonding wires electrically connecting a first bonding pad provided on the first rewiring to a substrate pad of the printed circuit board, wherein a plurality of grooves are formed on a bottom surface of the second rewiring chip, and the grooves are formed. The trajectory of the bonding wire passes through the space.

In addition, the stacked multi-chip package according to another aspect of the present invention for achieving the above object, a printed circuit board having a substrate pad; A first rewiring chip fixed on the printed circuit board, the first semiconductor chip having a first chip pad provided on an upper surface thereof, and a first rewiring chip electrically connected to the first chip pad; A second rearrangement chip connected to the flip chip through bumps on the first rearrangement chip; And bonding wires electrically connecting the first bonding pads provided on the first rewiring lines to the substrate pads of the printed circuit board, wherein a step is formed upwardly at an edge of the bottom surface of the second rewiring chip. The trajectory of the bonding wire passes through the formed space.

On the other hand, a method of manufacturing a stacked multi-chip package according to another aspect of the present invention for achieving the above object, the first step of applying a first dielectric layer on the upper surface of the plurality of semiconductor chips constituting the wafer; Opening a region corresponding to a chip pad provided in each semiconductor chip and a first region corresponding to an upper edge portion of each semiconductor chip among the first dielectric layers; Forming a metal wiring pattern on the chip pad and the first dielectric layer; 4 steps of applying a second dielectric layer on the wafer after the three steps; Among the second dielectric layers, a second region corresponding to a bonding pad to be formed on the metal wiring, the first region connected to the second region, and a third region corresponding to a bumping pad to be formed on the metal wiring 5 steps to open the; 6 steps of cutting the wafers passed through the five steps and individualizing the plurality of redistribution chips; Fixing the individualized first rewiring chip on the printed circuit board; An eighth step of flip-chip connecting the second rewiring chip of the same type or different type to the first rewiring chip using bumps on the first rewiring chip; And wire bonding a bonding pad formed on the metal wiring of the first rewiring chip and the substrate pad of the printed circuit board between the seventh and eighth steps or after the eighth step. .

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of a stacked multi-chip package according to the present invention.

4 is a cross-sectional view illustrating a stacked multi-chip package structure according to an exemplary embodiment of the present invention, FIG. 4A is an enlarged cross-sectional view of part A of FIG. 4, and FIG. 4B is an enlarged cross-sectional view of part B of FIG. 4 and from below. This is a bottom view, and FIG. 4C is a perspective view of the B part of FIG. 4 viewed from the bottom.

Referring to the drawings, the stacked multi-chip package according to an embodiment of the present invention comprises a printed circuit board 30, the first wiring chip 40, the second wiring chip 50, the bonding wire 60. .

The first rewiring chip 40 includes a first semiconductor chip 41, a first passivation layer 43, a first rewiring 47, and a second passivation layer 45. The first chip pad 41a is arranged on the upper surface (active surface) of the first semiconductor chip 41, and the first passivation layer 43 is patterned to expose the first chip pad 41a on the first semiconductor chip 41. ) Is formed. The first rewiring 47 is patterned on the first passivation layer 43, and the first rewiring 47 is electrically connected to the exposed first chip pad 41a. A second passivation layer 45 is formed on the first passivation layer 43 and the first rewiring 47 so as to expose the first bonding pad 47a and the bumping pad 47b. Here, the first and second passivation layers 43 and 45 may be made of a dielectric material, and the first rewiring 47 may be made of a metal material.

The second rewiring chip 50 includes a second semiconductor chip 51, a first passivation layer 53, a second rewiring 57, and a second passivation layer 55, and bumps on the first rewiring chip 40. The flip chip is connected via 80. The second chip pad 51a is arranged on the bottom (active surface) of the second semiconductor chip 51, and the first passivation layer 53 is patterned to expose the second chip pad 51a on the second semiconductor chip 51. ) Is formed. A second rewiring 57 is patterned on the first passivation layer 53, and the second rewiring 57 is electrically connected to the exposed second chip pad 51a. The second passivation layer 55 patterned to expose the bumping pad 57b is formed on the first passivation layer 53 and the second rewiring 57. Here, the first and second passivation layers 53 and 55 may be made of a dielectric material, and the second rewiring 57 may be made of a metal material. The second rewiring chip 50 may have the same structure and size as the first rewiring chip 40. However, the content of the present invention is not limited thereto, and the first and second rewiring chips 40 and 50 may be the same type or different types of chips.

The first rewiring chip 40 and the second rewiring chip 50 are connected through the bump 80, and the bump 80 is the bumping pad 47b and the second provided on the first rewiring 47. The bumping pads 57b provided on the redistribution 57 are electrically connected to each other. The bump 80 may be a metal bump made of Au, Ni, Cu, or the like, or may be a solder bump. Since the bumping process is a conventional process, a description thereof will be omitted.

The substrate pad 30a is arranged on the upper surface of the printed circuit board 30, and the bottom surface (inactive surface) of the first rewiring chip 40 is fixed by the adhesive member 70. However, the content of the present invention is not limited thereto, and various methods of fixing the first rewiring chip 40 to the printed circuit board 30 may be applied.

The bonding wire 60 electrically connects the first bonding pad 47a provided on the first rewiring 47 of the first rewiring chip to the substrate pad 30a of the printed circuit board as a conductive wire. Since the bonding wire 60 is easily damaged by contact, the bonding wire 60 may be spaced apart from the first passivation layer 53, the second protection layer 55, and the second rewiring 57 of the second rewiring chip.

4B and 4C, a plurality of grooves s1 and s2 are formed on the bottom surface of the second rewiring chip 50, and as shown in FIGS. 4A and 4C, the grooves s1 and s2 may be formed. The trajectory of the bonding wire 60 passes through the formed space.

In more detail, the grooves s1 and s2 are formed in regions corresponding to the second bonding pads 57a provided on the second rewiring 57 electrically connected to the second chip pads 51a. It comprises a first groove (s1), and the second groove (s2) formed deeper to the edge in the outer direction in connection with the first groove (s1).

At this time, considering the trajectory of the bonding wire 60 in Figure 4a, as shown in Figure 4b, it is preferable that the shape of the first groove (s1) and the second groove (s2) is connected to the plane.

A second rewiring 57 or a second bonding pad 57a is exposed at a portion where the first groove s1 is formed. When the second bonding pad is present, the second bonding pad 57a is exposed, and when the second bonding pad is not present, the second rewiring 57 is exposed. In addition, a bottom surface of the second semiconductor chip 51 may be exposed at a portion where the second groove s2 is formed.

As a result, the spacers required for securing the wire bonding space in the conventional stacked multi-chip package become unnecessary, and the space between the stacked chips can be reduced, thereby miniaturizing the package.

In FIG. 4, although the second chip pad 51a, the second rearrangement 57, and the bump 80 are electrically connected to each other, the second chip pad 51a, the second rearrangement 57, and the bump 80 may be electrically connected. That is, the second chip pad 51a, the second rewiring 57, and the bump 80 may be electrically connected to each other, only the second rewiring 57 and the bump may be electrically connected, and the second chip pad may be electrically connected. It may also be electrically connected to a separate second rewiring. This is also the case for the first rewiring chip 40.

Referring to FIG. 4, the stacked multi-chip package encapsulates the first and second rewiring chips 40 and 50, the bonding wire 60, and the bump 80 while contacting at least one surface of the printed circuit board 30. The encapsulant 90 is further included.

In addition, the first rewiring chip 40 is fixed on the printed circuit board 30 by the adhesive member 70. However, the content of the present invention is not limited thereto.

Meanwhile, referring to FIG. 5, the stacked multi-chip package according to another embodiment of the present invention may include a third rewiring chip 140 in addition to the first and second rewiring chips 40 and 50. The fourth rearrangement chip 150 is further included.

The third rewiring chip 140 is fixed on the second rewiring chip 50, and has a third semiconductor chip having a third chip pad provided on an upper surface thereof, and a third rewiring electrically connected to the third chip pad. . The third rewiring chip 140 may be the same type or heterogeneous chip as the first, second or fourth rewiring chip. The fourth rewiring chip 150 is flip-chip connected to the third rewiring chip 140 through bumps. In addition, the bonding wire 160 electrically connects the third bonding pad provided on the third rewiring and the substrate pad formed on the printed circuit board 30. In this case, the bonding wires 160 electrically connected to the third rewiring chip may share the same substrate pads as the bonding wires 60 electrically connected to the first rewiring chip, or may be connected to a separate substrate pad. In addition, the third redistribution chip 140 may be fixed on the second rewiring chip 50 by an adhesive member.

5, a plurality of grooves are formed on the bottom surface of the fourth rewiring chip 150, and the trajectory of the bonding wire 160 passes through the space in which the grooves are formed. Since the contents thereof are the same as those described with reference to FIGS. 4A and 4B, detailed description thereof will be omitted.

Meanwhile, referring to FIG. 6, the stacked multi-chip package according to another embodiment of the present invention may include a fifth rewiring chip in addition to the first and second rewiring chips 40 and 50 in the embodiment shown in FIG. 4. 120 further includes.

The fifth rewiring chip 120 is positioned between the printed circuit board 30 and the first rewiring chip 40. The fifth rewiring chip 120 is electrically connected to the fifth semiconductor chip provided with a fifth chip pad on its lower surface and the fifth chip pad. And a fifth bumping wiring and a chip bumping pad provided on the fifth wiring, and the chip bumping pad is electrically connected to the substrate bumping pad provided on the printed circuit board 30 through bumps. In addition, the first rewiring chip 40 may be fixed on the fifth rewiring chip 120 by an adhesive member. In addition, an underfill material 200 is filled between the fifth rewiring chip 120 and the printed circuit board 30.

On the other hand, a stacked multi-chip package according to another aspect of the present invention, a printed circuit board having a substrate pad; A first rewiring chip fixed on the printed circuit board, the first semiconductor chip having a first chip pad provided on an upper surface thereof, and a first rewiring chip electrically connected to the first chip pad; A second rearrangement chip connected to the flip chip through bumps on the first rearrangement chip; And bonding wires electrically connecting the first bonding pads provided on the first rewiring lines to the substrate pads of the printed circuit board, wherein a step is formed upwardly at an edge of the bottom surface of the second rewiring chip. The trajectory of the bonding wire passes through the formed space.

Unlike the previous embodiments, a step is formed upward in the bottom of the second rewiring chip instead of a plurality of grooves. Although the drawings for this embodiment are not separately illustrated, reference may be made to FIGS. 4 and 4A.

The second rewiring chip may include a second semiconductor chip provided with a second chip pad, a first passivation layer formed on the second semiconductor chip and selectively exposing the second chip pad, the second chip pad and the second chip. The second protective wiring patterned on the first protective film and the second protective film formed on the second wiring may be included.

In this case, the second rewiring chip may have the same structure and size as the first rewiring chip. In addition, a first step may be formed to expose the second bonding pad provided on the second rewiring electrically connected to the second chip pad, and a second step may be formed to expose the second semiconductor chip.

Hereinafter, a method of manufacturing a stacked multi-chip package according to an embodiment of the present invention will be described step by step with reference to FIGS. 2A to 2F and FIGS. 3 and 4.

FIG. 2A shows a one-step process of applying a photo-sensitive first dielectric layer 43 to the upper surface of the plurality of semiconductor chips 41 constituting the wafer, that is, the entire surface of the wafer. A chip pad 41a is formed on the upper surface of each semiconductor chip 41.

FIG. 2B shows two regions of the first dielectric layer 43 that open the region corresponding to the chip pad 41a provided in each semiconductor chip and the first region s2 corresponding to the top edge of each semiconductor chip 41. Represents a step process. Here, the region corresponding to the chip pad 41a is a space for contact between the metal wiring to be patterned in the subsequent process and the chip pad. In addition, the first region s2 is a space for securing a wire bonding space in a subsequent process. As a process of opening the regions, a general photo-lithograpy process may be used.

FIG. 2C illustrates a three-step process of forming a metal wiring 47 on the chip pad 41a and the first dielectric layer 43. At this time, it is preferable that the metal wiring 47 is not formed in the first region s2. As the metal wire forming process, a general sputtering method, chemical vapor deposition method, evaporation method or plating method may be used.

FIG. 2D shows a four-step process of applying a photosensitive second dielectric layer 45 to the entire surface of the wafer after the three steps. It is preferable to use the same material as the material forming the first dielectric layer 43 as the material forming the second dielectric layer 45.

FIG. 2E shows a second region s1 corresponding to a bonding pad to be formed on the metal wiring 47 among the second dielectric layers 45, and the first region s2 connected to the second region s1, and 5 shows a step of opening the third region corresponding to the bumping pad to be formed on the metal wiring. Here, the second region s1 is a space for securing the wire bonding space in a subsequent process. As a process of opening the regions, a general photo-lithograpy process may be used.

2F illustrates a process of forming a bump bump pad 47b in the third region opened in step 5 and then forming a metal bump 80 on the bump pad. As the bumping process, a general electroplating method, a ball attach method, or a screen printing method may be used.

Although not shown, there is a six-step process of cutting the wafers subjected to the five-step or the bumping process and individualizing the plurality of redistribution chips. By performing the manufacturing process on the same wafer at the same time before the six steps, manufacturing time and manufacturing cost can be greatly reduced. This is also known as wafer level package technology.

3 shows a seven-step process of fixing the individualized first rewiring chip 40 on the printed circuit board 30 without the bumping process, and then on the metallization 47 of the first rewiring chip 40. A step of wire bonding the formed bonding pad 47a and the substrate pad 30a of the printed circuit board is shown. The wire bonding process may be performed after the eight step process described below. In addition, in the seven-step process, the first rewiring chip 40 may be fixed on the printed circuit board 30 by the adhesive member 70.

FIG. 4 illustrates a flip chip connecting the second rewiring chip 50, which is the same type or heterogeneous as the first rewiring chip 40, after the bumping process on the first rewiring chip 40, using the bump 80. Represents a step process. In the case where the first and second rewiring chips 40 and 50 have the same structure and size, they are separated from the same wafer as the first and second rewiring chips 40 by the process shown in FIGS. 2A to 2E. Redistribution chips can also be used. Meanwhile, the encapsulant 90 is encapsulated using the encapsulant 90 to protect the first rewiring chip 40, the second rewiring chip 50, and the bonding wire 60 stacked on the printed circuit board 30.

When the wire bonding step is performed between the seventh and eighth steps, it is preferable to align the wire trajectory through the first and second regions s2 and s1 so that the trace of the wire may pass.

According to the present invention, by stacking chips of the same type or different types in parallel with the flip chip connection and the wire bonding connection method using the rewiring technology used in the existing wafer level package technology, the conventional spacer and the wire bonding method are used. Compared to multichip packages, many chips can be mounted at a thinner thickness, and flip-chip connections with short wiring lengths are provided for electrically important pads, effectively improving electrical characteristics.

Although the present invention has been described with reference to the illustrated embodiments, it is merely exemplary, and the present invention may encompass various modifications and equivalent other embodiments that can be made by those skilled in the art. Will understand.

Claims (22)

A printed circuit board having a substrate pad; A first rewiring chip fixed on the printed circuit board, the first semiconductor chip having a first chip pad provided on an upper surface thereof, and a first rewiring chip electrically connected to the first chip pad; A second rearrangement chip connected to the flip chip through bumps on the first rearrangement chip; And In the stacked multi-chip package comprising a bonding wire for electrically connecting the first bonding pad provided on the first rewiring and the substrate pad of the printed circuit board, A plurality of grooves are formed on the bottom surface of the second rewiring chip, and the locus of the bonding wire passes through the space in which the grooves are formed. The method of claim 1, The second rewiring chip may include a second semiconductor chip provided with a second chip pad, a first passivation layer formed on the second semiconductor chip and selectively exposing the second chip pad, the second chip pad and the second chip. And a second passivation layer formed on the first passivation layer, and a second passivation layer formed on the second passivation layer. The method of claim 2, And the second rewiring chip has the same structure and size as the first rewiring chip. The method of claim 2, The groove may include a first groove formed in a region corresponding to a second bonding pad provided on a second rewiring wire electrically connected to the second chip pad, and a first groove deeper connected to the first groove to an edge in an outer direction. Stacked multi-chip package, characterized in that consisting of two grooves. The method of claim 4, wherein The multilayered multi-chip package according to claim 1, wherein the second rewiring or the second bonding pad is exposed at a portion where the first groove is formed. The method of claim 4, wherein Stacked multi-chip package, characterized in that the second semiconductor chip is exposed in the portion where the second groove is formed. The method of claim 4, wherein Stacked multi-chip package, characterized in that the shape of the first groove is connected to the second groove is flat in shape. The method of claim 2, The bonding wire is a stacked multi-chip package, characterized in that spaced apart from the first protective film, the second protective film and the second rewiring of the second rewiring chip. The method of claim 1, The first rewiring chip and the second rewiring chip is a stacked multi-chip package, characterized in that the same type or heterogeneous chip. The method of claim 1, And a sealing material encapsulating the first and second rewiring chips, the bonding wires, and the bumps while in contact with at least one surface of the printed circuit board. The method of claim 1, And the first rewiring chip is fixed on the printed circuit board by an adhesive member. The method according to claim 1 or 11, wherein A third rewiring chip fixed on the second rewiring chip, the third semiconductor chip having a third chip pad provided on an upper surface thereof, and a third rewiring chip electrically connected to the third chip pad; A fourth rewiring chip connected to the flip chip via bumps on the third rewiring chip; And And a bonding wire configured to electrically connect the third bonding pad provided on the third rewiring with the substrate pad formed on the printed circuit board or a separate substrate pad. A plurality of grooves are formed on the bottom surface of the fourth rearrangement chip, and the trajectory of the bonding wire passes through the space in which the grooves are formed. The method of claim 12, And the third rewiring chip is fixed on the second rewiring chip by an adhesive member. The method of claim 1, Located between the printed circuit board and the first wiring chip, A fifth semiconductor chip having a fifth chip pad provided on a lower surface thereof, a fifth rewiring electrically connected to the fifth chip pad, and a chip bumping pad provided on the fifth rewiring; The chip bumping pad further comprises a fifth rewiring chip electrically connected to the substrate bumping pad provided on the printed circuit board through the bump. The method of claim 14, The multi-layer package of claim 5, wherein an underfill material is filled between the fifth rewiring chip and the printed circuit board. The method of claim 14, And the first rewiring chip is fixed on the fifth rewiring chip by an adhesive member. A printed circuit board having a substrate pad; A first rewiring chip fixed on the printed circuit board, the first semiconductor chip having a first chip pad provided on an upper surface thereof, and a first rewiring chip electrically connected to the first chip pad; A second rearrangement chip connected to the flip chip through bumps on the first rearrangement chip; And In the stacked multi-chip package comprising a bonding wire for electrically connecting the first bonding pad provided on the first rewiring and the substrate pad of the printed circuit board, And a step is formed upwardly at an edge of a bottom surface of the second rewiring chip, and a trajectory of the bonding wire passes through a space in which the step is formed. The method of claim 17, The second rewiring chip may include a second semiconductor chip provided with a second chip pad, a first passivation layer formed on the second semiconductor chip and selectively exposing the second chip pad, the second chip pad and the second chip. And a second passivation layer formed on the first passivation layer, and a second passivation layer formed on the second passivation layer. The method of claim 18, The second rewiring chip is a stacked multi-chip package, characterized in that having the same structure and size as the first rewiring chip. The method of claim 18, A multilayered multi-chip, wherein a first step is formed to expose a second bonding pad provided on a second rewiring wire electrically connected to the second chip pad, and a second step is formed to expose the second semiconductor chip. package. Applying a first dielectric layer to a plurality of semiconductor chips forming a wafer; Opening a region corresponding to a chip pad provided in each semiconductor chip and a first region corresponding to an upper edge portion of each semiconductor chip among the first dielectric layers; Forming a metal wiring pattern on the chip pad and the first dielectric layer; 4 steps of applying a second dielectric layer on the wafer after the three steps; Among the second dielectric layers, a second region corresponding to a bonding pad to be formed on the metal wiring, the first region connected to the second region, and a third region corresponding to a bumping pad to be formed on the metal wiring 5 steps to open the; 6 steps of cutting the wafers passed through the five steps and individualizing the plurality of redistribution chips; Fixing the individualized first rewiring chip on the printed circuit board; An eighth step of flip-chip connecting the second rewiring chip of the same type or different type to the first rewiring chip using bumps on the first rewiring chip; And Between the step 7 and the step 8 or after the step 8, a step of wire bonding a bonding pad formed on the metal wiring of the first rewiring chip and the substrate pad of the printed circuit board. Method of manufacturing multichip package. The method of claim 21, When the wire bonding step is performed between the seventh and eighth steps, an alignment of the wires may pass through the first and second regions so as to pass through the first and second regions. Manufacturing method.

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