KR100794916B1 - Design Verification Apparatus For Incremental Design Verification Using Mixed Emulation and Simulation, and Design Verification Method Using the Same - Google Patents

Abstract

The present invention relates to a design verification apparatus for design verification of a digital circuit of more than millions of gates designed and a design verification method using the same.

In the present invention, the input / output / input / output probe is possible by adding a probe additional circuit which enables the design verification system software of the present invention to be performed on an arbitrary server computer to enable the input / output / input / output probe to the design verification target circuit. Allows you to create extended circuits in an automated manner. In addition, the design verification interface module of the present invention connects the server board computer and the hardware board in which the extended circuit capable of input / output / input / output probe is implemented as one or more programmable elements and is mounted together with other hardware components. The design verification subject is applied to the server computer and the at least one programmable device by performing an input / output / input / output probe of the at least one programmable device on the hardware board at a specific time point or under certain conditions while controlling the performance of the hardware board. Allows quick exchange of performance results information for circuits or partial circuits. In addition, by using the server computer and any simulation server computer that simulates the entire circuit or only partial circuits of the design verification target, emulation and simulation are alternately performed one or more times in an automatic manner quickly and gradually through design verification. It is possible to quickly eliminate one or more design errors present in the.

Description

Design Verification Apparatus For Incremental Design Verification Using Mixed Emulation and Simulation, and Design Verification Method Using the Same}

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 schematically shows a design verification apparatus of the present invention.

Fig. 2 is a diagram schematically showing an example in which an output probe addition circuit is added to a design verification target circuit.

3 is a diagram schematically showing an example in which an input probe addition circuit is added to a design verification target circuit;

FIG. 4A is a diagram schematically showing a situation in which the entire design verification target circuit is performed by simulation; FIG.

4 (b) is a diagram schematically showing a situation in which a part of a design verification target circuit is performed by simulation while the other part is performed by emulation;

<Explanation of symbols for main parts of drawing>

12: RFPD 20: Computer for Server

26: design verification interface module 27: interface module

28: interface cable                 

30: Component other than one or more RFPD in which the design verification target circuit on any prototyping board is implemented.

32: Design verification system software 34: Arbitrary simulator

44: random prototyping board 74: multiplexer

73: Single Input Flip-Flop with Asynchronous Set / Reset and Synchronous Enable

75: dual input D flip flop 76: single input D flip flop

77: dual input flip-flop with asynchronous set and asynchronous reset

78: Single Input Flip-Flop with Asynchronous Set and Asynchronous Reset

79: Tri-state buffer

86: output probe target signal line

87: flip-flops forming a shift register of an additional circuit for the output probe

88: flip-flops forming the shift register of the additional circuit for the input probe

90: the entire circuit of the design verification target circuit to be simulated

92: part of the design verification target circuit simulated in the entire design verification target circuit

94: the rest of the design verification target circuit emulated throughout the design verification target circuit

The present invention relates to a technology for design verification of a multi-million-gate or more digital circuit designed. The present invention relates to a real hardware implementation of a multi-million-gate or more digital circuit designed as a programmable chip or a custom semiconductor chip, using a combination of emulation and simulation techniques. The present invention relates to a design verification method for quickly eliminating one or more design errors present in the multi-million gate class or more digital circuit, and a design verification apparatus for the same.

With the recent rapid development of integrated circuit design and semiconductor process technology, the scale of digital circuit design has grown from at least millions of gates to tens of millions of gates, and its composition has become extremely complicated. As the trend is expanding, more than 100 million gate designs are expected in the near future. However, competition in the market is getting fiercer, and therefore, a good product must be developed in a short time, and there is an increasing need for an effective method for efficiently designing and verifying a circuit designed in an automated manner in a short time.

Until now, the simulator, which is a software approach, has been mainly used to design and verify the designed digital circuit. However, the simulator has to execute the software code composed of the sequential instruction sequences that model the circuit to be designed and verified on the computer sequentially. Design verification times for designs beyond millions of gates are extremely long and unprecedented, and there is a limit to integrating with other surrounding hardware environments to verify the entire system (called ICE, In-Circuit Emulation). In addition, in order to perform design verification using simulation, an input pattern sequence for design verification should be generated in the design verification target circuit. However, as the size of the design verification circuit increases, the size of the input pattern sequence increases in proportion to the exponential function, and in most cases, a large amount of time and cost must be invested.

On the other hand, a hardware emulation-based design verification method using the designed circuit as a real chip is to verify the digital circuit in a situation where all the components of the designed digital circuit are actually operated in parallel on the implemented chip. Compared to other hardware environments, it is possible to verify the design up to 1 million times faster than the integrated environment. In addition, when design verification is performed by integrating with other surrounding hardware environments using the ICE method, since the actual input pattern sequence is supplied to the design verification target circuit in the surrounding hardware environment, the process of manually generating it may be omitted. However, emulation has the disadvantage that debugging is much more inconvenient than simulation. The main reason is that the visibility of the logic value of numerous signal lines in the design verification circuit implemented in the programmable chip or the custom semiconductor chip is This is because visibility falls far short of the simulation. In addition, if emulation using programmable chips or custom semiconductor chips is used, the execution itself can be performed at extremely high speed. However, if one or more design errors exist in the circuit to be verified, they can be corrected. In this case, it is necessary to reprogram the programmable chip or to manufacture the custom semiconductor chip again, which requires a very long time and sometimes a high cost. Many design errors exist, and these design errors are usually corrected from several times to tens of times. Therefore, design verification using emulation is not desirable in such a situation.

The patent application "Rapid input / output probe device and input / output probe method using the same and a mixed emulation / simulation method based on the same" (Patent Application No. 10-2000-0034628) is a reusable field programmable device (programmable chips) Devices (hereinafter referred to as "RFPD"), how to effectively perform design validation on digital systems using emulation and simulation using custom semiconductor devices such as application specific integrated circuits (ASICs) or application specific standard products (ASSPs) Presenting.

However, in addition to the above-listed patents, any other patents do not provide an effective method using emulation and simulation for the design of at least the millions of scales mentioned above. In other words, if the design subject to design verification is millions or more, the execution time of the simulation is extremely large due to the size of the circuit, even if the time required to perform the simulation required to obtain signal visibility in the emulation and simulation mixed verification process is short. If the size of is extremely large, the simulation itself may not be possible at all. In addition, in order to perform a combination of emulation and simulation in an in-circuit environment, at least millions of gate-class design verifications are performed by software modeling of other peripheral hardware environments in the in-circuit process. It is called a test bench, so it is necessary to generate a correct input pattern sequence through simulation and apply it to a software modeled design under test (DUT). However, it is extremely difficult to correctly model intricately different complex hardware environments in such an in-circuit, so this modeling need is not only a simulation of design verification, but also a combination of emulation and simulation in an in-circuit environment. The application of one design verification method is also very difficult. In addition, another problem with the design verification method using the emulation and simulation is that if the design errors found during the design verification are corrected, the re-programmable re-usable programming elements that are extremely time-consuming are re-programmed or the time is extremely long. They continue to have the problem of remanufacturing custom semiconductor devices that are time-consuming and very expensive.

In addition, the existing incremental prototyping technique or co-modeling technique using emulation and simulation is an emulation block (called an emulation block) and a simulation part (design emulation block). In the process of dividing into two parts of the simulation block, the input, output, and input / output ports located in the emulated circuit part (these are input, output, and input / output based on the partial circuit of the circuit to be emulated). In other words, internal signal lines may be physically connected to the pins of a programmable device or a custom semiconductor chip, which is an implementation medium, and as a result, it is necessary to change an emulation block or a simulation block. Extremely limited (E.g., to emulate blocks deep inside the design-verification circuitry, the input, output, and input / output ports of these blocks must all be physically connected to the pins of a programmable device or custom semiconductor chip that is the implementation medium. If these blocks are changed or newly added, the time for this is greatly increased.) The design verification using the spatial mixture of emulation and simulation is greatly reduced.

Accordingly, an object of the present invention is to design through a gradual design verification using the input and output probe method in the design verification mixed with the emulation and simulation of a large-scale digital system implemented in hardware using one or more RFPD for ultra-scale design verification The present invention provides a design verification method using a design verification apparatus that can eliminate a large number of design errors in a verification target circuit with minimal time and cost.

In order to achieve the above object, the design verification apparatus according to the present invention provides a design verification system software and a design verification interface module 26. The design verification interface module 26 may be composed of an interface module 27 and an interface cable 28. The design verification system software runs on a server computer, which has any simulator (e.g., an HDL simulator, a logic simulator, or a cycle-based simulator) or software that can take the place of a simulator. The design verification interface module is one or more hardware boards or prototyping hardware platforms or emulation hardware platforms that are equipped with server computers with design verification system software and one or more RFPDs implemented with millions of gate-class digital circuits designed. Another important feature of the design verification interface module is the system clock needed for the I / O probe to the circuit under test and the one or more users generated from the system clock. Clock, probe clock, operation mode control signal, probe mode control signal, probe memory read signal, etc. are generated under the control of design verification system software and supplied to any prototyping board or PCB as needed. Prototyping and controls the board or any PCB operation. To this end, the design verification interface module may have its own FPGA or CPLD, a microprocessor or microcontroller, or a dedicated ASIC / ASSP chip. Alternatively, the design verification interface module may be implemented together in an FPGA or CPLD in which a design verification target circuit or a target HDL code is implemented. 1 is a diagram schematically showing a design verification apparatus according to the present invention composed of a design verification system software and a design verification interface module operating in a server computer. Specifically, the design verification interface module 26 may be mounted in a PCI slot or connected to a secondary secondary system bus (such as a SUN workstation) to be connected to the Peripheral Computer Interface (PCI) bus of the server computer. It is common to connect to the S-bus, but if high speed is required, it may be connected to the main bus, which is the primary system bus of the server computer. Universal Serial Bus), parallel port or serial pod can be connected to it, and any server computer, any prototyping board or any PCB is connected.

The design verification system software, via the design verification interface module, can be used to design part or all of the millions of gate-level design verification circuits implemented on any prototyping board or PCB at any time or situation desired by the user during the design verification process. The complete state information or the partial state information about the state can be read from the prototyping board at any time point or situation or vice versa. Here, state information refers to the value of the memory elements (flip-flop or latch) of the digital circuit and the contents of the memory (RAM or ROM). Complete state information refers to the values and all the values of all the memory elements of the circuit for design verification. The partial state information refers to the value of the memory elements of the portion of the design verification target circuit and / or the contents of the portion of the memory. In addition, the memory device is different from the memory, and the memory device means flip-flop or latch, and the memory refers to all kinds of random access memory (RAM), PROM, EPROM such as SRAM, DRAM, SDRAM, Rambus DRAM, etc. It defines as all kinds of ROM (Read Only Memory) such as EEPROM, Flash Memory. On the other hand, the logic information refers to a binary logic sequence appearing on any one or more signal lines existing in the digital circuit. The logic information is different from the state information. It is possible to include the output value or input value of the combinational logic gate without limiting the content of.

The design verification system software includes a probe circuit synthesizer that converts input probes or output probes or input / output probes to specific signal lines present in the design verification circuit in an automated manner, such as a probe circuit synthesizer. By adding the additional circuit to the design verification target circuit, a completed circuit (which is called an extended design verification target circuit) is generated in an automated manner. The role of the probe additional circuit included in the extended design verification target circuit is that in the case of the output probe, the circuit part formed by adding the additional circuit has a shift register structure, so that the shifting operation synchronized with the probe clock is shifted immediately before the shifting operation. The logic values of the registers have the logic values of the signal lines in the circuit to be output probe.In the case of the input probe, the circuit part formed by adding an additional circuit has a shift register structure to perform the shifting operation. By using a specific logic value can be displayed after the shifting operation is completed on the signal lines in the circuit that is the input probe target, in the case of input and output probes, each of the input probe and the output probe can be performed at a desired time point, When normal operation is required, the additional circuit Even if it is added, the functional logical behavior of the design verification target circuit can be operated as a circuit that is not deformed. Alternatively, when the design verification subject is dictated by a hardware oral language (hereinafter referred to as HDL) code, the HDL code representing the behavior of the probe additional circuit is added to the HDL code to be verified by design. In the case of the output probe, the HDL part formed by adding the additional HDL code expresses the shift register behavior, so that the shifting operation synchronized with the probe clock is applied to the register HDL code in the HDL code immediately before the shifting operation. The signal values of the signal line have the logic values of the signal lines of the HDL code to be the output probe target.In the case of the input probe, the HDL code part formed by adding the additional HDL code has a shift register structure and is synchronized with the probe clock. The shifting operation is carried out. After the shifting operation is completed on the signal lines in the HDL code, which are the output probe targets of the HDL code, specific logic values can be displayed.In the case of the input / output probe, each of the input probe and the output probe can be performed at a desired time point. When normal operation is needed, even if an additional circuit is added, the functional logical behavior of the design verification HDL code is not modified.

In addition, when the signal lines to be probed are the outputs of the memory device, the role of the probe additional circuit included in the extended design verification target circuit is that in the case of the output probe, the circuit portion formed by adding the additional circuit has a shift register structure. The shifting operation synchronized with the probe clock has the logic values of the shift register immediately before the shifting operation with the logic values of all or a part of the memory elements in the circuit to be output probe, and in the case of the input probe, an additional circuit is added. The circuit part to be formed has a shift register structure to perform a shifting operation. By using such a shifting operation, a synchronous set or reset of all or a part of memory elements in a circuit that is an input probe object is performed. ) Operation, or following an asynchronous set or reset operation A synchronous disable operation following a synchronous set or reset or asynchronous set or reset operation makes a logic value of a memory element to be an input probe as an input probe value, and in the case of an input / output probe, Each of the output probes can be performed at a desired point in time, and when normal operation is required, it is possible to operate as a circuit that does not change the functional logical behavior of the circuit to be verified by design even if an additional circuit is added. . Alternatively, when the design verification subject is dictated by the HDL code, the HDL additional code representing the behavior of the probe additional circuit is added to the design verification HDL code, and the completed HDL code is formed by adding the additional HDL code in the case of the output probe. Since the HDL part expresses the shift register behavior, the shifting operation synchronized with the probe clock is performed. The HDL code expressing the shift register behavior immediately before the shifting operation indicates that the signal values of the register HDL code signal lines are output probes. All or part of the output signal values of the device and all the unidirectional inputs and all bidirectional input and output signals of the specific part HDL code of the design verification target circuit to be simulated, and in the case of the input probe is formed by adding additional HDL code The HDL code part has a shift register structure A shifting operation synchronized to the needle clock, and using this shifting operation, a synchronous set or reset of signals of the HDL code representing the memory element behavior of the HDL code that is the input probe target. reset operation or asynchronous set or reset operation followed by synchronous set or reset or asynchronous set or reset operation followed by synchronous disable operation. The input and output probes can be performed at desired times in the case of input / output probes, and when normal operation is required, the behavior of the design verification HDL code will not be modified even if additional probe circuits are added. do.

The specific implementation method of the probe additional circuit for the above-described probe is a previously filed "quick input and output probe device, input and output probe method using the same and mixed emulation / simulation method based on the same" (PCT application number: PCT / KR01 / Since much of 01092 is already mentioned in detail, this patent will refer to only a few cases of additional ones.

FIG. 2 is a diagram schematically illustrating an example of an implementation of a probe additional circuit that performs an output probe on arbitrary signal lines existing in a circuit to be verified for design.

FIG. 3 is a diagram schematically illustrating an example of an implementation of a probe additional circuit that performs an input probe on an arbitrary signal line that is an input or an output of a combination circuit existing in a design verification target circuit; Since the input probe should be performed on the signal lines other than the output of the device, the circuit portion formed by adding the additional circuit has a shift register structure to perform the shifting operation, and the input probe data is converted into the shift register structure using the shifting operation. After being stored in the flip-flops, the select input of the multiplexer 74 is controlled so that the input policy data appears on each of the corresponding signal lines.

Additionally, the design verification target circuit includes memory such as RAM or ROM, and these memories are also provided on-chip memory (specifically, for example, distributed RAM or block RAM of Xilinx FPGA). In the case of using an embedded array block of Altera FPGA, a memory read / write additional circuit is additionally included in the IOP probe additional circuit. The memory read / write additional circuit is controlled by the design verification system software and in the output probe mode, the output probe is read out by reading all the contents of the memory or the specific region in the design verification target circuit implemented in the RFPD in a predetermined order. It can be read through the interface module and the interface cable through the design verification system software in an automated manner.In the input probe mode, the data of the design verification system software is transferred to the RFPD input probe through the interface cable and the interface module. Through the RFPD, the write operation is performed in a predetermined order in all regions or specific regions of the writable memory in the design verification target circuit implemented in the RFPD. A specific example of the implementation of such a memory read / write additional circuit is already described in the "quick input / output probe apparatus and input / output probe method using the same and a mixed emulation / simulation method based on the same" (PCT application number: PCT / KR01 / 01092). Since it is mentioned in detail, it will be omitted in the present patent.

In the present invention, the output probe line and the input probe line may exist as separate independent unidirectional probes, or may exist as bidirectional probes in which the output probes and the input probes are combined. In addition, the probe clock used in the present invention may generate and use a clock separate from the user clocks used in the design verification target circuit from the system clock, or may use one of the user clocks (for example, the fastest clock).

The design verification system software includes a step of manually inputting or automatically determining, on the tamper signal lines and memory present in the design verification target circuit, or on the tamper signals and memory block present in the design verification HDL code, from the designer. In order to implement the design verification circuit in one or more RFPDs mounted on an arbitrary prototyping board or an arbitrary PCB, logic at a specific time zone or at a specific time in a signal line on an output probe or a memory area to be read is generated. Allows values to appear sequentially on the output probe only for a certain period of time, and can be used by any prototyping board or arbitrary to ensure that the signal lines on the input probe or the memory area to be written have logic values applied to the input probe at specific times. Design verification target assigned to one or more RFPD mounted on PCB The furnace adding a probe for adding circuit further includes the step of generating the extended design verification circuit. In addition, for the signal lines on the output probe and the memory area to be read, the logic values and the contents of the memory at specific time points on the signal lines on the output probe are displayed on the output probe of the corresponding RFPD using the probe additional circuit. The value displayed on the line is transmitted to the server computer through the design verification interface module. For the signal lines on the input probe and the memory area to be written, the input probe data is generated from the status information obtained from the server computer. The signal line on the input probe of the RFPD is applied while synchronizing with the probe clock only, or synchronized with the probe clock, and the probe mode is properly changed between the input probe mode and the output probe mode through the probe mode control signal line. Field of input signal lines And setting the status information of the design verification target circuit implemented in the RFPD to be the same as the status information obtained from the server computer by having the logic value and the contents of the write target memory area have the logic values transmitted through the input probe line.

By using the above-described design verification apparatus and design verification method, any prototyping board or any PCB equipped with one or more semiconductor chips in which an extended design verification target circuit in which a probe additional circuit is added to the design verification target circuit is implemented. And arbitrary simulators can be used to perform design verification by temporally or spatially mixing emulation and simulation. In other words, such emulation and simulation mixed verification may be performed by the design verification system software. The design verification system software may manually designate the signal signals and memory blocks present in the circuit to be verified, or the signals and memory blocks present in the design verification HDL code. The signal lines on the output probes present in the entire design verification circuit or part of the design verification circuit implemented in one or more RFPDs mounted on any prototyping board or any PCB. Alternatively, logic values at a specific time zone or at a specific time in the memory area to be read are sequentially displayed on the output probe only for a certain time, and signal lines or input memory areas on the input probe are specified to the input probe. To have logical values applied to the time zone The entire design verification circuit or the extended design by adding the probe additional circuit to the entire design verification circuit or part of the design verification circuit which is allocated to one or more RFPDs mounted on a prototyping board or an arbitrary PCB Generating a portion of the circuit to be verified. In addition, for the signal lines on the output probe and the memory area to be read, the logic values and the contents of the memory at specific time points on the signal lines on the output probe are displayed on the output probe of the corresponding RFPD using the probe additional circuit. The value displayed on the line is transmitted to the server computer through the design verification interface module so that the simulator can calculate the current status information or the logic information of the current probe signal lines of the entire design verification circuit or the part of the design verification circuit. For the signal lines on the input probe and the memory area to be written, the input probe data is generated from the state information or the logic value information obtained through the simulation on the server computer, and then the input probe data is generated through the interface module and the interface cable. Input probe of corresponding RFPD Apply to the target signal lines while synchronizing only with the probe clock, or by synchronizing with the probe clock and changing the probe mode between the input probe mode and the output probe mode through the probe mode control signal line. By making the logic value and the contents of the memory area to be written have the logic values transmitted through the input probe line, the state information or logic value information of the entire design verification circuit or part of the design verification circuit implemented in the RFPD is stored for a certain period of time in the simulator. And setting the same as the state information or logic value information generated through the simulation. The exchange of state information or logic value information between any one or more RFPDs mounted on any prototyping board or any PCB and any simulator may be performed by using a foreign language interface (FLI) or a programming language interface (PLI) provided in the simulator. This can be done at the API (Application Program Interface) level, with minimal overhead.

As described above, in order to perform mixed verification in an automated manner between emulation and simulation by using the design verification apparatus and the design verification method of the present invention, performance switching between emulation and simulation should be automatically performed. The execution mode switching can be performed every clock or when a specific condition is satisfied (for example, when a specific value is written twice to a specific register in the circuit). This is called a switching condition. The execution mode switching condition may be two or more times temporally related to the entire verification process. In such a case, the emulation mode may be changed when the condition is satisfied in the order of the condition set first from the time set later. Execution mode switching from simulation or simulation to logic emulation occurs. To do this, it is necessary to store the execution mode switching conditions in a queue, which is called the execution mode switching condition queue, and maintains it in the form of a data structure in the design verification system software.

Through this I / O probe, it is possible to alternately perform one or more simulations on the server computer and emulation using an arbitrary prototyping board or an arbitrary PCB. In particular, when there is no combinatorial feedback loop in the circuit under design verification, the output probe signal lines are the output lines of all memory elements (flip-flops or latches) present in the circuit under design verification (output at this time). The values of all probed memory elements are referred to as complete state information.) Even when the output probe target signal lines are output lines of partial memory elements present in the design verification target circuit, one or more clock cycles are output from the output line values of these partial memory elements. If it is possible to determine all the values of the remaining memory devices (the values of the output probed partial memory devices at this time are called complete partial state information), the logic values of the output probed signal lines are transferred to the simulator of the server computer. Following the emulation, the simulation can proceed continuously. If more than one combinational closed circuit is included in the design verification target circuit, each of the combinational signal lines present in the combined closed circuit that can cut the closed circuit in each combination closed circuit is also used as the output probe target signal line. Should be included in If the above emulation and simulation can be performed alternately one or more times, there are numerous advantages in performing design verification using an arbitrary prototyping board or an arbitrary PCB.

First, design validation in today's system on a chip (SoC) environment requires a great deal of time and money to create test benches for simulation. Typically, it is very difficult for a designer to create a test bench by hand, so that the code that implements the test bench takes up to 80% of the overall design code size until the design project is completed. In addition, it is very difficult for designers to create their own test benches in all SoC designs, considering all the many cases in which the actual designed chip is actually operated in a real environment. In contrast, the ICE-based design verification method is capable of prototyping the circuit under design verification and interworking with the real environment, so that there is no need to create a test bench, and actual situations are produced by actual operation in the real environment. As a result, it is possible to perform much more reliable verification than using a test bench. For this design verification by prototyping, the circuit to be verified must be implemented with at least one programmable device. In general, however, there are many design errors, so in the early stages of design validation, which must correct these errors from as few as many to several tens of times, the circuits for design verification are designed so that design errors can be corrected for prototyping. The chip implemented must also be modified, which is very time-consuming and expensive and cannot be used in the early stages of design. In other words, even when using the lowest cost programmable device (eg FPGA), re-implementation of design-verified circuits with corrected design errors can be re-implemented from a few hours to several tens of hours. The compilation process is necessary, which greatly increases the overall design verification time.

However, by using the design verification method proposed in this patent, it is possible to effectively solve such problems and perform design verification with minimum effort in a short time. That is, as already mentioned, emulation and simulation using an extended design verification circuit or an extended design verification circuit that adds a probe additional circuit or a probe additional HDL code to the design verification circuit or the design verification HDL code. Time and space in a systematic and automated way, when design validation is performed quickly using a mix of online and offline methods, it is not necessary to manually create a test bench from the early stage of the design. It is possible to use the results as they are, allowing for much more reliable design verification with much less time and cost. In addition, as the design verification progresses, instead of using simulations that take a long time to perform the parts of the design verification circuit, the parts of these design verification circuits are incrementally implemented on the chips together with the simulator. It is possible to improve the execution speed by spatial mixing of emulation and simulation, and ultimately, by implementing all the circuits for design verification on the chips, it is possible to obtain the ultra-fast execution speed by emulation. In addition, unlike other methods, the emulation method presented in this patent utilizes an extended design verification circuit with a probe additional circuit, thereby providing complete visibility of all signal lines present in the design verification circuit even during emulation. It's also an important advantage.

In addition, the proposed method starts with a full simulation of the entire design verification circuit in the initial stage of design verification, and as the design verification proceeds, the simulation and the emulation for the rest of the design verification circuit are mixed. In the end, it is possible to perform the design verification through the full emulation of the entire circuit to be verified. In other words, if it is necessary to obtain the high-speed execution speed from the initial stage of design verification, emulation is performed by implementing one or more programmable elements for design verification by prototyping the entire circuit for design verification. Instead of re-implementing the entire new design-verification circuit that eliminates design errors on the chips, only the HDL code blocks with design errors are corrected so that these modified HDL code blocks are simulated and the remaining parts are continuously emulated. It is also possible.

Now, the method of performing the above-mentioned emulation and simulation spatially mixed will be described in more detail, and FIG. 4 will be used for this. 4 is a view schematically illustrating an example of a situation in which the entire design verification circuit is performed by simulation. As described above, the advantage of this method is that a designer may use a separate test bench to simulate the design verification circuit. What happens in the real world using the ICE method, without creating it, can be used as a test bench for reliable verification effectively. To this end, the design verification system software must be able to control and carry out not only the circuits to be verified by design but also the actual surroundings that form the ICE environment (that is, not only the simulator but also the ICE Even the environment is completely controlled by the design verification system software, and in this sense, the emulation in this patent is no different from the acceleration of simulation).

FIG. 5 is a view schematically showing an example of a situation in which a part of a design verification target circuit that was performed by simulation in FIG. 4 is performed by simulation while the other part is performed by emulation. As described above, FIG. The advantage is that in the early stage of design verification, most of the circuits for design verification are performed by simulation, and as the design verification proceeds, a large part of the circuits for design verification is gradually performed by emulation. On the contrary, in the early stage of design verification, most of the circuits for design verification are emulated, and only the parts of the circuit where design errors are found are instantaneously simulated using a systematic and automated method. It is that the preparation process can be significantly shortened for. To this end, the design verification system software must be able to fully control and carry out not only the partial circuits to be verified by design but also the actual surrounding environment forming the ICE environment and the remaining partial circuits to be verified by emulation. To this end, in the present invention, the system clock is generated in the design verification interface module and supplied to the ICE environment, and the simulation clock supplied to the simulation is also supplied to the simulator under the control of the system clock.

In particular, in the case of adopting a progressive prototyping technique using such an input / output probe method, the incremental design technique (or the recent) provided by FPGA vendors such as Xilinx and Altera or EDA tool vendors such as Synopsys, Synplicity, and Mentor Graphics When used together, the design tools employing the modular design method, instead of implementing the entire design verification circuit on the FPGA chip at once, can selectively and quickly implement only the desired design verification circuit portion at a specific point in time. As a result, by dividing the circuits to be verified for each module into modules, one or more modules are selected and gradually implemented in the FPGA chip, thereby minimizing correlation with other modules and quickly changing the performance of the modules from simulation to emulation. It is possible.

In addition, the present design verification method is similar to the "quick input / output probe device and the input / output probe method using the same and a mixed emulation / simulation method based on the same" (PCT application No. PCT / KR01 / 01092), which have been previously applied, through simulation. Re-compile RFPD for all other signal lines, as well as signal lines that can be probed through the output probe in any design verification circuit implemented in one or more RFPDs on any prototyping board or any PCB. 100% probe is possible without process. The omission of this recompilation process is of utmost importance in the debugging process, since the time required to compile the latest multi-million-gate RFPD requires as little as tens of minutes to hours. Therefore, one of the most important things in the debugging process for the circuit implemented in the RFPD is to enable rapid debugging by maximally suppressing the recompilation of the RFPD. When design verification is performed using the simulation and emulation together, 100% visibility of all signal lines present in the design verification target circuit, which is essential for debugging, is completely achieved even during emulation without recompiling the RFPD. It is another advantage of this incremental design verification method.

Other objects and advantages of the present invention in addition to the above object will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a diagram schematically showing a design verification apparatus according to the present invention composed of a design verification system software running on a server computer, a simulator, and a design verification interface module.

2 is a diagram schematically showing an example in which an output probe addition circuit is added to a design verification target circuit, and FIG. 3 is a diagram schematically showing an example in which an input probe addition circuit is added to a design verification target circuit.

The extended design verification target circuit generated by adding the probe additional circuit to the design verification target circuit is implemented in one or more RFPDs on an arbitrary prototyping board or an arbitrary PCB. In the process of performing the verification, when the transition to simulation is necessary at a certain time or when a certain situation occurs, the design verification system software detects this and stops emulation and the one or more RFPDs under normal control of the design verification system software are normal. When the probe clock is applied to the RFPD after switching from mode to output probe mode, the logic on the signal lines that are probed through one or more output probes connected to the output of one flip-flop in each of the one or more shift register array structures Values are passed through the design verification interface module. It is sent to the server computer. However, the input / output probe timing may be determined statically before emulation, and may be determined dynamically such as when a specific situation occurs during emulation, and the input / output dependent on the emulation situation such as when a specific situation occurs. In order to determine the probe time point, an external device such as a logic analyzer can be used to observe it and determine the input / output probe time point, or an additional input / output probe time detector circuit for detecting an operation state inside the RFPD is added. By outputting the I / O probe status, the design verification system software can detect and start the I / O probe. When the input / output probe point detector circuit is additionally added to the design verification circuit along with the probe additional circuit inside the RFPD, the automatic generation and addition of the input / output probe point detector circuit is also in charge of the design verification system software.

In the case of input probes, the design verification system software generates input probe data for one or more RFPDs on the prototyping board, then switches the operation mode to the input probe mode under the control of the design verification system software, and then the probe clock One or more input probe data transmitted from the server computer through the design verification interface module through one or more input probes logically connected to the input of one flip-flop present in each of the one or more shift register array structures applied to the RFPD. The input probe data stored in the flip-flops existing in each shift register array structure, and thus the input probe object is the output of the memory device (in the case of a latch, it is converted into an equivalent circuit using a flip-flop and a multiplexer). After applying it, For further details, see PCT Application No .: PCT / KR01 / 01092) .Flip-flops on the input probe can be synchronously set or reset, or asynchronously set or reset. Following a synchronous set or reset or asynchronous set or reset operation, a synchronous disable operation enables the input probe to be made on one or more RFPDs mounted on any prototyping board or any PCB. If the input probe target signal lines are an output or an input of a combination circuit, the shift register array structure such that each of the outputs of the flip-flops existing in each of the shift register array structures in which the input probe data is stored is connected to the corresponding input probe target signal lines. Arbitrary prototypes that control the selection input of the multiplexer at the output of each flip-flop Ping is able to be done in the input probe RFPD board or the at least one mounted on any PCB.

4 is a view schematically showing an example of a situation in which the entire design verification target circuit is performed by simulation, and FIG. 5 is a situation in which a part of the design verification target circuit is performed by simulation while the other part is performed by emulation. It is a figure which shows an example schematically. The part 92 of the design verification target circuit simulated throughout the design verification target circuit is a part of the design verification target circuit that requires 100% visibility to identify the cause of the design error, or the design modification is performed due to the design error. It may be a part of the design verification target circuit (simulation of the design verification target circuit in which the design correction is performed as such is possible after a very short compile time).

As described above, an object of the design verification apparatus and the design verification method using the same according to the present invention is to verify design by performing emulation and simulation of a large-scale digital system embodied in hardware for ultra-scale design verification. Even if the scale of the target circuit exceeds the limit of simulation, the design verification method using the above emulation and simulation can be applied to quickly verify the design. Specifically, it is not only possible to quickly find design errors, but also to fix these found design errors quickly.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (9)

A probe additional circuit for a design verification target HDL code implemented in one or more programmable devices mounted on an arbitrary prototyping board or an arbitrary PCB is added to the design verification target HDL code, and present in the design verification target HDL code. Enabling input / output probes for one or more specific signal lines, Implementing a circuit capable of input / output probing to one or more specific signal lines of the design verification target HDL code in the at least one programmable device, and performing the design verification target HDL code by emulation; A part of the design verification target HDL code to perform a simulation in the simulator, and The one or more specific signal lines present in the design verification target HDL code implemented in the one or more programmable devices at any one or more points in time during which the design verification target HDL code implemented in the one or more programmable devices is emulated. By performing the input / output probe on the at least one programmable device, the design verification target HDL code implemented in the at least one programmable element is performed by emulation and the part of the design verification target HDL code is performed by the simulation simultaneously through the input / output probe. Through the steps to ensure that A design verification method for obtaining visibility of the portion of the design verification target HDL code during execution. 1 that exists in the design verification target HDL code by adding an additional circuit for the design verification target HDL code to the design verification target HDL code implemented in one or more programmable elements mounted on any prototyping board or any PCB. Enabling the input / output probe for the above specific signal lines; Implementing a circuit capable of input / output probing to one or more specific signal lines of the design verification target HDL code in the at least one programmable device, and performing the design verification target HDL code by emulation; Performing a modification on a portion of the design verification target HDL code performed by emulation; Causing the modified design verification target HDL code to be simulated in a simulator; A circuit capable of input / output probing for the one or more specific signal lines present in the design-verification target HDL code implemented in the one or more programmable elements is applied to the one or more programmable elements at any one or more points in the process of performing emulation. By performing an input / output probe for the portion of the implemented design verification target HDL code, the design verification target HDL code implemented in the one or more programmable elements is performed by emulation and the portion of the modified design verification target HDL code. Through what is performed by this simulation is carried out simultaneously through the input-output probe, And emulation and simulation concurrent execution without re-implementing said portion of said modified design verification target HDL code to said one or more programmable devices. delete delete delete delete delete delete delete

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